Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendments filed on 12/11/2024 have been fully considered and are made of record.
Claims 1-6 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 and 5-6 are rejected under 35 U.S.C. 102(a1) as being anticipated by MAEDA et al. (Pub NO. WO 2020/255191 (A1); hereinafter Maeda; translation attached).
Regarding Claim 1, Maeda teaches an optical semiconductor integrated circuit having an optical circuit and an electrical circuit (circuit in Fig. 3; See [0037]-[0042]), comprising:
a plurality of electrical input/output terminals (input/output terminals 201/106 in Fig. 3; See [0037]-[0042]) disposed around at least one periphery of a chip region (disposed on periphery of chip region 105a in fig. 3; See [0037]-[0042]); and
one or more optical input/output terminals (optical input/output terminals 107 in fig. 3; See [0037]-[0042]) disposed around one periphery in which the plurality of electrical input/output terminals are not disposed (107’s are disposed on periphery on 105a where 106/201 are not disposed in Fig. 3; See [0037]-[0042]).
Regarding Claim 3, Maeda teaches the optical semiconductor integrated circuit according to claim 1, wherein the optical circuit includes a photodiode (photodiode 110 in fig. 3; See [0043]), and the high frequency signal output terminals of the photodiode are included in the plurality of electrical input/output terminals (See [0043]).
Regarding Claim 5, Maeda teaches the optical semiconductor integrated circuit according to claim 1, wherein the optical input/output terminal is a grating coupler which can input and output light toward the outside of the chip region (See [0030]-[0047]).
Regarding Claim 6, Maeda teaches the optical semiconductor integrated circuit according to claim 1, which is prepared using a silicon photonics technique (See [0002]-[0003]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda in view of Miyazaki et al. (Pub NO. US 2024/0319558 A1; hereinafter Miyazaki).
Regarding Claim 2, Maeda teaches the optical semiconductor integrated circuit according to claim 1. Maeda is silent about wherein the optical circuit includes a Mach-Zehnder interferometer type modulator, and the high frequency signal input terminals of the Mach-Zehnder interferometer type modulator are included in the plurality of electrical input/output terminals.
Miyazaki teaches wherein the optical circuit includes a Mach-Zehnder interferometer type modulator (Se [0062-[0067]), and the high frequency signal input terminals of the Mach-Zehnder interferometer type modulator are included in the plurality of electrical input/output terminals (See [0062]-[0067], [0072]-[0075]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Maeda by using the optical circuit includes a Mach-Zehnder interferometer type modulator, and the high frequency signal input terminals of the Mach-Zehnder interferometer type modulator are included in the plurality of electrical input/output terminals, as taught by Miyazaki in order to control a light wave propagating through the optical waveguide (Miyazaki; abstract).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda.
Regarding Claim 4, Maeda teaches the optical semiconductor integrated circuit according to claim 1, wherein a distance between the electrical input/output terminal closest to the one or more optical input/output terminals among the electrical input/output terminals disposed along a periphery orthogonal to the one periphery on which the one or more optical input/output terminals are disposed and an optical input/output point of the optical input/output terminal (See the electrical terminals 106 and optical terminals 107 in Fig. 3).
Maeda is silent about terminal is 250 pm or more.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use terminal is 250 pm or more, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 in order to faster, smaller, and lower-cost optical transceivers (Maeda [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyazaki et al. (Pub NO. US 2023/0367147 A1) discloses Optical Waveguide Element.
Long et al. (Pub NO. US 2009/0134905 A1) discloses System for Measuring Signal Path Resistance.
Zhang et al. (Pub NO. US 2009/0273007 A1) discloses Method of Testing Integrated Circuit Die.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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