DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This office action is FINAL.
Response to Arguments
Applicant’s arguments with respect to claim(s) [ 1-20 ] have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 20 is objected to because of the following informalities: [the claim recites "wherein wherein" ]. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-6, 8-16, 18-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Lin et al. (US Pub No. 20170179980 IDS), hereinafter "Lin", in view of Bahns (US Pub No. 20150046448) ].
As per claim 1, Lin significantly teaches a receiver in a communication system, the receiver comprising (the techniques described herein are employed in a transceiver and instead of being written to or read from storage, the data is transmitted and received over a wired and/or wireless channel. [Lin PP 0029]): a detector configured to receive a codeword comprising bits, and to determine a list of respective reliability values for the bits of the codeword (Detector 130 performs detection on the received data and outputs decision and/or reliability information corresponding to one or more bits in a codeword. For example, a soft-output detector outputs reliability information and a decision for each detected bit. [Lin PP 0030]); and
a decoder coupled to the detector and configured to: receive, from the detector, the codeword and the reliability values (The decision and/or reliability information is passed to TPC decoder 140 which performs TPC decoding using the decision and/or reliability information. [Lin PP 0031]);
identify, from the CDF, a group including a specific number of least reliable bits (LRBs) that have the reliability values within a threshold range (The decoder may first compare the received LLR values with the first threshold t 1 to select N 1 least reliable bits. If the number of selected least reliable bits (e.g., N 1 ) is smaller than L, the decoder may then compare the received LLR values with a larger threshold value (e.g., the second threshold t 2 ) to select more of the least reliable bits [Lin PP 0053]); and
determine a location of each LRB of the group in the codeword (At 740 , the decoder stores the index information into a first in first out (FIFO) buffer. [Lin PP 0054], the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword [Lin PP 0047]).
Lin does not explicitly teach “compute a cumulative distribution function[[s]] (CDF) of the reliability values for the codeword, the CDF being a cumulative histogram of reliability information comprising CDF values corresponding to CDF indices, wherein each CDF index represents a maximum reliability value and each CDF value counts a total number of the bits whose reliability values are less than or equal to the corresponding CDF index;”
However, Bahns, in an analogous art, teaches compute a cumulative distribution function[[s]] (CDF) of the reliability values for the codeword (the anti-histogram unit 230 may generate an anti-histogram based on the histogram, where an anti-histogram is an integral of the histogram. The anti-histogram may provide a count of the cumulative quantity of members that are in the bins, starting from either the highest bin or the lowest [Bahns PP 0036]), the CDF being a cumulative histogram of reliability information comprising CDF values corresponding to CDF indices (In FIG. 3B, the bins are indexed with these values, and the histogram unit 220 assigns each member of the input set 300 to the bin with the matching value for the most significant 3 bits of that member. [Bahns PP 0035], The anti-histogram may provide a count of the cumulative quantity of members that are in the bins [Bahns PP 0036]), wherein each CDF index represents a maximum reliability value (the anti-histogram unit 230 may determine which bin holds the threshold value. The threshold value is the value of the member that separates the members belonging in the output (i.e., the top 8 values in this example) from the members that do not belong in the output. [Bahns PP 0037]) and each CDF value counts a total number of the bits whose reliability values are less than or equal to the corresponding CDF index (an anti-histogram is an integral of the histogram. The anti-histogram may provide a count of the cumulative quantity of members that are in the bins, starting from either the highest bin or the lowest … the anti-histogram unit 230 starts counting from the highest bin if the selection system 200 seeks to select the topmost members of the input set 300 , and starts from the lowest bin if the selection system 200 seeks to select the bottommost members. In the example of FIGS. 3A-3D, the selection unit 200 seeks to provide the top 8 members of the input set 300 . Thus, the anti-histogram may begin counting members in the histogram starting from the highest bin. [Bahns PP 0036]);
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 2, Lin significantly teaches wherein a reliability value of the reliability values is an absolute value of a log likelihood ratio (LLR) (a log-likelihood ratio (LLR) where the sign indicates the decision (e.g., a positive value corresponds to a “1” decision and a negative value corresponds to a “0” decision) and the magnitude indicates how sure or certain the detector is in that decision (e.g., a large magnitude indicates a high reliability or certainty). [Lin PP 0030]).
As per claim 3, Lin significantly teaches wherein the decoder is further configured to decode the codeword based on the identified LRBs and locations associated with the LRBs (the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword … The GBF block 570 may select S bits (S=1, . . . , L) among the L bits to flip. [Lin PP 0047], at 610 , the device chooses a plurality of least reliable bits based on the LLR values. at 620 , the device generates a one or more flipped patterns using the GBF block 570 [Lin PP 0051]).
As per claim 4, Lin does not explicitly teach “wherein the decoder is further configured to update the CDF after decoding the codeword, wherein to update the CDF, the decoder is further configured to prepare the CDF for a subsequent codeword to be decoded.”
However, Bahns, in an analogous art, teaches wherein the decoder is further configured to update the CDF after decoding the codeword (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]), wherein to update the CDF, the decoder is further configured to prepare the CDF for a subsequent codeword to be decoded (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]).
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 5, Lin significantly teaches wherein the decoder is further configured to: update the LLRs for the codeword (the data and syndrome values will be updated according to the flipped and decoded patterns. In one embodiment, updated data value may be written in data chunk memory 595 and updated syndrome value may be written in syndrome memory 585 [Lin PP 0050]); and
write the LLRs in memory (the decoder includes LLR memory block 510 [Lin PP 0046], updated data value may be written in data chunk memory 595 [Lin PP 0050]).
As per claim 6, Lin significantly teaches wherein the decoder is further configured to read the LLRs from the memory when decoding a next codeword at a later time (the decoder includes LLR memory block 510 [Lin PP 0046], the TPC decoder may iteratively perform decoding on the first dimension and/or second dimension codewords to correct errors. [Lin PP 0044], at 610 , the device chooses a plurality of least reliable bits based on the LLR values. [Lin PP 0051]).
As per claim 8, Lin does not explicitly teach “wherein the decoder is further configured to build the CDF on an entire sequence of the codeword or a partial sequence of the codeword.”
However, Bahns, in an analogous art, teaches wherein the decoder is further configured to build the CDF on an entire sequence of the codeword or a partial sequence of the codeword (The number of passes may generally be inversely proportionate to the number of bins … If it is determined that no more than four passes should be made through the data, then each pass may handle 8 of those 32 bits. [Bahns PP 0031], resolving the threshold value sufficiently need not mean resolving it exactly (i.e., resolving each and every bit of the threshold value) in every case. [Bahns PP 0045]).
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 9, Lin significantly teaches wherein the decoder is configured to identify the LRBs (The decision and/or reliability information is passed to TPC decoder 140 which performs TPC decoding using the decision and/or reliability information. [Lin PP 0031], the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword. [Lin PP 0047])
achieved when decoding processing is separated between write and read operations (the TPC decoder may iteratively perform decoding on the first dimension and/or second dimension codewords to correct errors [Lin PP 0044], the data and syndrome values will be updated according to the flipped and decoded patterns. In one embodiment, updated data value may be written in data chunk memory 595 and updated syndrome value may be written in syndrome memory 585 [Lin PP 0050]).
Lin does not explicitly teach “by applying a two-pass algorithm”
However, Bahns, in an analogous art, teaches by applying a two-pass algorithm (At block 420 , a histogram is generated on the most significant bits of the input set that have yet to be resolved. At block 430 , an anti-histogram is generated based on the histogram. At decision block 440 , it is determined whether a threshold value can be sufficiently resolved based on the prior histogram and anti-histogram. If not, the method returns to block 420 to begin an additional pass through the input set 300 . [Bahns PP 0048])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a multi-pass histogram and anti-histogram selection, in order to perform the LRB identification in a first pass when the LLR values are written to memory and in a second pass when the LLR values are read from memory, thereby separating the identification processing between write and read operations (At block 420 , a histogram is generated on the most significant bits of the input set that have yet to be resolved. At block 430 , an anti-histogram is generated based on the histogram. At decision block 440 , it is determined whether a threshold value can be sufficiently resolved based on the prior histogram and anti-histogram. If not, the method returns to block 420 to begin an additional pass through the input set 300 . [Bahns PP 0048]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 10, Lin significantly teaches wherein the codeword is encoded with an error correction code, and the detector is configured to receive the codeword from an encoder via a communication channel (The term “error correcting code (ECC)” is used herein to refer to a codeword that is generated by a process of adding redundant data, or parity data, to a message [Lin PP 0026], TPC encoder 110 receives information bits … TPC encoded data is output by TPC encoder 110 [Lin PP 0029], the data is transmitted and received over a wired and/or wireless channel [Lin PP 0029]).
As per claim 11, Lin significantly teaches A method comprising: receiving a codeword comprising bits (Detector 130 performs detection on the received data [Lin PP 0030], the techniques described herein are employed in a transceiver and instead of being written to or read from storage, the data is transmitted and received over a wired and/or wireless channel. [Lin PP 0029]);
determining respective reliability values for the bits of the codeword (a soft-output detector outputs reliability information and a decision for each detected bit. [Lin PP 0030]);
identifying, from the CDF, a group including a specific number of least reliable bits (LRBs) that have the reliability values within a threshold range (The decoder may first compare the received LLR values with the first threshold t 1 to select N 1 least reliable bits. If the number of selected least reliable bits (e.g., N 1 ) is smaller than L, the decoder may then compare the received LLR values with a larger threshold value (e.g., the second threshold t 2 ) to select more of the least reliable bits [Lin PP 0053]); and
determining a location of each LRB of the group in the codeword (At 740 , the decoder stores the index information into a first in first out (FIFO) buffer. [Lin PP 0054], the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword [Lin PP 0047]).
Lin does not explicitly teach “computing a cumulative distribution function (CDF) of the reliability values for the codeword, the CDF being a cumulative histogram of reliability information comprising CDF values corresponding to CDF indices, wherein each CDF index represents a maximum reliability value and each CDF value counts a total number of the bits whose reliability values are less than or equal to the corresponding CDF index;”
However, Bahns, in an analogous art, teaches computing a cumulative distribution function (CDF) of the reliability values for the codeword (the anti-histogram unit 230 may generate an anti-histogram based on the histogram, where an anti-histogram is an integral of the histogram. The anti-histogram may provide a count of the cumulative quantity of members that are in the bins, starting from either the highest bin or the lowest [Bahns PP 0036]), the CDF being a cumulative histogram of reliability information comprising CDF values corresponding to CDF indices (In FIG. 3B, the bins are indexed with these values, and the histogram unit 220 assigns each member of the input set 300 to the bin with the matching value for the most significant 3 bits of that member. [Bahns PP 0035], The anti-histogram may provide a count of the cumulative quantity of members that are in the bins [Bahns PP 0036]), wherein each CDF index represents a maximum reliability value (the anti-histogram unit 230 may determine which bin holds the threshold value. The threshold value is the value of the member that separates the members belonging in the output (i.e., the top 8 values in this example) from the members that do not belong in the output. [Bahns PP 0037]) and each CDF value counts a total number of the bits whose reliability values are less than or equal to the corresponding CDF index (an anti-histogram is an integral of the histogram. The anti-histogram may provide a count of the cumulative quantity of members that are in the bins, starting from either the highest bin or the lowest … the anti-histogram unit 230 starts counting from the highest bin if the selection system 200 seeks to select the topmost members of the input set 300 , and starts from the lowest bin if the selection system 200 seeks to select the bottommost members. In the example of FIGS. 3A-3D, the selection unit 200 seeks to provide the top 8 members of the input set 300 . Thus, the anti-histogram may begin counting members in the histogram starting from the highest bin. [Bahns PP 0036]);
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 12, Lin significantly teaches wherein a reliability value of the reliability values is an absolute value of a log likelihood ratio (LLR) (a log-likelihood ratio (LLR) where the sign indicates the decision (e.g., a positive value corresponds to a “1” decision and a negative value corresponds to a “0” decision) and the magnitude indicates how sure or certain the detector is in that decision (e.g., a large magnitude indicates a high reliability or certainty). [Lin PP 0030]).
As per claim 13, Lin significantly teaches further comprising decoding the codeword based on the identified LRBs and locations associated with the LRBs (the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword … The GBF block 570 may select S bits (S=1, . . . , L) among the L bits to flip. [Lin PP 0047], at 610 , the device chooses a plurality of least reliable bits based on the LLR values. at 620 , the device generates a one or more flipped patterns using the GBF block 570 [Lin PP 0051]).
As per claim 14, Lin does not explicitly teach “further comprising: updating the CDF after decoding the codeword, wherein the updating comprises preparing the CDF for a subsequent codeword to be decoded.”
However, Bahns, in an analogous art, teaches further comprising: updating the CDF after decoding the codeword (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]), wherein the updating comprises preparing the CDF for a subsequent codeword to be decoded (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]).
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 15, Lin significantly teaches further comprising: updating the LLRs for the codeword (the data and syndrome values will be updated according to the flipped and decoded patterns. In one embodiment, updated data value may be written in data chunk memory 595 and updated syndrome value may be written in syndrome memory 585 [Lin PP 0050]); and
writing the LLRs in memory (the decoder includes LLR memory block 510 [Lin PP 0046], updated data value may be written in data chunk memory 595 [Lin PP 0050]).
As per claim 16, Lin significantly teaches further comprising reading the LLRs from the memory when decoding a next codeword at a later time (the decoder includes LLR memory block 510 [Lin PP 0046], the TPC decoder may iteratively perform decoding on the first dimension and/or second dimension codewords to correct errors. [Lin PP 0044], at 610 , the device chooses a plurality of least reliable bits based on the LLR values. [Lin PP 0051]).
As per claim 18, Lin does not explicitly teach “further comprising building the CDF on an entire sequence of the codeword or a partial sequence of the codeword.”
However, Bahns, in an analogous art, teaches further comprising building the CDF on an entire sequence of the codeword or a partial sequence of the codeword (The number of passes may generally be inversely proportionate to the number of bins … If it is determined that no more than four passes should be made through the data, then each pass may handle 8 of those 32 bits. [Bahns PP 0031], resolving the threshold value sufficiently need not mean resolving it exactly (i.e., resolving each and every bit of the threshold value) in every case. [Bahns PP 0045]).
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a histogram and anti-histogram unit, in order to reduce the hardware cost and latency associated with selecting least reliable bits (The above approaches are generally not well suited to hardware implementations. [Bahns PP 0004]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 19, Lin significantly teaches wherein identifying the LRBs (The decision and/or reliability information is passed to TPC decoder 140 which performs TPC decoding using the decision and/or reliability information. [Lin PP 0031], the LRB selection block 580 selects L least reliable bits based on received LLR values from the bits in the codeword. [Lin PP 0047]),
achieved when decoding processing is separated between write and read operations (the TPC decoder may iteratively perform decoding on the first dimension and/or second dimension codewords to correct errors [Lin PP 0044], the data and syndrome values will be updated according to the flipped and decoded patterns. In one embodiment, updated data value may be written in data chunk memory 595 and updated syndrome value may be written in syndrome memory 585 [Lin PP 0050]).
Lin does not explicitly teach “comprises applying a two-pass algorithm”
However, Bahns, in an analogous art, teaches comprises applying a two-pass algorithm (At block 420 , a histogram is generated on the most significant bits of the input set that have yet to be resolved. At block 430 , an anti-histogram is generated based on the histogram. At decision block 440 , it is determined whether a threshold value can be sufficiently resolved based on the prior histogram and anti-histogram. If not, the method returns to block 420 to begin an additional pass through the input set 300 . [Bahns PP 0048])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of a multi-pass histogram and anti-histogram selection, in order to perform the LRB identification in a first pass when the LLR values are written to memory and in a second pass when the LLR values are read from memory, thereby separating the identification processing between write and read operations (At block 420 , a histogram is generated on the most significant bits of the input set that have yet to be resolved. At block 430 , an anti-histogram is generated based on the histogram. At decision block 440 , it is determined whether a threshold value can be sufficiently resolved based on the prior histogram and anti-histogram. If not, the method returns to block 420 to begin an additional pass through the input set 300 . [Bahns PP 0048]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
As per claim 20, Lin significantly teaches wherein wherein receiving the codeword comprises receiving the codeword from an encoder via a communication channel (TPC encoder 110 receives information bits … TPC encoded data is output by TPC encoder 110 [Lin PP 0029], the data is transmitted and received over a wired and/or wireless channel. [Lin PP 0029]).
Claim(s) [ 7, 17 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Lin, in view of Bahns, in further view of Gareau et al (US Pub No. 20240007225), hereinafter "Gareau" ].
As per claim 7, Lin significantly teaches when writing the LLRs to memory (updated data value may be written in data chunk memory 595 [Lin PP 0050], the decoder includes LLR memory block 510 [Lin PP 0046]).
Lin does not explicitly teach “wherein the decoder is an open forward error correction (oFEC) decoder, … and the oFEC decoder is configured to build the CDF”
However, Bahns, in an analogous art, teaches and the oFEC decoder is configured to build the CDF (the anti-histogram unit 230 may generate an anti-histogram based on the histogram [Bahns PP 0036])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of building the histogram when data is written, in order to build the cumulative distribution function at the time the LLR values are written to memory so that a separate pass through the data is avoided (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
Lin in view of Bahns do not explicitly teach “wherein the decoder is an open forward error correction (oFEC) decoder”
However, Gareau, in an analogous art, teach wherein the decoder is an open forward error correction (oFEC) decoder (openFEC: a block-based encoder and iterative Soft Decision (SD) [Gareau Table PP 0017], OFEC includes a block-code-based encoder and iterative soft-decision-based decoder [Gareau PP 0020])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin in view of Bahns to incorporate Gareau's teaching of an open forward error correction (oFEC) decoder, in order to provide a block-code-based encoder and iterative soft-decision decoder having a known net coding gain (OFEC includes a block-code-based encoder and iterative soft-decision-based decoder, such as with an overhead of 15.3% and a Net Coding Gain (NCG) of 11.1 dB for Quadrature Phase Shift Keying (QSPK) and 11.6 dB for 16-Quadrature Amplitude Modulation (16QAM) after three soft-decision iterations, with pre-FEC BER threshold of ˜2.0×10−2 [Gareau PP 0020]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to the Lin in view of Bahns invention.
As per claim 17, Lin significantly teaches when writing the LLRs to memory by (updated data value may be written in data chunk memory 595 [Lin PP 0050], the decoder includes LLR memory block 510 [Lin PP 0046])
Lin does not explicitly teach “further comprising building the CDF … an open forward error correction (oFEC) decoder.”
However, Bahns, in an analogous art, teaches further comprising building the CDF (the anti-histogram unit 230 may generate an anti-histogram based on the histogram [Bahns PP 0036])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin to incorporate Bahns teaching of building the histogram when data is written, in order to build the cumulative distribution function at the time the LLR values are written to memory so that a separate pass through the data is avoided (During anti-histogramming, all addresses of the histogram bin memories may be sequenced and zeroed out in preparation for the next use. [Bahns PP 0057]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lin's invention.
Lin in view of Bahns do not explicitly teach “an open forward error correction (oFEC) decoder”
However, Gareau, in an analogous art, teach an open forward error correction (oFEC) decoder (openFEC: a block-based encoder and iterative Soft Decision (SD) [Gareau Table PP 0017], OFEC includes a block-code-based encoder and iterative soft-decision-based decoder [Gareau PP 0020])
Therefore, It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the decoder disclosed by Lin in view of Bahns to incorporate Gareau's teaching of an open forward error correction (oFEC) decoder, in order to provide a block-code-based encoder and iterative soft-decision decoder having a known net coding gain (OFEC includes a block-code-based encoder and iterative soft-decision-based decoder, such as with an overhead of 15.3% and a Net Coding Gain (NCG) of 11.1 dB for Quadrature Phase Shift Keying (QSPK) and 11.6 dB for 16-Quadrature Amplitude Modulation (16QAM) after three soft-decision iterations, with pre-FEC BER threshold of ˜2.0×10−2 [Gareau PP 0020]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to the Lin in view of Bahns invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
