CTNF 18/874,211 CTNF 81991 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/12/2024 and 2/25/2026 have been considered by the examiner. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. A title such as the following is suggested: A Semiconductor Device Performing Temperature Estimation. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim (s) 1-5 and 7-10 are rejected under 35 U.S.C. 102 a1 as being anticipated by Kawai (US 2021/0072297) . With respect to claim 1, Kawai discloses a semiconductor device that drives and controls a semiconductor element, the semiconductor element having a positive electrode terminal (Fig. 4 drain M0), a negative electrode terminal (Fig. 4 source M0), and a control terminal (Fig. 4 gate M0), a drive voltage (Fig. 4 Vg) for controlling a main current (Fig. 4 current drain to source of M0) flowing between the positive electrode terminal and the negative electrode terminal being applied to the control terminal, the semiconductor device comprising: a driver circuit (Fig. 4 DR0) to supply the drive voltage to the control terminal to shift the semiconductor element between an on state and an off state; a current controller (Fig. 4 OSC) provided to pass a current (Fig. 4 I) of pulse shape (Fig 4 sinusoidal pulses) between the control terminal and the negative electrode terminal; a timing controller (Fig. 4 CONTROL CIRCUIT CTR2) to control a timing of supply of the current by the current controller; a peak detection circuit (Fig. 4 20-21,Ao,M1-M2) to output a peak value (Fig. 4 Vp) of an input voltage (Fig. 4 Vg) the input voltage being a potential difference of the control terminal (Fig. 4 gate M0) or the negative electrode terminal with respect to a reference potential (Fig. 4 ground voltage) in a current supply period (Fig. 12 period of chirp) by the current controller; a voltage detector (as in Fig. 5 10) to sample an output voltage of the peak detection circuit; and a temperature estimator (as in Fig. 5 11) to calculate an estimated temperature (paragraph 61) of the semiconductor element based on a detection voltage by the voltage detector, wherein the timing a controller causes the current controller to operate to provide the current supply period during at least one of an on-period after the semiconductor element shifts to the on state; and an off-period (Fig. 12 Vg low) after the semiconductor element shifts to the off state. With respect to claim 2, Kawai discloses the semiconductor device according to claim 1, wherein the peak detection circuit includes: a first diode (Fig. 4 DO0) having an anode connected to a first node, the first node being electrically connected to the control terminal or the negative electrode terminal; a capacitor (Fig. 4 C0) connected between a second node connected to a cathode of the first diode and a node supplying the reference potential (Fig. 4 ground symbol); and a discharge switch element or a discharge resistance (Fig. 4 R0) to discharge the capacitor. With respect to claim 3, Kawai discloses the semiconductor device according to claim 2, wherein the peak detection circuit further includes an impedance conversion circuit (Fig. 4 A0) arranged at least one of between the first node and the anode of the first diode; and between the second node (Fig. 4 cathode) and the voltage detector (Fig. 4 voltage detector connected to pout as in Figure 5). With respect to claim 4, Kawai discloses the semiconductor device according to claim 3, wherein the peak detection circuit includes, as the impedance conversion circuit (Fig. 7 A2), an operational amplifier (Fig. 7 A2) connected in a voltage follower connection manner between the first node and the anode of the first diode, and the peak detection circuit further includes a second diode (Fig. 7 M4 diode mode) inserted into and connected to a return path (Fig. 7 return path from the output of A2 to the inverting input of A2) of the voltage follower connection and causing a voltage drop equivalent to that of the first diode (Fig. 7 M3 diode mode). With respect to claim 5, Kawai discloses the semiconductor device according to claim 1, wherein the timing controller provides a plurality of the current supply periods (Fig. 12 chirp periods) during the at least one of the on-period and the off-period (Fig. 12 Vg off period). With respect to claim 7, Kawai discloses the semiconductor device according to claim 1, wherein the current controller is arranged at a position (Fig. 4 OSC arranged to ground symbol) where the current is supplied from the negative electrode terminal side (Fig. 4 Vss side of M0) of the semiconductor element. With respect to claim 8, Kawai discloses the semiconductor device according to claim 1, wherein the current controller is arranged at a position (Fig. 4 OSC arranged at Vg) where the current is supplied from the control terminal side (Fig. 4 gate of M0) of the semiconductor element. With respect to claim 9, Kawai discloses the semiconductor device according to claim 1, wherein the current of pulse shape has a predetermined amplitude (Fig. 2 I amplitude), the current supply period is provided to have a predetermined time length (Fig. 2 length of chirp), and the temperature estimator calculates the estimated temperature (paragraph 20) using a resistance value (Fig. 4 Rg) determined from the detection voltage and the amplitude of the current in the current supply period, and information indicating a preliminarily determined (paragraph 61) relationship between a temperature of the semiconductor element and the resistance value. With respect to claim 10, Kawai discloses a power conversion device comprising: a main conversion circuit (paragraph 61, “power circuit)” having the semiconductor device (paragraph 31, “power device”) as recited in claim 1 and a semiconductor element (Fig. 4 M0) driven and controlled by the semiconductor device (Fig. 4 102), the main conversion circuit converting and outputting input electric power (power circuit converts input power to output power), and a control circuit (Fig. 4 control circuit of the power circuit to create gate signal to driver DR0 not shown) to output a control signal (Fig. 4 input to DR0 not shown) for controlling power conversion by the main conversion circuit to the main conversion circuit . Allowable Subject Matter Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 6, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the timing controller repeatedly provides a plurality of the current supply periods within a thermal resistance measurement period in which the semiconductor element is maintained off, and the semiconductor device hither comprises: a main current detector to detect the main current of the semiconductor element; a main voltage detector to detect a main voltage between the positive electrode terminal and the negative electrode terminal of the semiconductor element; and a thermal resistance calculator to calculate a power loss for each switching cycle that occurs in the semiconductor element before the thermal resistance measurement period, and calculate a thermal resistance of the semiconductor element based on the calculated power loss and a variation of the estimated temperature calculated for each of the plurality of the current supply periods. The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Barrenscheen (US 10,972,088), Kawai (US 2020/0091907), Wang (US 2019/0376850), Singh (US 2016/0252402) and Melkonyan (US 2020/0350904) disclose temperature estimation . Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HARRY R BEHM/Primary Examiner, Art Unit 2838 Application/Control Number: 18/874,211 Page 2 Art Unit: 2838 Application/Control Number: 18/874,211 Page 3 Art Unit: 2838 Application/Control Number: 18/874,211 Page 4 Art Unit: 2838 Application/Control Number: 18/874,211 Page 5 Art Unit: 2838
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