DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 12-20 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Porret et al. (US 20060040628) in view of Gunwoo et al. (KR 102077402), Applicant’s submitted IDS.
As to claim 1, Porret et al.’s figure 4 shows a filter circuit comprises a variable capacitor circuit (C1A,S1A-can,SnA) connected in parallel with inductor L1A. The figure fails to show the structure of the variable capacitor circuit as claimed. However, Gunwoo et al.’s figure 2 shows a variable capacitor circuit that is capable of reducing voltage stress. It would have been obvious to one having ordinary skill in the art to use Gunwoo et al.’s variable capacitor circuit for Porret et al.’s variable capacitor circuit for the purpose of reducing voltage stress. Thus, the modified Porret et al.’s 4 shows: an impedance adjustment circuit configured to adjust an impedance by adjusting an equivalent capacitance, the impedance adjustment circuit comprising: a capacitor (Gunwoo et al.’s C1 used in Porret et al.’s variable capacitor circuit); a unit leg (Gunwoo et al.’s remaining elements) configured to change the equivalent capacitance according to a connection with the capacitor; a control unit (not shown that drives Q1 and Q2) configured to control the leg to change the equivalent capacitance; and an inductor (Porret et al.’s L1A) and a compensation voltage source (Porret et al.’s V2. ¶0041 teaches that V2 can be any DC voltage value. It is inherent that a voltage source V2 is connected to ground V1, e.g., Gunwoo et al. shows that voltage source -VPIN connected to ground) connected in parallel with the leg.
As to claim 2, the modified Porret et al.’s figure shows that the unit leg includes: an adjustment capacitor (Gunwoo et al.’s Cvar) that has one electrode connected to a reference voltage rail and is equivalently connected to the capacitor(C1) to adjust the equivalent capacitance; a leg voltage source (Gunwoo et al.’s VPIN); two switches (Q1 and Q2) connected in series with the leg voltage source; a first inductor (Gunwoo et al.’s Lchoke) having one electrode connected to a node to which the two switches are connected and the other electrode connected to the other electrode of the adjustment capacitor; and a diode (GunWoo et al.’s DPIN) connected to a radio frequency (RF) rail and having an anode to which an RF voltage is provided and a cathode connected to the other electrode of the first inductor.
As to claim 3, the modified Porret et al.’s figure shows that the capacitor (Gunwoo et al.’s C1) has one electrode connected to the RF rail and the other electrode connected to the reference voltage rail.
As to claim 4, since the magnitude of Gunwoo et al.’s +VPIN is silenced, any value can be selected for VPIN. Selecting a voltage provided by the leg voltage source to be greater in magnitude than the RF voltage provided to the RF rail is seen as an obvious design preference to ensure optimum performance, i.e., ensuring diode DPIN is turned off when Q2 is on, MPEP 2144.05.
As to claim 5, the modified Porret et al.’s figure shows that the compensation voltage source (any selected value for V2) compensates for a voltage drop when the switch is turned on and a forward voltage drop of the diode.
As to claim 6, the modified Porret et al.’s figure shows that the adjustment capacitor is connected in parallel with the capacitor through the diode, so that the equivalent capacitance is adjusted.
As to claim 7, the modified Porret et al.’s figure shows that the two switches include a first switch (Gunwoo et al.’s Q1) connected to the reference voltage rail and a second switch (Q2) connected to the leg voltage source, and when the second switch is turned off and the first switch is turned on, the adjustment capacitor and the capacitor are equivalently connected in parallel, so that the equivalent capacitance is adjusted.
As to claim 8, the modified Porret et al.’s figure shows that when the first switch is turned off and the second switch is turned on, the connection between the adjustment capacitor and the capacitor is equivalently cut off.
As to claim 12, the modified Porret et al.’s figure shows that the diode is a P-type-intrinsic- N-type (PIN) diode.
Claims 13-20 and 24 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim(s) 9-11 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Porret et al. (US 20060040628) in view of Gunwoo et al. (KR 102077402) and Morii et al. (US 20190288683).
As to claim 9, the modified Porret et al.’s figure fails to show that the unit leg is provided as a plurality of unit legs connected in parallel. However, Morri et al.’s figures 2 and 6 shows a similar device that its unit leg is provided as a plurality of unit legs connected in parallel. It would have been obvious to one having ordinary skill in the art to plurality of unit legs connected in parallel with Porret et al.’s unit leg for the purpose of achieving desired capacitance precisely.
As to claim 10, capacitors having different capacitances connected in parallel is well known in the art. It would have been obvious to one having ordinary skill in the art to set the capacitors included in the plurality of unit legs have different capacitances for the purpose of achieving desired total capacitance.
As to claim 11, the modified Porret et al.’s figure shows the control unit controls the adjustment capacitor included in one of the plurality of unit legs to be equivalently connected to the capacitor.
Claims 21-23 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13, 15 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gunwoo et al. (KR 102077402 B1).
As to claim 13, Gunwoo et al.’s figure 2 shows an impedance adjustment circuit configured to adjust an impedance by adjusting an equivalent capacitance, the impedance adjustment circuit comprising: a capacitor (C1); a unit leg (remaining elements) configured to change the equivalent capacitance according to a connection with the capacitor; and a control unit (not shown that controls Q1 and Q2) configured to control the leg to change the equivalent capacitance, wherein the unit leg includes a diode (DPIN) that has an anode connected to a radio frequency (RF) rail and conducts to change the equivalent capacitance when the control unit controls the leg to increase the equivalent capacitance.
As to claim 15, figure 2 shows that the capacitor has one electrode connected to the RF rail and the other electrode connected to a reference voltage rail.
As to claim 24, figure 2 shows that the diode is a P-type-intrinsic- N-type (PIN) diode.
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/QUAN TRA/
Primary Examiner
Art Unit 2843
Prosecution Insights