DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. This communication is responsive to Application No. 18/874,421 filed on December 12, 2024. Claims 1-19 are subject to examination.
Information Disclosure Statement (IDS)
3. The IDS submitted on 03/12/25 has been entered and considered by the Examiner.
Claim Objections/Suggestions
4. Following claims are objected to because of the following informalities:
in claim 1, “and configured to” (line 8) should be replaced with “and the PFD-CPC circuit is configured to”; similar objection applies to claim 13; in addition, in claim 13, “circuit, comprising” (line 2) should be replaced with “circuit, the method comprising”;
claim 11 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 2; when two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m);
in claims 14-17, “voltage-controlled oscillator (VCO)” should be replaced with “VCO”;
in claim 18, “the reconfigurable charge pump controller (CPC)” (line 2) should be replaced with “the CPC”; and
in claim 19, “the multi-phase phase frequency detector (PFD)” (line 1) should be replaced with “the PFD”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites a limitation “the output of the divider” (line 6). There is insufficient antecedent basis for this limitation in the claim. Hence, renders claim 1 and its dependent claims indefinite.
Claim 13 recites limitations “phase noise”, “jitter contribution”, “one or more forward path loop components” and “a targeted frequency band” (lines 9-10) and “phase noise”, “jitter contribution”, “one or more forward path loop components” and “a targeted frequency band” (lines 13-14). It is not clear whether said limitations “phase noise”, “jitter contribution”, “one or more forward path loop components” and “a targeted frequency band” in lines 13-14 are different from or the same as “phase noise”, “jitter contribution”, “one or more forward path loop components” and “a targeted frequency band” as recited in line 9-10. Hence, renders claim 13 and its dependent claims indefinite.
Claims 14-15 recite "a voltage-controlled oscillator (VCO)". It is not clear whether said “voltage-controlled oscillator (VCO)” are different from or the same as "a voltage-controlled oscillator (VCO)" as recited in line 12 of claim 13.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
I. Determining the scope and contents of the prior art.
II. Ascertaining the differences between the prior art and the claims at issue.
III. Resolving the level of ordinary skill in the pertinent art.
IV. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. Claims 1-2, 4-11 and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li (“Fast locking adaptive PLL using Dual-Edge Phase-Frequency Detector” ©2015 –Attached as an NPL) and in view of Ng (US 10,819,349 B2).
Regarding claims 1 & 13, Li teaches a wide-band, multi-phase (Figure 4: Wide-Bandwidth, Dual-Edge Phase Frequency Detector (DE-PFD) & Narrow-Bandwidth, Single-Edge Phase Frequency Detector (SE-PFD)) phase-locked loop (PLL) circuit (Figure 1: Proposed PLL) comprising: a voltage-controlled oscillator (VCO) having an output (Figure 1: VCO & Output); a divider circuit coupled to the output of the VCO (Figure 1: ÷N); and a reconfigurable and programmable multi-phase phase frequency detector (PFD) and reconfigurable charge pump controller (CPC) (PFD-CPC) coupled to the output of the divider circuit (Figure 1: DE-PFD, Charge Pump, Bandwidth Control Unit (BCU), Section 3.2.1. Charge pump control circuit & Section 3.2.3. PFD control circuit: a value of the DE-PFD is adjusted by the programmable count selector), wherein the PFD-CPC includes a multi-phase PFD (Figure 1: DE-PFD) and a plurality of identical slices of the reconfigurable CPC (Figure 9: the charge pump of the proposed PLL & upper/lower 3Icp, Icp, CPset) and configured to operate in either single-phase (Figure 4: SE-PFD) or multi-phase mode (Figure 4: DE-PFD) to reduce phase noise and jitter contribution of one or more forward path loop components within a targeted frequency band (Section 2, Second Paragraph: when the phase difference is… DE-PFD is switched to the SE-PFD to reduce the noise and jitter). Li further teaches additional limitations, with regard to claim 13, i.e., “providing a high-frequency reference signal…” (Figure 1: 2Fref) and “maximizing bandwidth and suppressing phase noise and jitter contribution…” (Section 2, Second Paragraph: when the phase difference is… DE-PFD is switched to the SE-PFD to reduce the noise and jitter & Third Paragraph: the locking state detection and the bandwidth control are accomplished by using the DE-PFD and the BCU to control the loop filter resistor to keep the PLL stable). Although Li teaches PFD-CPC, Li does not explicitly disclose a PFD-CPC circuit. In a related field of endeavor Ng discloses a PFD-CPC circuit (Figures 6A & 7A: 406 PFD+CP). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize Li’s PFD-CPC to include a PFD-CPC circuit as in Ng. One of ordinary skill in the art would be motivated to do so to achieve a desired performance, Column 9, Lines 29-30.
Regarding claims 2 & 11, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches a loop filter coupled to an output of the PFD-CPC and to a control input of the VCO (Figure 1: Loop Filter & Vctrl). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit as well as a loop filter (Figures 6A & 7A: 406 PFD+CP & Figure 7A: 708 loop filter).
Regarding claims 4 & 14, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches a high- frequency reference signal coupled to the PFD-CPC (Figure 1: 2Fref). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit as well as a reference signal (Figures 6A & 7A: 406 PFD+CP & Figure 7A: ref).
Regarding claims 5 & 18, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches wherein each of the plurality of identical slices of the reconfigurable CPC of the PFD-CPC is configured to independently adjust an overall charge pump current for bandwidth tuning (Figure 9: the charge pump of the proposed PLL & upper/lower 3Icp, Icp, CPset). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit as well as configured to adjust frequency (Figures 6A & 7A: 406 PFD+CP & Figure 6A: 406B).
Regarding claim 6, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches wherein each of the plurality of identical slices of the reconfigurable CPC of the PFD-CPC is configured to adjust frequency margining of an output signal to expand a range of operating frequencies (Figure 9: the charge pump of the proposed PLL & upper/lower 3Icp, Icp, CPset). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit as well as an adjustment of the charge pump (Figures 6A & 7A: 406 PFD+CP & Figure 6A: 406B).
Regarding claims 7 & 19, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches wherein the multi-phase PFD of the PFD-CPC is configured to adjust phase differences between a feedback signal and a reference signal for tracking frequency and phase of an output signal (Figure 1: DE-PFD, Div & 2Fref). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit (Figures 6A & 7A: 406 PFD+CP).
Regarding claim 8, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches wherein the PFD-CPC is configured to dynamically switch between single-phase mode and multi-phase mode based on operating conditions (Section 2, Second Paragraph: Section 2, Second Paragraph: when the phase difference is… DE-PFD is switched to the SE-PFD to reduce the noise and jitter). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit (Figures 6A & 7A: 406 PFD+CP).
Regarding claim 9, the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1. In addition, Li teaches wherein each one of the plurality of identical slices of the reconfigurable CPC is configured to be set as active or inactive (Figure 9: the charge pump of the proposed PLL & upper/lower 3Icp, Icp, CPset).
Regarding claim 10, Li also teaches wherein each one of the plurality of identical slices of the reconfigurable CPC is configured to independently adjust an overall charge pump current (Figure 9: the charge pump of the proposed PLL & upper/lower 3Icp, Icp, CPset).
Regarding claim 15, the combination of Li and Ng teaches the method of claim 13. In addition, Li teaches providing an output signal from a voltage-controlled oscillator (VCO) (Figure 1: VCO) coupled to the PFD-CPC circuit (Figure 1: DE-PFD, Charge Pump & Bandwidth Control Unit (BCU)), wherein the output signal is used as a feedback signal (Figure 1: VCO & Output) in conjunction with the high-frequency reference signal (Figure 1: 2Fref) to the PFD-CPC for adjusting the operating mode and optimizing noise suppression within the targeted frequency band (Section 2, Second Paragraph: when the phase difference is… DE-PFD is switched to the SE-PFD to reduce the noise and jitter & Third Paragraph: the locking state detection and the bandwidth control are accomplished by using the DE-PFD and the BCU to control the loop filter resistor to keep the PLL stable). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit (Figures 6A & 7A: 406 PFD+CP).
Regarding claim 16, the combination of Li and Ng teaches the method of claim 13. In addition, Li teaches adjusting a control input of the voltage-controlled oscillator (VCO) (Figure 1: Vctrl & VCO) coupled to the PFD-CPC circuit based on feedback from a divider circuit (Figure 1: ÷N) to maintain stable operation and accurate tracking of frequency and phase (Section 2, Second Paragraph: when the phase difference is… DE-PFD is switched to the SE-PFD to reduce the noise and jitter & Third Paragraph: the locking state detection and the bandwidth control are accomplished by using the DE-PFD and the BCU to control the loop filter resistor to keep the PLL stable). However, as stated in claim 1 that Li does not explicitly disclose the PFD-CPC circuit. Ng, on the other hand, discloses the PFD-CPC circuit (Figures 6A & 7A: 406 PFD+CP).
Regarding claim 17, Li also teaches adjusting frequency margining of an output signal from the voltage-controlled oscillator (VCO) to expand a range of operating frequencies within the targeted frequency band (Figure 1: VCO/Output & Figure 9: upper/lower 3Icp, Icp, CPset).
9. Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Ng and in further view of Arcudia (US 2016/026172 A1).
Regarding claim 3, although the combination of Li and Ng teaches the wide-band, multi-phase PLL circuit of claim 1, the combination does not explicitly disclose wherein the VCO is a low phase noise voltage-controlled oscillator with a split capacitor bank and varactor. In a related field of endeavor, Arcudia discloses wherein the VCO is a low phase noise voltage-controlled oscillator with a split capacitor bank and varactor (Figure 3: 340 & Paragraph 32: the VCO 340 comprises an LC tank 350 including an inductor L, varactors 352 and a capacitor bank 355). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize combination’s VCO to include a capacitor bank and varactor as in Arcudia. One of ordinary skill in the art would be motivated to do so to provide desired frequencies, Paragraph 4.
Regarding claim 12, Arcudia further discloses wherein the VCO further comprises a tank circuit (Figure 3: 340 & Paragraph 32: the VCO 340 comprises an LC tank 350 including an inductor L, varactors 352 and a capacitor bank 355).
Conclusion
10. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to SHAWKAT M. ALI whose telephone number is (571) 270-1639. The Examiner can normally be reached on Monday-Thursday 8:30AM-3:30PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO AIR at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, SAM K. AHN can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWKAT M ALI/
Primary Examiner, Art Unit 2633
Prosecution Insights