DETAILED ACTION
This action is in response to the Application filed on 12/13/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/13/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the dipole is a depletion-mode transistor” must be shown or the feature(s) canceled from the claim(s). Figures 5 – 7 shows that dipole D1, 11 and D21, respectively, are enhancement-mode transistors symbols (M21-M23 / M31 – M3n). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim(s) 1 – 3 is/are objected to because of the following informalities:
Claim 1 recites “the drain” in line 4. Said limitation lacks antecedent basis.
Claim 1 recites “the source” in line 6. Said limitation lacks antecedent basis.
Claim 1 recites “the ground” in line 7. Said limitation lacks antecedent basis.
Claim 1 recites “the drain” in line 7. Said limitation lacks antecedent basis.
Claim 1 recites “the one hand” in line 8. Said limitation lacks antecedent basis.
Claim 1 recites “the other hand” in line 8. Said limitation lacks antecedent basis.
Claim 1 recites “the gate of said bottom transistor” in line 9. Said limitation lacks antecedent basis.
Claim 1 recites “the drain” in line 15. Said limitation lacks antecedent basis.
Claim 1 recites “the source” in line 16. Said limitation lacks antecedent basis.
Claim 1 recites “the drain” in line 17. Said limitation lacks antecedent basis.
Claim 1 recites “the gate” in line 18. Said limitation lacks antecedent basis.
Claim 1 recites “the source” in line 18. Said limitation lacks antecedent basis.
Claim 1 recites “the source” in line 20. Said limitation lacks antecedent basis.
Claim 1 recites “the drain” in line 21. Said limitation lacks antecedent basis.
Claim 1 recites “the reference voltage” in line 27. Said limitation lacks antecedent basis.
Claim 2 recites “the drain” in line 3. Said limitation lacks antecedent basis.
Claim 2 recites “the one hand” in line 3. Said limitation lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Page 9 of the original specifications recites “the dipole D11 corresponds to three enhancement-mode transistor M21, M22, M23 connected in series” and “In the embodiment of figure 7, the dipole D21 corresponds to n enhancement-mode transistors M31-M3n connected in series”. However, claim 2 recites “characterised in that wherein the dipole is a depletion-mode transistor”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “to the gate of said enhancement-mode transistor”. However, claim 1 on which claim 2 depends, claims a plurality of enhancement-mode transistors. It is unclear to which of the claimed enhancement-mode transistor claim 2 is referring to.
Claim 3 recites “said enhancement-mode transistor”. However, claim 1 on which claim 3 depends, claims a plurality of enhancement-mode transistors and claim 3 also claims a plurality of enhacenment-mode transistors. It is unclear to which of the claimed enhancement-mode transistors claim 3 is referring to.
Claim 3 recites “n enhancement-mode transistors”. However, n is not defined in the claims, therefore, the limits and bounds of the claim are indefinite.
Claim 3 recites “two consecutive transistors (M31-M3n) being connected by the source of one and the drain of the other”. It is unclear to what application is referring to by using “of one” and “the other”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 4 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 4 depends on itself. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over
US Patent No. 4,654,578; (hereinafter Salerno) in view of US Pub. No. 2011/0018520; (hereinafter Imura).
Regarding claim 1, Salerno [e.g. Fig. 1] discloses a voltage reference circuit comprising: a first branch comprising: a first depletion-mode top transistor [e.g. MD1], the drain of which is connected to a voltage source [e.g. VDD], a first enhancement-mode bottom transistor [e.g. ME3], the source of which is connected to the ground, the drain of which is connected, on the one hand, to the gate of the top transistor [e.g. via ME1], and on the other hand, the gate of said bottom transistor [e.g. drain terminal of ME3 is directly connected to the gate terminal of ME3], and a dipole [e.g. ME1], a first terminal [e.g. drain (upper) terminal] of which is connected to the source of the top transistor [e.g. MD1] and the second terminal [e.g. source (lower) terminal] of which is connected to the drain of the first bottom transistor [e.g. ME3], and a second branch comprising: a second depletion-mode top transistor [e.g. MD2], the drain of which is connected to the voltage source [e.g. VDD], the source of which is connected to the drain of a third transistor [e.g. ME2], and the gate of which is connected to the source of said third transistor [e.g. via source of MD2 and gate of ME2], and a second enhancement-mode bottom transistor [e.g. ME4], the source of which is connected to the ground [e.g. directly, as shown], and the drain of which is connected to the source of the third transistor [e.g. directly as shown], the source of the first top transistor of the first branch being connected to the gate of the third transistor of the second branch [e.g. via MD2], the gates of the first bottom transistor of the first branch and of the second bottom transistor of the second branch being connected so as to form a current mirror [e.g. gates of ME3 and ME4 are directly connected], the reference voltage being provided to the source of the second top transistor of the second branch [e.g. VH].
Salerno fails to disclose wherein the third transistor is a depletion-mode transistor.
Imura teaches wherein the third transistor [e.g. 3] is a depletion-mode transistor [e.g. paragraph 023 recites “an N-channel depletion type MOS transistor 3”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Salermo by wherein the third transistor is a depletion-mode transistor as taught by Imura in order of being able to provide lower power consumption, paragraph 03.
Regarding claim 2, Salerno [e.g. Fig. 1] discloses characterised in that wherein the dipole is a depletion-mode transistor [e.g. ME1], the drain of which is connected, on the one hand, to the gate of said enhancement-mode transistor [e.g. the drain and gate terminals of ME1 are directly connected], and on the other hand, to the first terminal of the dipole [e.g. having IR1], and the source of which is connected to the second terminal of the dipole [e.g. terminal between ME1 and ME3].
Claim(s) 3 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Salerno in view of Imura and further in view of US Patent No. 9,647,476; (hereinafter Kinzer).
Regarding claim 3, Salerno [e.g. Fig. 1] fails to disclose characterised in that wherein the dipole comprises n enhancement-mode transistors (M31,M3n), each of said enhancement-mode transistors (M31-M3n) having its gate connected to its drain, said enhancement-mode transistors (M31-M3n) being connected in series, two consecutive transistors (M31-M3n) being connected by the source of one and the drain of the other and, the drain of the first transistor forming the first terminal of the dipole and the source of the last transistor forming the second terminal of the second dipole.
Kinzer [e.g. Fig. 20] teaches characterised in that wherein the dipole comprises n enhancement-mode transistors [e.g. 2020], each of said enhancement-mode transistors having its gate connected to its drain [e.g. as shown], said enhancement-mode transistors being connected in series [e.g. as shown], two consecutive transistors being connected by the source of one and the drain of the other [e.g. as shown] and, the drain of the first transistor forming the first terminal of the dipole [e.g. 2011] and the source of the last transistor forming the second terminal of the second dipole [e.g. 2012; col. 23, lines 57 – 58 recite “series of identical diode connected enhancement-mode low-voltage transistors 2020”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Salermo by characterised in that wherein the dipole comprises n enhancement-mode transistors (M31,M3n), each of said enhancement-mode transistors (M31-M3n) having its gate connected to its drain, said enhancement-mode transistors (M31-M3n) being connected in series, two consecutive transistors (M31-M3n) being connected by the source of one and the drain of the other and, the drain of the first transistor forming the first terminal of the dipole and the source of the last transistor forming the second terminal of the second dipole as taught by Kinzer in order of being able to provide a regulated Vref that does not fluctuate over high dV/dT.
Regarding claim 4, Salerno fails to disclose characterised in that the dipole comprises three enhancement-mode transistors.
Kinzer [e.g. Fig. 20] teaches characterised in that the dipole comprises three enhancement-mode transistors [e.g. upper three transistors in 2020].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Salermo by characterised in that the dipole comprises three enhancement-mode transistors as taught by Kinzer in order of being able to provide a regulated Vref that does not fluctuate over high dV/dT.
Claim(s) 3 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Salerno in view of Imura and further in view of US Pub. No. 2024/0329674; (hereinafter Bimbi).
Regarding claim 5, Salerno fails to disclose characterised in that the transistors are GaN transistors.
Bimbi teaches characterised in that the transistors are GaN transistors [e.g. paragraph 0115 recites “The depletion n-type MOSFET transistors and enhancement n-type MOSFET transistor are obtained by Gallium Nitride technology, in particular are GaN High Electron Mobility Transistor”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Salermo by characterised in that the transistors are GaN transistors as taught by Bimbi in order of being able to provide higher efficiency, switching speeds, reduced size and improved thermal management, as it is well known in the art.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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