DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2013/0214703 (“Bouchard”) in view of U.S. Patent Pub. 2015/0114086 (“Lin”).
Claim 1
Bouchard discloses a temperature sensor, comprising: a first thermistor (thermistor 106), a second thermistor (thermistor 108) connected in parallel to the first thermistor (Fig. 3, paragraphs [0018-0019]), a first diode connected in series to the first thermistor (diode 318), and a second diode connected in series to the second thermistor (diode 320), and the first diode and the second diode are two adjacent diodes with a same type, but opposite polarities (paragraphs [0018-0019], positive and negative).
Bouchard does not appear to explicitly disclose wherein the first thermistor and the second thermistor are two adjacent thermistors with a same material and process, but different geometric dimensions.
Lin discloses calibrating thermistor heating elements of the same material including different geometries providing different temperature/resistance correlation (paragraph [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the first thermistor and the second thermistor are two adjacent thermistors with a same material and process, but different geometric dimensions, as disclosed by Lin, into the device of Bouchard, for the purpose of calibrating a temperature of the thermistor (Lin, paragraph [0042]).
Claim 2
Bouchard in view of Lin discloses the temperature sensor according to claim 1, wherein in a case where a detection position is on a metal interconnect layer on a silicon wafer chip, the first thermistor and the second thermistor are formed by metal interconnects of the metal interconnect layer (Lin, paragraphs [0025-0026]).
Claim 3
Bouchard in view of Lin discloses the temperature sensor according to claim 1, wherein the first thermistor and the second thermistor are polysilicon resistors (Lin, paragraphs [0025-0026]).
Claim 4
Bouchard in view of Lin discloses the temperature sensor according to claim 1, wherein the first diode and the second diode are discrete devices or integrated devices (Bouchard, Fig. 3, integrated diodes).
Claim 5
Bouchard in view of Lin discloses the temperature sensor according to claim 1, wherein spacing between the first thermistor and the second thermistor and spacing between the first diode and the second diode are determined by a manufacturing process employed (Lin, paragraph [0042], manufacturing procedures).
Claim 15
Bouchard in view of Lin discloses the temperature sensor according to claim 5, wherein the spacing between the first thermistor and the second thermistor and the spacing between the first diode and the second diode are a minimum spacing allowed by rules of the manufacturing process employed (Lin, paragraphs [0025-0026]).
Claim 6 -10 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2013/0214703 (“Bouchard”) in view of U.S. Patent Pub. 2015/0114086 (“Lin”), further in view of U.S. Patent Pub. 2013/0168815 (“Leneel”).
Claim 6
Bouchard in view of Lin discloses a temperature sensor according to claim 1.
Bouchard in view of Lin does not appear to explicitly disclose temperature sensor packaging method applied to the temperature sensor the temperature sensor packaging method comprising: forming the first thermistor, the second thermistor, the first diode and the second diode on a silicon wafer chip by a diffusion process, and interconnecting the first thermistor, the second thermistor, the first diode and the second diode by metal on the silicon wafer chip to form the temperature sensor on the silicon wafer chip.
Leneel discloses a method of semiconductor fabrication for a thermistor including diffusion (paragraph [0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated temperature sensor packaging method applied to the temperature sensor the temperature sensor packaging method comprising: forming the first thermistor, the second thermistor, the first diode and the second diode on a silicon wafer chip by a diffusion process, and interconnecting the first thermistor, the second thermistor, the first diode and the second diode by metal on the silicon wafer chip to form the temperature sensor on the silicon wafer chip, as disclosed by Leneel, into the device of Bouchard in view of Lin, for the purpose of manufacturing a multilayer structure without breaking vacuum and minimizing defects (Leneel, paragraph [0079]).
Claim 7
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 6, further comprising,in a case where the first thermistor and the second thermistor are polysilicon resistors, leading out the temperature sensor from the silicon wafer chip through vias and a metal interconnect layer on the silicon wafer chip (Leneel, paragraph [0079-0080]).
Claim 8
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 7, further comprising: plating the first thermistor and the second thermistor onto the silicon wafer chip (Leneel, paragraph [0079-0080]).
Claim 9
Bouchard in view of Lin discloses the temperature sensor according to claim 1.
Bouchard in view of Lin does not appear to explicitly disclose a temperature sensor packaging method applied to the temperature sensor, the temperature sensor packaging method comprising: burying the first thermistor, the second thermistor, the first diode, and the second diode into a buried layer of a substrate by embedding, or arranging the first thermistor, the second thermistor, the first diode, and the second diode on the substrate by surface mounting, wherein the first thermistor, the second thermistor, the first diode, and the second diode are discrete components.
Leneel discloses a method of semiconductor fabrication for a thermistor including embedding and surface deposition (paragraph [0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated a temperature sensor packaging method applied to the temperature sensor, the temperature sensor packaging method comprising: burying the first thermistor, the second thermistor, the first diode, and the second diode into a buried layer of a substrate by embedding, or arranging the first thermistor, the second thermistor, the first diode, and the second diode on the substrate by surface mounting, wherein the first thermistor, the second thermistor, the first diode, and the second diode are discrete components, as disclosed by Leneel, into the device of Bouchard in view of Lin, for the purpose of manufacturing a multilayer structure without breaking vacuum and minimizing defects (Leneel, paragraph [0079]).
Claim 10
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 9, wherein the first thermistor and the second thermistor are formed by metal interconnects of a detection layer of the substrate (Lin, paragraphs [0025-0026]).
Claim 16
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 6, wherein in a case where a detection position is on a metal interconnect layer on a silicon wafer chip, the first thermistor and the second thermistor are formed by metal interconnects of the metal interconnect layer (Lin, paragraphs [0025-0026]).
Claim 17
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 6, wherein spacing between the first thermistor and the second thermistor and spacing between the first diode and the second diode are determined by a manufacturing process employed (Lin, paragraphs [0025-0026]).
Claim 18
Bouchard in view of Lin, further in view of Leneel discloses the temperature sensor packaging method according to claim 9, wherein spacing between the first thermistor and the second thermistor and spacing between the first diode and the second diode are determined by a manufacturing process employed (Lin, paragraphs [0025-0026]).
Allowable Subject Matter
Claims 11-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the present application relates in general to temperature sensor packaging and method including a first and second thermistor; a first and second diode. The cited art, U.S. Patent Pub. 2013/0214703 (“Bouchard”) in view of U.S. Patent Pub. 2015/0114086 (“Lin”), further in view of U.S. Patent Pub. 2013/0168815 (“Leneel”), discloses a similar temperature sensor packaging and method also including a first and second thermistor; a first and second diode. However, the cited art does not appear to explicitly disclose or suggest the temperature sensor packaging method comprising: respectively arranging a plurality of temperature sensors in different system layers of a stacked packaging structure, wherein the temperature sensors are at a wafer level or a substrate level; and uniformly leading ports of the temperature sensors out to a highest-layer packaging port through internal interconnection, so as to perform a parallel test among multiple layers; changing a polarity of a voltage between two ports of the temperature sensor, and measuring a resistance of the temperature sensor before the change of the polarity of the voltage and a resistance of the temperature sensor after the change of the polarity of the voltage; and obtaining a difference ΔR between the first thermistor and the second thermistor in the temperature sensor according to the resistance of the temperature sensor before the change of the polarity of the voltage and the resistance of the temperature sensor after the change of the polarity of the voltage, and obtaining a temperature T detected by the temperature sensor based on the specific resistance formula. Thus, the specific structure including temperature measurement and calculation as required by the claimed invention is not provided by the cited art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERICA S Y LIN whose telephone number is (571)270-7911. The examiner can normally be reached M-F 8-4, TW M,W.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERICA S LIN/Primary Examiner, Art Unit 2853
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