DETAILED ACTION
This Office action is in response to the application filed on 17 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 7 and 11 are objected to because of the following informalities:
In claim 7 at line 2, “the sensing current” lacks antecedent basis.
In claim 11 at line 2, “the set signal” lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the AC component reflector” at line 1. There is no antecedent basis for this element in the claims, but rather claim 1 recites, “a SAW signal modulator to generate a second SAW signal by reflecting an [AC] component”. It is thus not clear if the AC component reflector in claim 3 is meant to refer to the SAW signal modulator, or if it is instead introducing a new element that is a sub-component of the SAW signal modulator.
For purposes of examination, “the AC component reflector” is being interpreted as the SAW signal modulator.
Claim 6 depends from claim 4 and recites “the integrating capacitor” at line 1. There is no antecedent basis in claim 6 or its parent claims for this element. However, claim 5 properly introduces the integrating capacitor, making it unclear if claim 6 was intended to depend from claim 5 instead of claim 4.
For purposes of examination, claim 6 is being interpreted as depending from claim 5.
Claim 7 recites that the first SAW signal is generated “by synthesizing the sensing current of the power conversion device with the ramp signal”. This appears to contradict the recitation in the parent claim 4 specifying that the ramp signal is generated “as the first SAW signal”. That is, claim 4 appears to require that the ramp signal is itself the first SAW signal, where claim 7 appears to instead require that the first SAW signal is synthesized from the combination of the ramp signal and the current sensing signal.
For purposes of examination, claim 7 is being interpreted by assuming that the first SAW signal is the ramp signal, and is further generated based on a current sensing signal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 11-15, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fang et al. (US 2015/0340957; hereinafter “Fang”).
In re claim 1, Fang discloses a power controller (Fig. 6(b)) comprising:
an error signal generator (716) configured to generate an error signal (COMP at 574) according to the difference between a sensing voltage (720) and a reference voltage (722) of a power conversion device (see Fig. 6(a)) including a power semiconductor (528);
a SAW signal generator (702) configured to generate a first SAW signal (see Figs. 6(b) and 8(c), showing detail of circuits within Fig. 6(b): components of signal Ramp at 728/1798 aside from the component generated from Icomp 738/1734);
a SAW signal modulator (742 in Fig. 6(b), 1734 in Fig. 8(c)) configured to generate a second SAW signal (signal Ramp at 728/1798 including all of its components; i.e., the final signal Ramp applied to comparator 706 in Fig. 6(b)) by reflecting an alternating current (AC) component of the error signal to the first SAW signal ([0093]: 742 converts error signal COMP (including its AC component) to current Icomp and supplies it to Ramp generator); and
a Power Width Modulation (PWM) signal generator (706, 708) configured to generate a PWM signal (730) to control the power semiconductor by comparing the second SAW signal and the error signal (Fig. 6(b): comparator 706 compares second SAW signal ramp/728 with error signal COMP).
In re claim 2, Fang discloses a gate controller (710) configured to generate a gate signal (756) according to the PWM signal (730) and supply the gate signal to the power semiconductor (see GATE output of controller in Fig. 6(a)).
In re claim 3, Fang discloses wherein the AC component reflector includes a Direct Current (DC) blocking capacitor (Fig. 8(c): capacitor C/1718; it is noted that all capacitors inherently block DC and are thus considered DC blocking capacitors), and is configured to reflect the AC component to the first SAW signal through the DC blocking capacitor (Fig. 8(c): Icomp 1734 is provided through C/1718 to SAW signal ramp at 1798).
In re claim 4, Fang discloses wherein the SAW signal generator includes a ramp signal generator that periodically generates a ramp signal as the first SAW signal (Fig. 8(c): ramp signal generator including components within circuit 1700), and wherein the SAW signal modulator is configured to generate the second SAW signal using the ramp signal (Fig. 8(c): Icomp 1734 is provided through C/1718 to SAW signal ramp at 1798 to produce second SAW signal).
In re claim 5, Fang discloses wherein the ramp signal generator includes a current source and an integrating capacitor (Fig. 8(c): current source formed by current mirror 1712/1714, integrating capacitor 1718), and wherein the current source is connected to one side of the integrating capacitor (through 1716), and the other side of the integrating capacitor is connected to a line to which the error signal is supplied (Fig. 8(c): error signal supplied as Icomp 1734 to other side of capacitor 1718).
In re claim 6 Fang discloses wherein the integrating capacitor is periodically reset to a constant voltage (Fig. 8(c) and [0118]: switch 1720 resets voltage Ramp on capacitor 1718 to constant voltage Vref; see also Ramp waveform 2912 in Fig. 10(b)).
In re claim 7, Fang discloses wherein the SAW signal generator is configured to generate the first SAW signal by synthesizing the sensing current of the power conversion device with the ramp signal ([0090] and Fig. 6(b): SAW generator 702 produces ramp 728 based on current sensing signal I0/794).
In re claim 11, Fang discloses wherein the gate controller is configured to form a rising edge of the gate signal according to the set signal and form a falling edge of the gate signal according to the rising edge of the PWM signal (see waveforms of Fig. 10(b): Gate signal 2904 rises with set signal Trigger 2908 and falls with PWM signal Modulation 2902).
In re claim 12, Fang discloses wherein the power conversion device is a buck converter or a boost converter (Fig. 6(a): the flyback topology is understood to be capable of both bucking and boosting operations) including two power semiconductors (transistor 528 and diode 518).
In re claim 13, Fang discloses a power conversion device (Fig. 6(a)) comprising:
a power semiconductor (528); and
a power controller (502/Fig. 6(b)) configured to supply a gate signal (GATE 542) to a gate of the power semiconductor (528) to regulate the output of the power conversion device (Abstract), and including a capacitor (Fig. 8(c): C/1718), wherein the capacitor is arranged between a line of an error signal (Figs. 6(b) and 8(c): C/1718 connected to Icomp current source 174 which is produced from error signal COMP as shown in Fig. 6(b)) generated according to a difference between a sensing voltage (Fig. 6(b): 720) and a reference voltage (Vref_ea 722) of the power conversion device and a line of a SAW signal (Fig. 8(c): SAW signal Ramp at 1798).
In re claim 14, Fang discloses wherein the power controller is configured to generate a first SAW signal (see Figs. 6(b) and 8(c), showing detail of circuits within Fig. 6(b): components of signal Ramp at 728/1798 aside from the component generated from Icomp 738/1734) using a current source (Fig. 8(c): current source formed by current mirror 1712/1714, integrating capacitor 1718) and the capacitor (C 1718), and wherein one side of the capacitor is connected to the current source (through 1716), and the other side of the capacitor is connected to the line of the error signal (Fig. 8(c): error signal supplied as Icomp 1734 to other side of capacitor 1718).
In re claim 15, Fang discloses wherein the power controller is configured to generate the first SAW signal by synthesizing a voltage on one side of the capacitor and a sensing current of the power conversion device ([0090] and Fig. 6(b): SAW generator 702 produces ramp 728 based on current sensing signal I0/794).
In re claim 18, Fang discloses wherein a control loop compensation circuit is connected to the line of the error signal (Fig. 6(b): error amp 716 forms compensation circuit; see [0090]).
In re claim 20, Fang discloses wherein the capacitor includes a DC blocking capacitor that blocks a DC component and transmits an AC component (Fig. 8(c): capacitor C/1718; it is noted that all capacitors inherently block DC and are thus considered DC blocking capacitors).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Darmawaskita et al. (US 2014/0132236; hereinafter “Darmawaskita”).
In re claims 8 and 16, Fang discloses wherein the error signal generator includes an error amplifier configured to amplify and output the difference between the sensing voltage and the reference voltage (Fig. 6(b): error amp 716 amplifies difference between sensing voltage 720 and reference voltage Vref_ea 722).
Fang does not disclose a buffer configured to buffer the output of the error amplifier, and wherein the output of the buffer is generated as the error signal. Whereas Darmawaskita discloses a power controller (Fig. 1) in which a buffer (114) is connected and configured to buffer the output of an error amplifier (116) to produce the error signal (output of 114) in order to ensure the error generation circuitry has enough drive capability to drive the subsequent stages ([0038]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller of Fang by including a buffer configured to buffer the output of the error amplifier, and wherein the output of the buffer is generated as the error signal in order to ensure the error generation circuitry has enough drive capability to drive the subsequent stages as taught by Darmawaskita.
In re claims 9 and 17, Fang as modified discloses wherein the SAW signal modulator/capacitor (742 in Fig. 6(b), 1734 in Fig. 8(c)) is arranged between an output side of the buffer and the SAW signal generator (i.e., once modified as proposed above, the buffer would be connected between the error amplifier and SAW modulator, resulting in the claimed relationship between SAW modulator and SAW signal generator).
In re claim 10, Fang as modified discloses wherein the error signal generator further includes a control loop compensation circuit connected to an input side of the buffer (Fang, Fig. 6(b): error amp 716 forms part of compensation circuit; Darmawaskita, Fig. 1: compensation network 120 is further connected to error amplifier 116).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang.
In re claim 19, Fang discloses the invention according to claim 13 as explained above, but does not disclose the output of the power conversion device is supplied to a display driving device that drives pixels at a constant frame rate. However, the limitation represents a mere intended use of the power conversion device, whereas Fang discloses a general purpose power conversion device that would be understood to a person of ordinary skill in the art to be capable of supplying power to a wide variety of load devices that require a suitable DC voltage.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the power conversion device of Fang to supply power to a display driving device that drives pixels at a constant frame rate, for the purpose of providing a suitable DC voltage to power the particular load.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2009/0295445, US 2013/0038301, US 2013/0038302, US 2013/0127557, US 2015/0263614, US 2016/0062375, US 2016/0181942 and US 2024/0413749 are all cited as relevant for showing power controllers in which an error signal is added to or otherwise combined with a ramp or SAW signal and provided to a PWM generator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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