DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "to generate the fourth current pulse" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 10 depends on claim 6, however, there is no mention of the fourth current pulse in claim 6 or claim 1, the fourth current pulse is introduced in claim 9, claim 10 should depend on claim 9. For the purpose of examination, claim 10 is interpreted to depend on claim 9 instead of claim 6. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Seong (KR 102148473) in the view of Kawase (US 7227519).
Regarding claim 1: Seong teaches display pixel for a display screen comprising a light-emitting circuit comprising at least a first electroluminescent source (Fig. 4 and paragraph [0014, 0031-0034] teach a display comprising a light emitting circuit 30 comprising at least a first LED), a controllable current source for driving the light-emitting circuit with current pulses and a driver circuit for controlling the current source (Figs. 4-5 and paragraph [0031-0036] teach a drive circuit 200 comprising a controllable current source for driving the light emitting circuit 30 with current pulses as shown in Fig. 5), the driver circuit being configured to receive a digital signal comprising bits (Fig. 11 and paragraph [0071, 0077] teach the host system 14 generates digital data "The timing controller 11 receives digital video data (RGB) of an input image from the host system 14 ", the driver circuit therefore receives digital data and therefore implicitly a plurality of bits, first and second as brightness control information "The LED driver 200 generates the final modulated PWM signal of the present invention that changes at a constant period based on the brightness control information (GD, LD, CV, Vsync) supplied from the host system 14), and to control the current source for supplying the current pulses modulated by pulse-width modulation and modulated by pulse-amplitude modulation based on the bits of the digital signal (Figs. 4-5 and paragraph [0031-0036] teach the light source driving device 20 includes a driving voltage generating unit 100 and an LED driving unit 200" it is to be noted that the driving device 20 includes the driving voltage generator 100, and generating the current pulses modulated by pulse-width modulation and modulated by pulse-amplitude modulation), wherein the driver circuit is configured to command the current source to provide a current that is the sum of successive first current pulses having a constant intensity and first durations that depend on the first bits of the digital signal (Figs. 6-8 and paragraph [0037-0052] teach two PWMs, PWMa and PWMb are added either according to model of figure 6 or model of figure 7, see figures 8b or 8c) and a second current pulse commanded by the second bit of the digital signal and having a constant second duration, the sum of the first durations being inferior or equal to the second duration (Figs. 6-8 and paragraph [0037-0052] teach two PWMs, PWMa and PWMb are added either according to model of figure 6 or model of figure 7, see figures 8b or 8c. See figure 8b either B is equal A -see figure CH1 or CH2 of figure 8b- or inferior to A -see figure CH3 of figure 8b).
Seong does not explicitly teach the digital signal comprising first bits and one second bit, the second bit being different from the first bits.
However, Kawase teach the digital signal comprising first bits and one second bit, the second bit being different from the first bits (Figs. 6-8 and column 12 lines 16-66 teach "A specific method of distribution will now be described. The distribution of voltage value and pulse width can be freely set, but as an example, consider distribution in equal divisions. Input data is divided into n high-order bits and m low-order bits to realize gray scale. For example, consider the case of realizing 6 bit gray scale (64 gray scale levels), the bits being distributed such that 2 bits are allotted to voltage value (4 gray scale levels) and 4 bits to pulse width (16 gray scale levels). The decode algorithm is as follows. First, 2 high-order bits and 4 low-order bits of input data are latched as voltage value division data [A] and pulse width division data [B], respectively. Next, a voltage value for the numerical value of the data [A] is outputted over a period of 16 intervals. At the same time, output is such that for only the number of intervals corresponding to the numerical value of data [B], 1 is added to the voltage value output"). Therefore, it would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Seong’s invention by including above teachings of Kawase, because utilizing different bits for LED driving to achieve optimal grayscale levels is very well-known and widely used in the art, as shown by Kawase. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 2: Combination of Seong and Kawase teach wherein the current source is configured to generate the successive first current pulses while the second current pulse is generated (Seong in Figs. 7-8 and paragraph [0037-0053] teach two the successive current pulses PWMs, PWMa and PWMb are added according to model of figure 7, see figure 8b. Also, taught by Kawase in Figs. 7-8). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claim 3: Combination of Seong and Kawase teach wherein the bits of the digital signal are ranked from the most significant bit to the least significant bit and wherein the intensity of the second current pulse depends on the rank of the second bit of the digital signal (Kawase in Figs. 6-8 and column 12 lines 16-66). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claim 4: Combination of Seong and Kawase teach wherein the second bit comprises the most significant bit of the digital signal (Kawase in Figs. 6-8 and column 12 lines 16-66). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claim 5: Combination of Seong and Kawase teach wherein the digital signal comprises a third bit different from the first bits and the second bit, and wherein the driver circuit is configured to command the controllable current source to provide the current that is the sum of the successive first current pulses, the second current pulse, and a third current pulse commanded by the third bit of the digital signal and having the second duration (Kawase in Figs. 6-8 and column 12 lines 16-66 teach input data is divided into n high-order bits and m low-order bits to realize gray scale. For example, consider the case of realizing 6 bit gray scale (64 gray scale levels), the bits being distributed such that 2 bits are allotted to voltage value (4 gray scale levels) and 4 bits to pulse width (16 gray scale levels). The decode algorithm is as follows. First, 2 high-order bits and 4 low-order bits of input data are latched as voltage value division data [A] and pulse width division data [B], respectively. Next, a voltage value for the numerical value of the data [A] is outputted over a period of 16 intervals. At the same time, output is such that for only the number of intervals corresponding to the numerical value of data [B], 1 is added to the voltage value output.", wherein two bits are dedicated to the amplitudes, therefore the MSB bit and the next MSB-1 bit lower as the MSB one are used, the next MSB-1 being identified as the third bit). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claims 6-8: Combination of Seong and Kawase teach wherein the current source is configured to generate the third current pulse simultaneously with the second current pulse; wherein the intensity of the third current pulse depends on the rank of the third bit of the digital signal and is different from the intensity of the second current pulse; and wherein the third bit is the second most significant bit of the digital signal (Kawase in Figs. 6-8 and column 12 lines 16-66 teach input data is divided into n high-order bits and m low-order bits to realize gray scale. For example, consider the case of realizing 6 bit gray scale (64 gray scale levels), the bits being distributed such that 2 bits are allotted to voltage value (4 gray scale levels) and 4 bits to pulse width (16 gray scale levels). The decode algorithm is as follows. First, 2 high-order bits and 4 low-order bits of input data are latched as voltage value division data [A] and pulse width division data [B], respectively. Next, a voltage value for the numerical value of the data [A] is outputted over a period of 16 intervals. At the same time, output is such that for only the number of intervals corresponding to the numerical value of data [B], 1 is added to the voltage value output.", wherein two bits are dedicated to the amplitudes, therefore the MSB bit and the next MSB-1 bit lower as the MSB one are used, the next MSB-1 being identified as the third bit). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claims 9 and 10: Combination of Seong and Kawase teach wherein the digital signal comprises a fourth bit different from the first bits, the second bit, and the third bit, and wherein the driver circuit is configured to command the controllable current source to provide the current that is the sum of the successive first current pulses, the second current pulse, the third current pulse, and a current fourth pulse commanded by the fourth bit of the digital signal and having the second duration; and wherein the current source is configured to generate the fourth current pulse simultaneously with the second current pulse; and wherein the current source[[ (82)]] is configured to generate the fourth current pulse simultaneously with the second current pulse (Kawase in Figs. 6 and column 12 lines 16-66 teach input data is divided into n high-order bits and m low-order bits to realize gray scale. For example, consider the case of realizing 6 bit gray scale (64 gray scale levels), the bits being distributed such that 2 bits are allotted to voltage value (4 gray scale levels) and 4 bits to pulse width (16 gray scale levels). The decode algorithm is as follows. First, 2 high-order bits and 4 low-order bits of input data are latched as voltage value division data [A] and pulse width division data [B], respectively. Next, a voltage value for the numerical value of the data [A] is outputted over a period of 16 intervals. At the same time, output is such that for only the number of intervals corresponding to the numerical value of data [B], 1 is added to the voltage value output.", wherein two bits are dedicated to the amplitudes, therefore the MSB bit and the next MSB-1 bit lower as the MSB one are used, the next MSB-1 being identified as the third bit, and the next bit being identified as the fourth bit). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claims 11-12: Combination of Seong and Kawase teach wherein the intensity of the fourth current pulse depends on the rank of the fourth bit of the digital signal and is different from the intensity of the second current pulse and the intensity of the third current pulse; and wherein the fourth bit is the third most significant bit of the digital signal (Kawase in Figs. 6 and column 12 lines 16-66, see claim 9 rejection). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claims 13-14: Combination of Seong and Kawase teach wherein the driver circuit comprises a first storage circuit for storing said first bits of the digital signal and wherein the first storage circuit comprises a shift register clocked by a pulse-width modulation clock signal (PWM); and wherein the driver circuit comprises a second storage circuit for storing said second bit of the digital signal, and a logic circuit controlled by a control signal (Ctrl) and configured to receive successively the first bits from the shift register clocked by the pulse-width modulation clock signal (PWM) and to receive said second bit from the second storage circuit and to control the controllable current source from the successively received first bits and the second bit when the control signal is in a given state (Kawase in Fig. 9 and column 13 line 30 to column 14 line 20 teach reference numeral 40 denotes a shift register for determining the timing of the sampling of data signals according to clock and start signals from the controller.". The applicant is invited to clarify the intended technical effect of dividing a single storage register by two storage registers, as the person skilled in the art can effectively use a plurality of storage registers without involving any inventive activity, as illustrated in figure 9 In the case of a system of gray scale where amplitude control and pulse width control are combined to carry out output, the decoder 42 decodes the data into two types of data, that in the time direction and that in the voltage output direction." In addition, because it is possible to program the decoder according to the characteristics of the connected panel, the distribution of and the number of divisions of amplitude (voltage, current) and pulse width can be arbitrarily changed, making accurate output of gray scale possible). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claim 15: Combination of Seong and Kawase teach wherein the light-emitting circuit comprises a first group of electroluminescent sources having a first number of electroluminescent sources and a second group of electroluminescent sources having a second number of electroluminescent sources, wherein the controllable current source comprises a first controllable current source commanded by the first bits and connected to the electroluminescent sources of the first group and a second controllable current source commanded by the second bit and connected to the electroluminescent sources of second group (Seong in Fig. 4 and paragraph [0014, 0031-0034] teach the light emitting circuit 30 comprises a plurality of group of LEDs as shown by channels, and each channel is controlled by its individual current line providing the driving current. Further, Kawase in Figs. 6-8 and column 12 lines 16-66 teach driving the LEDs via different bits, as explained in claim 1 rejection). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Regarding claim 21: Seong teaches display screen comprising an array of display pixels according to claim 1 (Fig. 11 and paragraph [0069])].
Regarding claim 22: Combination of Seong and Kawase teach comprising a circuit configured to modify a supply voltage of the display pixels according to the second bit (Seong in Figs. 9-11 and paragraph [0054-0060] teach a circuit 200 configured to modify a supply voltage of the display pixels. Further, Kawase in Figs. 6-8 and column 12 lines 16-66 teach driving the LEDs via different bits, as explained in claim 1 rejection). See claim 1 rejection for combination reasoning of Seong and Kawase, same rationale applies here.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Seong (KR 102148473), in the view of Kawase (US 7227519), and further in the view of Gu (US 20220044643).
Regarding claim 16: Combination of Seong and Kawase do not explicitly disclose wherein the controllable current source comprises: a first MOS transistor connected to the light-emitting circuit and a first switch connected to the first MOS transistor; and a second MOS transistor connected to the light-emitting circuit and a second switch connected to second MOS transistor.
However, Gu teaches wherein the controllable current source comprises: a first MOS transistor connected to the light-emitting circuit and a first switch connected to the first MOS transistor; and a second MOS transistor connected to the light-emitting circuit and a second switch connected to second MOS transistor (Fig. 6 and paragraph [0072] teach a first MOS transistor 644 connected to the light emitting circuit LED and a first switch 645 connected to the first MOS transistor 644; and a second MOS transistor 654 connected to the light-emitting circuit LED and a second switch 655 connected to the second MOS transistor 654). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Seong and Kawase, by including above features of Gu, because utilizing such driving structure of LEDs allows the display to optimally supply the current to the LEDs and control the brightness, as described by Gu. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claims 17-18: Combination of Seong, Kawase, and Gu teach wherein the logic circuit is configured to control the first switch successively from each first bit, and to control the second switch based on said second bit; and wherein the driver circuit is configured to control only the first switch based on some the first bits and to control both the first switch and the second switch based on the other of the first bits (Gu in Fig. 6 and paragraph [0072] teach the logic circuit 641&642 controlling the first and second switches as claimed). See claim 16 rejection for combination reasoning of Seong, Kawase, and Gu, same rationale applies here.
Regarding claim 19: Combination of Seong, Kawase, and Gu teach wherein the electroluminescent sources of the first group of electroluminescent sources are connected to the first MOS transistor and wherein the electroluminescent sources of the second group are connected to the second MOS transistor (Seong in Fig. 4 and paragraph [0014, 0031-0034] teach a plurality of different LED channels or groups and each group connected to individual driving line. Further, Gu in Fig. 6 and paragraph [0072] teach LED groups individually connected to MOS transistor, and similarly the different groups as disclosed by Seong can be connected to different MOS transistor). See claim 16 rejection for combination reasoning of Seong, Kawase, and Gu, same rationale applies here.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Seong (KR 102148473), in the view of Kawase (US 7227519), in the view of Gu (US 20220044643), and further in the view of Kwak (US 20230154391)
Regarding claim 20: Combination of Seong, Kawase, and Gu teach wherein the light-emitting circuit comprises a third group of electroluminescent sources having a third number of electroluminescent sources and wherein the control source comprises a third MOS transistor connected to the electroluminescent sources of the third group and a third connected to the third MOS transistor wherein the first number is equal to the second number (Seong in Fig. 4 and paragraph [0014, 0031-0034] teach a plurality of different LED channels or groups comprising same number of LEDs and each group connected to individual driving line. Further, Gu in Fig. 6 and paragraph [0072] teach LED groups individually connected to MOS transistor, and similarly the different groups as disclosed by Seong can be connected to different MOS transistor). See claim 16 rejection for combination reasoning of Seong, Kawase, and Gu, same rationale applies here.
Combination of Seong, Kawase, and Gu do not explicitly disclose wherein the third number is greater than the second number.
However, Kwak teaches wherein the third number is greater than the second number (Figs. 8 & 11 and paragraph [0036, 0092, 0100] disclose each group of LED can comprises a different number of LEDs, wherein the one group can have more LEDs than other group). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Seong, Kawase, and Gu, by including above teachings of Kwak, because utilizing a different number of LEDs in each group is quite common and widely used in the art, in order to achieve desired brightness needs for different area of the display panel, as taught by Kwak. The rationale would have been to use a known method or technique to achieve predictable results.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 20210049957) in Figs. 3-6 and related discloser teach a luminous element and a pixel circuit connected to the luminous element, wherein the pixel circuit includes a first pixel circuit including a memory storing bit values of multi-bit data corresponding to image data of a single frame and a pulse width modulation (PWM) controller configured to generate a PWM signal based on the bit values and a clock signal that is output in accordance with each bit of the multi-bit data and a second pixel circuit configured to adjust a light-emission time and a non-light-emission time of the luminous element during a single frame in response to the PWM signal.
Conclusion
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/AMIT CHATLY/Primary Examiner, Art Unit 2624