DETAILED ACTION
This Office action is in response to the application filed on 18 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanazawa et al. (US Patent 6,552,912; hereinafter “Kanazawa”).
In re claim 1, Kanazawa discloses a power conversion device (Figs. 1-2) comprising:
a first capacitor (4) that outputs a high-side potential of a DC voltage (DC potential at top terminal of 4 in Fig. 1);
a second capacitor (5) that is connected in series with the first capacitor (4) and outputs a low-side potential of the DC voltage (DC potential at bottom terminal of 5 in Fig. 1);
an inverter circuit (6) that converts the DC voltage output from the first capacitor and the second capacitor into an AC voltage (AC outputs from 6 to load CM);
a control circuit (8) that controls the inverter circuit (col. 3:3-8); and
a first substrate (30 in Fig. 2) on which the inverter circuit is mounted (see Fig. 2), wherein each of the first capacitor and the second capacitor is arranged such that an axial direction, which defines its longest size, is substantially parallel to a plane direction of the first substrate (See Fig. 2: axial/longest direction of caps 4 and 5 is parallel to substrate 30).
Kanazawa discloses the claimed invention as explained above, except that Kanazawa teaches that the second capacitor is arranged at a position farther away from the control circuit than the first capacitor, whereas claim 1 recites the opposite: the first capacitor is arranged at a position farther away from the control circuit than the second capacitor.
However, the following facts are notable: First, Kanazawa does not teach any particular reasoning or desirability for having the capacitors in the particular arrangement in which the second capacitor is farther (first capacitor is closer) to the control circuit; Second, regardless of how and where the two capacitors are to be placed inside the housing of Kanazawa’s apparatus, only three possibilities exist with respect to the relative distances of the two capacitors and the control circuit: (1) the second capacitor is farther than the first capacitor (Kanazawa’s arrangement); (2) the first capacitor is farther than the second capacitor (claimed arrangement); and (3) both capacitors are equidistant from the control circuit.
Of the three possibilities presented above, option (3) would apparently require a major reconstruction of the housing, because the entire premise of Kanazawa’s disclosure is to keep the capacitors together in a separated portion of the housing in order to ensure that there is space for a gas-discharge from the electrolytic capacitors’ bodies to occur in the event of increased ambient temperature or the like (Kanazawa at col. 3: 26-36 and col. 4: 3-10). Thus, to have the two capacitors be placed equidistant from the control circuit 8 would require a significant rearrangement of the components inside the housing of Fig. 2, and would make it more difficult to ensure the capacitors could be placed together in a separated portion of the housing for the sake of ensuring space for a safe gas-discharge to occur.
Thus there exist two remaining, practical possibilities for the relative placement of capacitors 4 and 5 in Kanazwa’s housing: the option disclosed in Kanazawa and the claimed option.
Not later than the effective filing date of the claimed invention, it would have been obvious for the person of ordinary skill in the art to have experimented and tried the other of the above two design choice possibilities for the capacitor placement in the apparatus of Kanazawa, with just as reasonable a likelihood of success in determining an optimum and workable solution, resulting in the power conversion device in which the first capacitor is arranged at a position farther away from the control circuit than the second capacitor.
In re claim 2, Kanazawa as modified discloses a rectifier circuit (Fig. 1: 3) that is mounted on the first substrate (30; see Fig. 2) and rectifies an external AC voltage (from AC source 1 in Fig. 1) and charges the first capacitor and the second capacitor (col. 1: 22-26 and col. 2: 58-62),
wherein the first capacitor (4) is charged in a positive half cycle of the external AC voltage (as readily understood from the circuit schematic of Fig. 1: when the AC voltage from 1 is in a positively half-cycle, the upper diode in rectifier 3 will conduct to charge capacitor 4), and
wherein the second capacitor (5) is charged in a negative half cycle of the external AC voltage (as explained above, mutatis mutandis).
In re claim 3, Kanazawa as modified discloses wherein the control circuit (8) is mounted on the first substrate (30; see Fig. 2), and
wherein the first capacitor is arranged at a position farther away from the first substrate than the second capacitor (that is, after the above-proposed modification to Kanazawa to reverse the placement of first and second capacitors 4 and 5, the first capacitor 4 would be in a position farther away from the mounting location of control circuit 8 on the first substrate 30).
In re claim 4, Kanazawa discloses wherein each of the first capacitor and the second capacitor has a positive electrode terminal and a negative electrode terminal on the same surface (see Fig. 6: electrodes 4b, 5b).
In re claim 8, Kanazawa discloses wherein the first capacitor is physically bonded to the first substrate via a bonding member (col. 4: 23-34 the electrodes of the capacitors are buried in urethane resin 24 which bonds them to the first substrate).
In re claim 9, Kanazawa discloses wherein the first capacitor and the second capacitor are physically bonded to each other via a bonding member (id.: the urethane resin 24 likewise bonds the two capacitors to one another).
Allowable Subject Matter
Claims 5-7 and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, the closest prior art in Kanazawa, modified as proposed above in this Office action, discloses the invention according to claim 1, but does not further disclose a second substrate arranged with a direction substantially perpendicular to a plane of the first substrate used as a plane direction, wherein the first capacitor and the second capacitor are mounted on the second substrate. More specifically, Kanazawa only discloses the first substrate, on which the capacitors are mounted.
Furthermore, the additional prior art on record does not disclose or suggest an obvious modification that would achieve the claimed features.
Claims 6-7 both depend from claim 5 and so would be allowable for the same reasons.
With respect to claim 5, the closest prior art in Kanazawa, modified as proposed above in this Office action, discloses the invention according to claim 1, but does not further disclose a third substrate electrically connected to the first substrate, wherein the control circuit is mounted on the third substrate, and wherein the first capacitor is arranged at a position farther away from the third substrate than the second capacitor. More specifically, Kanazawa only discloses the first substrate, on which the control circuit and the capacitors are mounted.
Furthermore, the additional prior art on record does not disclose or suggest an obvious modification that would achieve the claimed features.
Claims 11-13 each depend, either directly or indirectly, from claim 10 and so would be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2014/0321171 discloses a power conversion device with rectifier, inverter, and DC link capacitors that are arranged with their axial direction parallel to a first substrate.
US 2021/0111660 discloses a power conversion device with rectifier, inverter, smoothing and snubber capacitors and control circuit mounted to a substrate, wherein smoothing capacitors are arranged further from the substrate than snubber capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FRED E FINCH III/Primary Examiner, Art Unit 2838
Prosecution Insights