DETAILED ACTION
This office action is in response to the application filed on 12/18/2024. Claims 1-14 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 12/18/2024 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/18/2024 and 09/17/2025 been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 10, 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
For claims 3, 10, 14, Applicants recite the limitations in claim 1 “… a controllable switching transistor …”, and further recite in claims 3, 10, 14 “ … the switching transistor …” without proper antecedence basis. It is not clear that Applicant recited “ … the switching transistor…” is intended referring to the previously recited controllable switching transistor, or different switching transistor other than the controllable switching transistor. Therefore, the metes and bounds of the claim are unclear. Applicant’s correction is required. Applicant reminded to consistently recite the limitations throughout the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-12, 14 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by ISHIKAWA et al. (US Patent or PG Pub. No. 20200099300, hereinafter ‘300).
Claim 1, ‘300 teaches a buck-boost converter (e.g., see Fig. 1-20), comprising:
a controller (e.g., 90), a controllable switching transistor (e.g., 21), a freewheeling diode (e.g., 22), and a Boost circuit (e.g., the circuits comprising L3, D3, D4, C1, C2), wherein a first terminal (e.g., the collector of 21) of the controllable switching transistor is connected to a positive input terminal (e.g., Ni) of the buck-boost converter, and a second terminal (e.g., N1) of the controllable switching transistor is connected to a positive input terminal of the Boost circuit (e.g., see Fig. 1, 11, 12); an anode of the freewheeling diode is connected to a negative input terminal (e.g., 11) of the buck- boost converter, and a cathode of the freewheeling diode is connected to the second terminal of the controllable switching transistor (e.g., see Fig. 1, 11, 12); and the controller is configured to: control the buck-boost converter to operate in a buck mode in a case that an input voltage (e.g., Vin) of the buck-boost converter is greater than a preset voltage (e.g., when Vin>Vdc, see [0016][0070][0071], Fig. 6), and control the buck-boost converter to operate in a boost mode in a case that the input voltage of the buck- boost converter is less than the preset voltage (e.g., when Vin<Vdc, see [0018][0081][0082], Fig. 8).
Claim 2, ‘300 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the preset voltage is equal to an output voltage (e.g., Vdc) of the Boost circuit (e.g., see [0016][0070][0071], [0018][0081][0082], Fig. 6, 7); the Boost circuit is a two-level Boost circuit (e.g., Vdc, see Fig. 1) or a three-level Boost circuit; and in a case that the Boost circuit is the three-level Boost circuit, the three-level Boost circuit is a symmetrical three-level Boost circuit or a three-level Boost circuit with a flying capacitor ( (Examiner note: the recited limitation “a two-level Boost circuit or a three-level Boost circuit” have been interpreted as alternative, or optional between one another. Therefore, a three-level Boost circuit has been interpreted and treated as optional and did not given patentable weight in the claim 2 rejection).
Claim 3, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein in a case that the Boost circuit is the two-level Boost circuit, in the boost mode, the controller is configured to control the controllable switching transistor to operate in a normal-on state (e.g., 21 being always ON), and the two-level Boost circuit operates in a boost state (e.g., Boost Mode, see Fig. 3); and in the buck mode, the controller is configured to control the controllable switching transistor to operate in a state (e.g., 21 under PWM control during buck mode) same as a state of the switching transistor in the two-level Boost circuit (e.g., 31 under PWM control during boost mode, see Fig. 3), and the two-level Boost circuit operates in a buck state (e.g., the operation of 31 and 35 under Buck mode, see Fig. 1, 3).
Claim 4, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the two-level Boost circuit comprises: a first switching transistor (e.g., 31), an inductor (e.g., 45), and a first diode (e.g., 32); a first terminal of the inductor is connected to the second terminal of the controllable switching transistor, and a second terminal of the inductor is connected to an anode of the first diode (e.g., see Fig. 1); a first terminal of the first switching transistor is connected to the second terminal of the inductor, and a second terminal of the first switching transistor is connected to the anode of the freewheeling diode (e.g., see Fig. 1); and a cathode of the first diode is connected to a positive output terminal of the buck-boost converter (e.g., Vdc, see Fig. 1).
Claim 5, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein in a case that the three-level Boost circuit is the symmetrical three-level Boost circuit, in the boost mode, the controller is configured to control the controllable switching transistor to operate in a normal-on state, and the symmetrical three-level Boost circuit operates in a boost state; and in the buck mode, the controller is configured to control the controllable switching transistor to operate in a state same as a state of the switching transistor in the symmetrical three-level Boost circuit, and the symmetrical three-level Boost circuit operates in a buck state (Examiner note: since the recited limitation “the three-level Boost circuit” was treated as optional and did not given patentable weight as discussed in claim 2 rejection above, the limitations recited in claim 5 is also treated the same as optional and not given patented weight).
Claim 6, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the symmetrical three-level Boost circuit comprises: an inductor, a first switching transistor, a second switching transistor, a first diode, and a second diode; a first terminal of the inductor is connected to the second terminal of the controllable switching transistor, a second terminal of the inductor is connected to an anode of the first diode, and a cathode of the first diode is connected to a positive output terminal of the buck-boost converter; a first terminal of the first switching transistor is connected to the second terminal of the inductor, a second terminal of the first switching transistor is connected to a first terminal of the second switching transistor, and a second terminal of the second switching transistor is connected to the anode of the freewheeling diode; and the second terminal of the first switching transistor is connected to an output midpoint of the buck-boost converter (Examiner note: since the recited limitation “the three-level Boost circuit” was treated as optional and did not given patentable weight as discussed in claim 2 rejection above, the limitations recited in claim 6 is also treated the same as optional and not given patented weight).
Claim 7, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein in a case that the three-level Boost circuit is the three-level Boost circuit with the flying capacitor, in the boost mode, the controller is configured to control the controllable switching transistor to operate in a normal-on state, and the three-level Boost circuit with the flying capacitor operates in a boost state; and in the buck mode, the controller is configured to perform synchronous triggering on the controllable switching transistor and a switching transistor in the three-level Boost circuit with the flying capacitor, wherein the synchronous triggering refers to rising edges or falling edges of corresponding driving signals are synchronized (Examiner note: since the recited limitation “the three-level Boost circuit” was treated as optional and did not given patentable weight as discussed in claim 2 rejection above, the limitations recited in claim 7 is also treated the same as optional and not given patented weight).
Claim 8, ‘300 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the three-level Boost circuit with the flying capacitor comprises: an inductor, a first switching transistor, a second switching transistor, a first diode, a second diode, the flying capacitor, and a flying diode; a first terminal of the inductor is connected to the second terminal of the controllable switching transistor, a second terminal of the inductor is connected to an anode of the first diode, and a cathode of the first diode is connected to a positive output terminal of the buck-boost converter through the second diode; a first terminal of the first switching transistor is connected to the second terminal of the inductor, a second terminal of the first switching transistor is connected to a first terminal of the second switching transistor, and a second terminal of the second switching transistor is connected to the anode of the freewheeling diode; a first terminal of the flying capacitor is connected to a cathode of the first diode, and a second terminal of the flying capacitor is connected to a second terminal of the first switching transistor; and an anode of the flying diode is connected to the second terminal of the first switching transistor, and a cathode of the flying diode is connected to an output midpoint of the buck-boost converter (Examiner note: since the recited limitation “the three-level Boost circuit” was treated as optional and did not given patentable weight as discussed in claim 2 rejection above, the limitations recited in claim 8 is also treated the same as optional and not given patented weight).
Claim 11, ‘300 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the inductor is arranged separately from other components in the Boost circuit (e.g., 45 being arranged separately from other components, such as before 31, 32, in the Boost circuit, see Fig. 1, 11).
Claim 12, ‘300 teaches the limitations of claim 1 as discussed above. It further teaches a power supply system (e.g., see Fig. 1, 11), comprising the buck-boost converter according to claim 1, and further comprising an inverter circuit (e.g., 60), wherein an output terminal of the buck-boost converter is connected to an input terminal of the inverter circuit (e.g., see Fig. 1, 11).
Claim 14, ‘300 teaches the limitations of claim 5 as discussed above. It further teaches that wherein the controller is configured to control the controllable switching transistor to operate in the normal-on state, in a case that the switching transistor in the Boost circuit is turned on, a direct-current power supply charges an inductor in the Boost circuit; in a case that the switching transistor in the Boost circuit is turned off, both the direct-current power supply and the inductor supply power to a load; and the buck-boost converter operates in the boost mode; and the controller is further configured to control the controllable switching transistor and the switching transistor in the Boost circuit to be turned on and turned off simultaneously, in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned on, the direct-current power supply charges the inductor in the Boost circuit; in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned off, the inductor supplies power to the load; and the buck-boost converter operates in the buck mode (Examiner note: claim 14 depending on claim 5 which recited the Boost circuit being “the three-level Boost circuit”, and was treated as optional and did not given patentable weight as discussed in claim 2 rejection above, the limitations recited in claim 14 is also treated the same as optional and not given patented weight).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Claim 9 is rejected under 35 U.S.C. 103(a) as being unpatentable over ISHIKAWA et al. (US Patent or PG Pub. No. 20200099300, hereinafter ‘300), in view of Manabe et al. (US Patent or PG Pub. No. 20090051346, hereinafter ‘346).
Claim 9, ‘300 teaches the limitations of claim 1 as discussed above. ‘300 further teaches that wherein the buck-boost converter further comprises a switch (e.g., 25), and the switch is connected in parallel with the controllable switching transistor and operates in a same state as the controllable switching transistor (e.g., Both 21 and 25 are always ON when operating in Boost Mode, see Fig. 1, 3, 11, 13).
‘300 does not explicitly disclose that the controllable switching transistor comprises a diode reversely connected in parallel.
‘346 discloses a buck-boost converter having a controllable switching transistor (e.g., TR1, see Fig. 2). ‘346 further discloses that the controllable switching transistor comprises a diode reversely connected in parallel (e.g., D1 reversely connected in parallel to TR1, see Fig. 2) to allow a current to also flow in the forward direction of diode D1 when TR1 is OFF (e.g., see [0095][0096], Fig. 2).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘300 by including the diode reversely connected in parallel with the controllable switching transistor as taught by ‘346 in order of being able to provide a current path to allow a current to also flow in the forward direction of diode D1 when TR1 is OFF (e.g., see [0095][0096], Fig. 2).
Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over ISHIKAWA et al. (US Patent or PG Pub. No. 20200099300, hereinafter ‘300), in view of Gao (US Patent or PG Pub. No. 20190173383, hereinafter ‘383).
Claim 10, ‘300 teaches the limitations of claim 3 as discussed above. It further teaches that wherein the controller is configured to control the controllable switching transistor to operate in the normal-on state (e.g., during Boost Mode, 21 being Always ON), in a case that the switching transistor (e.g., 31) in the Boost circuit is turned on, a direct-current power supply charges an inductor (e.g., 45) in the Boost circuit (e.g., while 31 in ON state of the PWM control during Boost Mode operation, see Fig. 3); in a case that the switching transistor (e.g., 31) in the Boost circuit is turned off, both the direct-current power supply and the inductor supply power to a load (e.g., powering 60 and 300, while 31 in OFF state of the PWM control during Boost Mode operation, see Fig. 3); and the buck-boost converter operates in the buck mode (e.g., the buck mode, see Fig. 3).
‘300 does not explicitly disclose that the buck-boost converter operates in the boost mode; and the controller is further configured to control the controllable switching transistor and the switching transistor in the Boost circuit to be turned on and turned off simultaneously, in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned on, the direct-current power supply charges the inductor in the Boost circuit; in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned off, the inductor supplies power to the load.
‘383 discloses a buck-boost converter (e.g., see Fig. 3-4) operating in the boost mode (e.g., see [0040]); and the controller (e.g., 36) is further configured to control the controllable switching transistor (e.g., 24) and the switching transistor (e.g., 28) in the Boost circuit to be turned on and turned off simultaneously, in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned on (e.g., both 24 and 28 are ON during Tincrease in the boost mode, see [0040], Fig. 3, 4), the direct-current power supply charges the inductor in the Boost circuit (e.g., inductor 32 being charged by Vin during both 24 and 28 are ON, see Fig. 3, 4); in a case that both the controllable switching transistor and the switching transistor in the Boost circuit are controlled to be turned off (e.g., both 24 and 28 are OFF during Tdecrease in the boost mode, see [0040], Fig. 3, 4), the inductor supplies power to the load (e.g., 32 supplying power to load 12 during both 24 and 28 are ON and S2 is ON during Tdecrease, see Fig. 3, 4); and the buck-boost converter operates in the buck mode (e.g., 50 operating in buck mode, see [0036][0047][0055][0056]).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘300 by including the buck-boost converter control method including to control the controllable switching transistor and the switching transistor in the Boost circuit to be turned on and turned off simultaneously operating in the boost mode when operating in boost mode as taught by ‘383 in order of being able to provide the buck-boost converter less complex, and less expensive (e.g., see [0003][0033], Fig. 3).
Claim 13 is rejected under 35 U.S.C. 103(a) as being unpatentable over ISHIKAWA et al. (US Patent or PG Pub. No. 20200099300, hereinafter ‘300), in view of Hintz et al. (US Patent or PG Pub. No. 20120068537, hereinafter ‘537).
Claim 13, ‘300 teaches the limitations of claim 12 as discussed above. It further teaches that the input terminal of the buck-boost converter is connected to a direct-current power supply the output terminal of the buck-boost converter is connected to the input terminal of the inverter circuit (e.g., see Fig. 1, 11).
‘300 does not explicitly disclose that the power supply system comprises a plurality of buck-boost converters; an input terminal of each of the plurality of buck-boost converters is connected to a corresponding direct-current power supply, wherein the direct-current power supply is a new energy power supply or a battery, and the new energy power supply comprises photovoltaic strings or wind turbines; and output terminals of the plurality of buck-boost converters are connected in parallel and then are connected to the input terminal of its load circuit.
‘537 discloses a power supply system comprises a plurality of buck-boost converters (e.g., see Fig. 17, 19); an input terminal of each of the plurality of buck-boost converters is connected to a corresponding direct-current power supply (e.g., the primary power source G1), wherein the direct-current power supply is a new energy power supply or a battery , and the new energy power supply comprises photovoltaic strings or wind turbines (e.g., see [0066], Fig. 17, 19); and output terminals of the plurality of buck-boost converters are connected in parallel and then are connected to the input terminal of the load (e.g., G2 when in G1-G2 charging mode, see Fig. 12, 17, 19).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘300 by including the power supply system comprises a plurality of parallel connected buck-boost converters as taught by ‘537 in order of being able to provide the power supply system having a plurality of buck-boost converters with lower cost and reduced parasitic losses (e.g., see [0121]).
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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