DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Receipt of the Amendment, filed on December 18, 2024, is acknowledged.
Cancellation of claims 11-13, 21 and 25 has been entered.
Claims 1-10, 14-20 and 22-24 are pending in the instant application.
The substitute specification, filed December 18, 2024, has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6, 7 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et al. (US 2021/0333608 A1).
Regarding claim 1, Yao discloses an array substrate comprising a plurality of scanning lines (61) and a plurality of data lines (81), wherein the plurality of data lines (61) are intersected with the plurality of scanning lines (81) to define a plurality of sub-pixel areas; the scanning line (61) comprises a plurality of sub-scanning lines (611, 612) spaced apart from each other and a connection line (2) connecting two adjacent sub-scanning lines (611, 612); and the array substrate further comprises a base substrate (1) and a plurality of conductive layers (¶[0043]) provided on a side of the base substrate, and the sub-scanning line (611, 612) and the connection line (2) are arranged in different conductive layers respectively (Fig. 2A-2C).
Regarding claim 2, Yao discloses an array substrate wherein the array substrate further comprises a plurality of transistors (¶[0057]), and the plurality of conductive layers (82/62, Figs. 2B-2C) comprise: a first conductive layer (62), provided on the side of the base substrate, and comprising a gate electrode of the transistor (¶[0058]); and a second conductive layer (82), provided on a side, away from the base substrate, of the first conductive layer, and comprising a source electrode and a drain electrode of the transistor (¶[0060]), wherein the sub-scanning line (611, 612) is arranged in the first conductive layer (Fig. 2C).
Regarding claim 6, Yao discloses an array substrate wherein the scanning line (611, 612) extends in a first direction, the sub-scanning lines are arranged in the first direction, the sub-scanning line has a head end and a tail end (Fig. 2A), and the tail end of a previous sub-scanning line is connected to the head end of a next the sub-scanning line by the connection line (Fig. 2A); and an orthographic projection, on the base substrate, of the connection line (2) connecting the two adjacent sub-scanning lines (611, 612) is at least partially overlapped with orthographic projections, on the base substrate, of the two adjacent sub-scanning lines (611, 612).
Regarding claim 7, Yao discloses an array substrate wherein the two adjacent sub-scanning lines (611, 612) comprises a first sub-scanning line and a second scanning line, and the tail end of the first sub-scanning line is provided next to the head end of the second sub-scanning line in the first direction (Fig. 2A).
Regarding claim 23, Yao discloses an array substrate wherein the connection line (2) is located between transistors of two adjacent sub-pixel area arranged in an extension direction of the scanning line (Fig. 2A).
Claim(s) 1-3, 6-7 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih (US 2007/0222936 A1).
Regarding claim 1, Shih discloses an array substrate comprising a plurality of scanning lines (632) and a plurality of data lines (640), wherein the plurality of data lines (632) are intersected with the plurality of scanning lines (632) to define a plurality of sub-pixel areas; the scanning line (632) comprises a plurality of sub-scanning lines (Fig. 6) spaced apart from each other and a connection line (634) connecting two adjacent sub-scanning lines (Fig. 6); and the array substrate further comprises a base substrate (310) and a plurality of conductive layers (360, 324, 326) provided on a side of the base substrate, and the sub-scanning line (632) and the connection line (634) are arranged in different conductive layers respectively (Fig. 6, ¶[0047-0048], the sub-scanning layers and the connection line are formed in different layers in similar method described for the invention shown in Figs. 4A-4J).
Regarding claim 2, Shih discloses an array substrate wherein the array substrate further comprises a plurality of transistors (120), and the plurality of conductive layers comprise: a first conductive layer (322), provided on the side of the base substrate, and comprising a gate electrode (322) of the transistor; and a second conductive layer (324/326), provided on a side, away from the base substrate, of the first conductive layer, and comprising a source electrode (324) and a drain electrode (326) of the transistor, wherein the sub-scanning line (632) is arranged in the first conductive layer.
Regarding claim 3, Shih discloses an array substrate wherein the connection line (634) is arranged in the second conductive layer (Fig. 6).
Regarding claim 6, Shih discloses an array substrate wherein the scanning line (632) extends in a first direction, the sub-scanning lines (632) are arranged in the first direction, the sub-scanning line has a head end and a tail end, and the tail end of a previous sub-scanning line is connected to the head end of a next the sub-scanning line by the connection line (634); and an orthographic projection, on the base substrate, of the connection line (634) connecting the two adjacent sub-scanning lines (632) is at least partially overlapped with orthographic projections, on the base substrate, of the two adjacent sub-scanning lines (Fig. 6).
Regarding claim 7, Shih discloses an array substrate wherein the two adjacent sub-scanning lines (632) comprises a first sub-scanning line and a second scanning line, and the tail end of the first sub-scanning line is provided next to the head end of the second sub-scanning line in the first direction (Fig. 6).
Regarding claim 23, Shih discloses an array substrate wherein the connection line (634) is located between transistors of two adjacent sub-pixel area arranged in an extension direction of the scanning line (632).
Claim(s) 1-3, 6-7 and 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2010/0225859 A1).
Regarding claim 1, Tsai discloses an array substrate comprising a plurality of scanning lines (60) and a plurality of data lines (61), wherein the plurality of data lines (61) are intersected with the plurality of scanning lines (60) to define a plurality of sub-pixel areas; the scanning line (60) comprises a plurality of sub-scanning lines (601, 602) spaced apart from each other and a connection line (67) connecting two adjacent sub-scanning lines (Fig. 6); and the array substrate further comprises a base substrate (70) and a plurality of conductive layers (640, 642, 643) provided on a side of the base substrate, and the sub-scanning line (601, 602) and the connection line (67) are arranged in different conductive layers respectively (Figs. 6-7).
Regarding claim 2, Tsai discloses an array substrate wherein the array substrate further comprises a plurality of transistors (64), and the plurality of conductive layers comprise: a first conductive layer (640), provided on the side of the base substrate, and comprising a gate electrode (640) of the transistor; and a second conductive layer (642/643), provided on a side, away from the base substrate, of the first conductive layer, and comprising a source electrode (642) and a drain electrode (643) of the transistor, wherein the sub-scanning line (601, 602) is arranged in the first conductive layer (Figs. 6-7).
Regarding claim 3, Tsai discloses an array substrate wherein the connection line (67) is arranged in the second conductive layer (Figs. 6-7).
Regarding claim 6, Tsai discloses an array substrate wherein the scanning line (60) extends in a first direction, the sub-scanning lines (601, 602) are arranged in the first direction, the sub-scanning line has a head end and a tail end, and the tail end of a previous sub-scanning line is connected to the head end of a next the sub-scanning line by the connection line (67); and an orthographic projection, on the base substrate, of the connection line (67) connecting the two adjacent sub-scanning lines (601, 602) is at least partially overlapped with orthographic projections, on the base substrate, of the two adjacent sub-scanning lines (Fig. 6).
Regarding claim 7, Tsai discloses an array substrate wherein the two adjacent sub-scanning lines (601, 602) comprises a first sub-scanning line and a second scanning line, and the tail end of the first sub-scanning line is provided next to the head end of the second sub-scanning line in the first direction (Fig. 6).
Regarding claim 23, Tsai discloses an array substrate wherein the connection line (67) is located between transistors of two adjacent sub-pixel area arranged in an extension direction of the scanning line (601, 602).
Regarding claim 24, Tsai discloses a display panel comprising a color film substrate (2’, Fig. 18), provided on a side of the array substrate (2) and comprising a color film layer (22’), the color film layer comprising a light-shielding portion (28’) and a plurality of filtering portions (22’) defined by the light-shielding portion, and the filtering portions (22’) being provided to respectively correspond to the sub-pixel areas in a direction perpendicular to the base substrate; and a liquid crystal layer (21’), provided between the array substrate (2) and the color film substrate (2’), wherein an orthographic projection, on the base substrate, of the connection line is located within an orthographic projection, on the base substrate, of the light-shielding portion (Fig. 18, light-shielding portion 28’ overlaps the scanning line 20 and the data lines 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2021/0333608 A1).
Regarding claim 8, Yao fails to disclose an interval between the tail end of the first sub-scanning line and the head end of the second the sub-scanning line is not less than 3 µm. One skilled in the art would have reasonably contemplated optimization of the interval between adjacent sub-scanning lines in order to control parasitic capacitance between the scanning line and the data line, as an obvious matter of design engineering. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to one having ordinary skill in the art at the time of effective filling of the claimed invention in order to control parasitic capacitance between the scanning line and the data line, since optimization of workable ranges is considered within the skill of the art.
Allowable Subject Matter
Claims 4, 5, 9-10, 14-20 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim(s) 4, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 4, and specifically comprising the limitation of a third conductive layer, provided between the base substrate and the first conductive layer, and comprising a light-shielding structure, wherein the connection line is arranged in the third conductive layer.
Regarding claim(s) 5, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 5, and specifically comprising the limitation of a third conductive layer, provided between the base substrate and the first conductive layer, and comprising a light-shielding structure; and a fourth conductive layer, provided on a side, close to the base substrate, of the third conductive layer, or between the third conductive layer and the first conductive layer, or between the first conductive layer and the second conductive layer, or on a side, away from the base substrate, of the second conductive layer, wherein the connection line is arranged in the fourth conductive layer.
Regarding claim(s) 9, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 9, and specifically comprising the limitation of the array substrate further comprises an active layer, a first gate insulating layer and an interlayer dielectric layer, the active layer is provided between the base substrate and the first conductive layer, the first gate insulating layer is provided between the active layer and the first conductive layer, and the interlayer dielectric layer is provided between the first conductive layer and the second conductive layer; the connection line is arranged in the second conductive layer, the interlayer dielectric layer is provided with a first through-hole passing through the interlayer dielectric layer, an orthographic projection, on the base substrate, of the first through-hole is at least partially overlapped with the orthographic projection, on the base substrate, of the sub-scanning line, and the orthographic projection, on the base substrate, of the first through-hole is at least partially overlapped with the orthographic projection, on the base substrate, of the connection line; and the connection line is connected to the sub-scanning line through the first through-hole.
Regarding claim(s) 14, claims(s) 14 is/are allowable for the reasons given in claim(s) 9 because of its/their dependency status from claim(s) 9.
Regarding claim(s) 10, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 10, and specifically comprising the limitation of a third conductive layer provided between the base substrate and the first conductive layer, and comprising a light-shielding structure, the array substrate further comprises a buffer layer and a first gate insulating layer, and the buffer layer and the first gate insulating layer are stacked between the third conductive layer and the first conductive layer in a direction away from the base substrate; the connection line is arranged in the third conductive layer, the buffer layer and the first gate insulating layer are provided with a first through-hole passing through the buffer layer and the first gate insulating layer.
Regarding claim(s) 15, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 15, and specifically comprising the limitation of the sub-scanning line further comprises an intermediate portion between the head end and the tail end; and the two adjacent sub-scanning lines comprises a first sub-scanning line and a second sub-scanning line, the intermediate portion of the second sub-scanning line is provided at a side, of the tail end of the first sub-scanning line in the first direction, and the head end of the second sub-scanning line is provided next to the tail end of the first sub-scanning line in a second direction, the second direction being perpendicular to the first direction.
Regarding claim(s) 16-20, claims(s) 16-20 is/are allowable for the reasons given in claim(s) 15 because of its/their dependency status from claim(s) 15.
Regarding claim(s) 22, the references of the Prior Art of record fail to teach or suggest the combination of the limitations as set forth in claim(s) 22, and specifically comprising the limitation of the plurality of transistors are arranged to form rows along an extension direction of the scanning line, every three transistors in a same row of transistors are connected to a same sub-scanning line, and the sub-scanning line has a length of 90-200 µm.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Peng et al. (CN 104808376 B) discloses an array substrate and a display device, wherein the array substrate comprises: a substrate, a plurality of scan lines on the substrate, the plurality of scanning lines extending along the first direction, a first insulating layer on the plurality of scan lines; a plurality of data lines arranged on the first insulating layer, the plurality of data lines extending along the second direction, a plurality of pixel units arranged in a matrix, the pixel unit comprises a TFT switch and a pixel electrode.
Li (US 2015/0123135 A1) discloses array substrate including a display region and a frame region surrounding the display region, the display region including a plurality of data lines, a plurality of scan lines and a plurality of scan connection lines.
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mariceli Santiago whose telephone number is (571) 272-2464. The examiner can normally be reached on Monday-Friday from 8:00 AM to 4:00 PM.
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/Mariceli Santiago/Primary Examiner, Art Unit 2879
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