DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is in response to the communication filed on 06/18/2026. Claims 1, 5-16, 18, 20 and 25-26 are pending in this application.
Response to Arguments
Applicant’s arguments filed 06/18/2026 have been fully considered but they are not persuasive. Applicant argues:
a.
Applicant argues that “The cited references fail to teach the feature of “constructing a target protocol that comprises the internal address of the target receiving device,” and “According to paragraph [0056] and FIG. 5, FIG. 6 of Harriman, "The corresponding protocol circuitry (e.g., of ports 520, 525) may be utilized to generate packets (e.g., 530, 535) with packet headers according to each of the flit mode and non-flit mode", it can be clearly seen that the corresponding protocol circuitry (e.g., of ports 520, 525) may be utilized to generate packets (e.g., 530, 535) with packet headers, rather than to generate a protocol. However, in claim 1 of the present application, the feature of constructing a target protocol that comprises the internal address of the target receiving device is recited. Thus, Applicant believes that Harriman fails to disclose the above distinguished features (Reply, pp. 10-11).”
a.
Examiner respectfully disagrees. In the Office Action (05/14/2026, Page 5), Examiner analyzed the claimed “constructing a target protocol” based on claims 1, 18 and 20, as well as the instant Specification: “Examiner notes that the applicant has claimed "constructing/construct a target protocol" in independent claims 1 and 20, also claimed "the target protocol is a protocol that is constructed" in independent claim 18. According to the instant Specification [0069], "the target protocol" includes the internal address of the target receiving device, and is a specially designed general-purpose communication protocol. Applying the broadest reasonable interpretation in light of the specification and taking into account the meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, "the target protocol" is considered as a set of rules to determine the addresses used for communication between the devices.” Examiner maintains the result of the analysis, therefore the rejection of “constructing a target protocol that comprises the internal address of the target receiving device” is maintained.
b.
Applicant also argues that “The cited references fail to teach the feature of "receiving the internal address of the target receiving device and a corresponding address type, which are returned by the host end in a way of calling the callback function in the device key information of the target transmitting device,” and “that is, in Khatri, there is nothing about "callback function", the assigned PCIE capability identifier is different from the "callback function" (Reply, pp. 11-12).
b.
Examiner respectfully disagrees. Examiner notes that the even/interrupt handler technique is used here to teach calling the callback function.
Response to Amendment
The claim objections to claims 4 and 20 are now withdrawn in view of the claim amendments
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10, 18, 20 and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), in view of US 20190146853 A1 (hereinafter Xu), and in further view of US 20130124768 A1 (hereinafter Khatri).
For Claim 1, Cannata teaches a method for peer-to-peer communication between devices, applied to a target transmitting device (Cannata, FIG. 1, FIG. 7; para. [0097] “… FIG. 7 provides an example flow diagram for the handling of a peer-to-peer data transfer in a compute unit established according to FIG. 6. FIG. 7 includes a flow diagram that illustrates an operational example of PCIe fabric enabled peer-to-peer data transfers in compute units for any of the systems discussed herein, such as for platform 100 of FIG. 1, system 200 of FIG. 2, or processor 300 of FIG. 3 …”) and comprising:
obtaining an internal address of a target receiving device, wherein both the target transmitting device and the target receiving device are peripheral component interconnect express (PCIE) devices (Cannata teaches determining the target PCIe destination addresses corresponding to the source PCIe device; Examiner notes that the limitation “an internal address” is the only “address” recited in the independent claims (e.g. there is no “an external address” recited to further limit the interpretation of the “internal address), therefore it is considered as a destination PCIe address corresponding to the PCIe device peer-to-peer data communications; FIG. 7; para. [0098] “… Management driver 141 determines (702) instructions to issue to a device driver associated with a source PCIe device or initiator PCIe device. These instructions indicate addresses corresponding to the peer-to-peer address ranges. The device driver for the source PCIe device then uses these addresses corresponding to the peer-to-peer address ranges. The device driver for the source PCIe device issues instructions to the source PCIe device to initiate a peer-to-peer data transfer. These instructions indicate one or more target addresses corresponding to the peer-to-peer address ranges …”); …; and
transmitting the target data packet to the target receiving device (Cannata teaches the PCIe traffic being transmitted to the PCIe devices and/or PCIe switches; FIG. 7; para. [0099] “… The source PCIe device then performs (703) the data transfer by directing communications to the one or more target addresses. The PCIe device is typically not aware that these one or more target addresses correspond to an address trap established in the PCIe fabric, and will perform the data transfer as the source PCIe device normally would for a non-peer-to-peer transfer. The one or more target addresses correspond to a target PCIe device, but comprise virtual addresses previously determined by management driver 141 which are separate and different than virtual addresses determined for the target PCIe device by a host processor during device enumeration. The source PCIe device may perform the data transfer as a direct memory access (DMA) data transfer. Instead of this DMA traffic being directed to the host processor, the address trap redirects this traffic through the PCIe fabric to the target PCIe device-bypassing the host processor …”) to cause the target receiving device to: analyze, after receiving the target data packet, the target protocol carried in the target data packet to obtain the internal address, and perform data processing on the internal address (Cannata teaches the PCIe devices and/or PCIe switches using an address table of relationship to extract and translate the destination address information and route the PCIe traffic; FIG. 7; para. [0100] “… An address trap of one of the PCIe switches detects (704) the data transfer as using an address from the address ranges for peer-to-peer data transfers. The address trap may redirect the detected PCIe data transfer to the destination PCIe device without passing through host memory or the host processor. For example, the address trap may refer to an address table of relationships between address ranges for peer-to-peer data transfers and corresponding physical PCIe address of the corresponding PCIe device …”);
before the step of obtaining the internal address of the target receiving device, the method further comprises: … to cause the host end to: register the target transmitting device and return the internal address of the target receiving device (Cannata teaches an enumeration process initializing the PCIe device in the host processor, the host processor assigning a BAR and address range for the PCIe device, and establishing peer-to-peer relationship for the PCIe devices; FIG. 1, FIG. 2; para. [0045] “… while establishing compute unit 160 (e.g. compute unit 160 of domain 'x' of PCIe fabric 151), management processor 110 may configure one or more PCIe switches 150 communicatively coupling the physical components of the domain to provide functionality for peer-to-peer data transfers using peer-to-peer relationship 180 … processor 120 may establish address ranges associated with peer-to-peer data transfers for one or more of the PCIe endpoint devices of the domain (e.g. during or following PCIe enumeration) …”; para. [0060] “… An enumeration process discovers the PCIe device as able to communicate with the host processor, and initializes the PCIe device in the host processor for later interaction over a corresponding PCIe interface. This enumeration process also includes the host processor assigning a base address register (BAR) and address range or space within a system memory space of the host processor. This BAR and address range is used for memory mapped access to the PCIe device, and does not typically correspond to physical memory or RAM coupled to the host processor …”);
wherein the device key information of the target transmitting device at least comprises a device identification (Cannata teaches PCIe enumeration including identifying PCIe devices via device identifiers; Examiner notes that the limitation “at least comprises A, B, and C” is considered to limit a conjunctive list of all items; para. [0060] “… An enumeration process discovers the PCIe device as able to communicate with the host processor, and initializes the PCIe device in the host processor for later interaction over a corresponding PCIe interface …”; para. [0076] “… Processing resources can have unique identifiers assigned thereto for use in identification by the management processor and for identification on the PCIe fabric …”), a type of matched receiving device (Cannata teaches establishing peer-to-peer relationship for the compatible PCIe devices, therefore the device type being identifiable to the peer devices; FIG. 1, FIG. 2; para. [0045] “… while establishing compute unit 160 (e.g. compute unit 160 of domain 'x' of PCIe fabric 151), management processor 110 may configure one or more PCIe switches 150 communicatively coupling the physical components of the domain to provide functionality for peer-to-peer data transfers using peer-to-peer relationship 180 … processor 120 may establish address ranges associated with peer-to-peer data transfers for one or more of the PCIe endpoint devices of the domain (e.g. during or following PCIe enumeration) …”), …;
Cannata teaches PCIe data transmission/routing comprises the target PCIe destination addresses (Cannata, FIG. 1, FIG. 7; para. [0051], para. [0098]). Cannata does not explicitly teach, but Harriman teaches according to a preset protocol format, constructing a target protocol that comprises the internal address of the target receiving device, and generating a target data packet carrying the target protocol (Harriman teaches generating PCIe TLP packets according to a PCIe protocol format, the protocol format comprising address fields identifying the destination device; Examiner notes that the applicant has claimed “constructing/construct a target protocol” in independent claims 1 and 20, also claimed “the target protocol is a protocol that is constructed” in independent claim 18. According to the instant Specification [0069], “the target protocol” includes the internal address of the target receiving device, and is a specially designed general-purpose communication protocol. Applying the broadest reasonable interpretation in light of the specification and taking into account the meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, “the target protocol” is considered as a set of rules to determine the addresses used for communication between the devices; FIG. 5, FIG. 6; para.[0056] “… Turning to FIG. 5, a simplified block diagram 500 is shown illustrating an example PCIe link 505 coupling a first device 510 to a second device 515 … The port ( e.g., 520, 525) may include transmit and receive circuitry as well as logic (e.g., implemented in hardware circuitry) to implement one or more interconnect protocols governing operation of a corresponding connection. For instance, ports 520, 525 may each include circuitry to implement a layered protocol stack of a PCIe-based protocol … The corresponding protocol circuitry (e.g., of ports 520, 525) may be utilized to generate packets (e.g., 530, 535) with packet headers according to each of the flit mode and non-flit mode …”; para. [0059] “… Turning to FIG. 6, a representation 600 is illustrated of an example flit-mode packet (e.g., TLP) format. For instance, the flit-mode packet format may include a header base 605 composed of a set of fields (e.g., 640, 645) that may be parsed by a receiver to determine an overall length of the packet, as well as other information, such as an identifier of the source of the packet, address information (e.g., for a destination of the packet), a transaction identifier, among other example information. The fields and format of the header base 605 may be based on and correspond to the type of packet …”).
Harriman and Cannata are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the generating packets according to a PCIe protocol format techniques of Harriman with the system of Cannata to facilitate the PCIe communication in point-to-point interconnects, switch-based technology, and packetized protocol (Harriman, para. [0023]).
Cannata-Harriman does not explicitly teach, but Moertl teaches transmitting device key information of the target transmitting device to a host end for registration (Moertl teaches a PCIe device driver passing structured information (including device driver memory data structure address and parameters) to a host device driver services for registration; para. [0018] “… The device driver services are responsible for managing memory accessible by the PCIe endpoint, including the address translation and protection table (ATPT) and the address translation caches (ATCs) of the PCIe endpoint. …”; para. [0036] “… a method is provided for managing address translations. The method may comprise invoking, by a device driver, device driver services for initializing address translation entries in an address translation data structure of a root complex of the data processing system and passing, from the device driver to the device driver services, an address of a device driver memory data structure and registration modifiers …”).
Moertl and Cannata-Harriman are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the structured communication between a PCIe device and a host techniques of Moertl with the system of Cannata-Harriman to facilitate the PCIe device address translation (Moertl, para. [0016]).
Cannata-Harriman-Moertl does not explicitly teach, but Foong teaches a PCIe device information may include a quantity of addresses (Foong exemplifies that PCIe device 110 may include three BARs (i.e. Base Address Register) 111, 112, 113 in FIG. 1, therefore a PCIe device information may include multiple addresses; para. [0020] “… Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous ….”), an internal available device address (Foong teaches a BAR identifies an internal address (base address and size) for device communication; para. [0020] “… Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous ….”), …;
the internal available device address at least comprises a host mapping address, an internal address, an address length and an address type (Foong teaches that a PCIe device address being associated with a host assigned BAR address, a device address within an address range, an address range/length and an address type (e.g. memory vs I/O access addresses, 32-bit vs 64-bit); Examiner notes that the limitation “at least comprises A, B and C” is considered to limit a conjunctive list of all items; para. [0011] “… PCIe BAR mapping involves mapping a PCIe device into the memory-mapped address space (or other I/O address space) of the computer system. This mapping enables the computer system to address PCIe devices …”; para. [0020] “… In general, PCIe devices provide three address ranges. PCIe functionality allows memory-mapped I/O access to device control registers of up to six non-contiguously mapped memory regions, via six 32-bit BARs. At least one BAR is required for 32-bit operating systems, and two BARs are required for 64-bit operating systems. For 64-bit devices, these can be identified as Bar 0/1, Bar 2/3, and Bar 4/5.ABARis a pointer to a base address as well as identifying a length. Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous …”).
Foong and Cannata-Harriman-Moertl are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe device addressing structures techniques of Foong with the system of Cannata-Harriman-Moertl to facilitate the PCIe device communication connections (Foong, para. [0002]).
Cannata-Harriman-Moertl-Foong does not explicitly teach, but Xu teaches a PCI device is associated with a callback function (Xu, para. [0014] “… a generic callback framework is provided which comprises (a) callback function definitions pertaining to device-specific state management that are defined by the hypervisor, and (b) implementations of those callback functions that are defined by PCI device vendors and included in each PCI device's host device driver …”).
Xu and Cannata-Harriman-Moertl-Foong are analogous art because they are both related to PCI communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe device specific callback function techniques of Xu with the system of Cannata-Harriman-Moertl-Foong to facilitate the PCI device state management (Xu, para. [0014]).
Cannata-Harriman-Moertl-Foong-Xu does not explicitly teach, but Khatri teaches the step of obtaining the internal address of the target receiving device comprises: receiving the internal address of the target receiving device and a corresponding address type, which are returned by the host end in a way of calling the callback function in the device key information of the target transmitting device (Khatri teaches the host management entity sending messages/packets to the PCIe device through event/interrupt handler techniques; Examiner notes that the event/interrupt handler technique is used here to teach calling the callback function; FIG. 1; para. [0041] “… The BIOS SMI handler can be configured to receive the notification from the management controller 170 indicating that the management controller has a packet bound for a PCIE I/O device associated with the processor 104. The BIOS SMI handler can be configured to generate an SMI in response to the notification. The BIOS SMI handler can be configured to retrieve the data packet from the management controller 170 and to send a payload of the data packet to the PCIE I/O device using, for example, the assigned PCIE capability identifier. …”)
Khatri and Cannata-Harriman-Moertl-Foong-Xu are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices communication techniques of Khatri with the system of Cannata-Harriman-Moertl-Foong-Xu to facilitate handling user specific information communications (Khatri, para. [0003]).
For Claim 10, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches the method for the peer-to-peer communication between the devices according to claim 1, wherein the step of transmitting the device key information of the target transmitting device to the host end to cause the host end to register the target transmitting device comprises: transmitting the device key information of the target transmitting device to the host end to cause the host end to locally store the device key information transmitted by the target transmitting device (Khatri teaches a PCIe device sending messages/packets to host management entity, the host management entity storing the information in the messages/packets according to the property of an information handling system; FIG. 1; para. [0012] “… an information handling system can include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or use any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes …”; para. [0042] “… the BIOS 140 can be configured to detect an event at the secondary processor 104. For instance, the disk controller 150 or another PCIE I/O device can assert the event, such as any interrupt, at the secondary processor 104 after uploading a VDM packet or another data packet from a data source. In response to detecting the event, the BIOS 140 can be configured to query a buffer, a control register, or both, at the PCIE I/O device to determine the presence of the data packet. After determining the presence of the data packet at the PCIE I/O device, the BIOS SMI handler can be configured to generate an SMI. Further, the BIOS SMI handler can be configured to retrieve the data packet from the PCIE I/O device. The BIOS SMI handler can be configured to send a payload of the data packet to the management controller 170 …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices communication techniques of Khatri with the system of Cannata-Harriman-Moertl-Foong-Xu to facilitate handling user specific information communications (Khatri, para. [0003]).
For Claim 18, Cannata teaches a method for peer-to-peer communication between devices, applied to a target receiving device (Cannata, FIG. 1, FIG. 7; para. [0097] “… FIG. 7 provides an example flow diagram for the handling of a peer-to-peer data transfer in a compute unit established according to FIG. 6. FIG. 7 includes a flow diagram that illustrates an operational example of PCIe fabric enabled peer-to-peer data transfers in compute units for any of the systems discussed herein, such as for platform 100 of FIG. 1, system 200 of FIG. 2, or processor 300 of FIG. 3 …”) and comprising:
receiving a target data packet that is … and transmitted by a target transmitting device … (Cannata teaches the PCIe traffic being transmitted to the PCIe devices and/or PCIe switches; FIG. 7; para. [0099] “… The source PCIe device then performs (703) the data transfer by directing communications to the one or more target addresses. The PCIe device is typically not aware that these one or more target addresses correspond to an address trap established in the PCIe fabric, and will perform the data transfer as the source PCIe device normally would for a non-peer-to-peer transfer. The one or more target addresses correspond to a target PCIe device, but comprise virtual addresses previously determined by management driver 141 which are separate and different than virtual addresses determined for the target PCIe device by a host processor during device enumeration. The source PCIe device may perform the data transfer as a direct memory access (DMA) data transfer. Instead of this DMA traffic being directed to the host processor, the address trap redirects this traffic through the PCIe fabric to the target PCIe device-bypassing the host processor …”), wherein both the target transmitting device and the target receiving device are peripheral component interconnect express (PCIE) devices; … the target transmitting device obtains an internal address of the target receiving device … (Cannata teaches determining the target PCIe destination addresses corresponding to the source PCIe device; Examiner notes that the limitation “an internal address” is the only “address” recited in the independent claims (e.g. there is no “an external address” recited to further limit the interpretation of the “internal address), therefore it is considered as a destination PCIe address corresponding to the PCIe device peer-to-peer data communications; FIG. 7; para. [0098] “… Management driver 141 determines (702) instructions to issue to a device driver associated with a source PCIe device or initiator PCIe device. These instructions indicate addresses corresponding to the peer-to-peer address ranges. The device driver for the source PCIe device then uses these addresses corresponding to the peer-to-peer address ranges. The device driver for the source PCIe device issues instructions to the source PCIe device to initiate a peer-to-peer data transfer. These instructions indicate one or more target addresses corresponding to the peer-to-peer address ranges …”); and
analyzing the target protocol carried in the target data packet to obtain the internal address, and performing data processing on the internal address (Cannata teaches the PCIe devices and/or PCIe switches using an address table of relationship to extract and translate the destination address information and route the PCIe traffic; FIG. 7; para. [0100] “… An address trap of one of the PCIe switches detects (704) the data transfer as using an address from the address ranges for peer-to-peer data transfers. The address trap may redirect the detected PCIe data transfer to the destination PCIe device without passing through host memory or the host processor. For example, the address trap may refer to an address table of relationships between address ranges for peer-to-peer data transfers and corresponding physical PCIe address of the corresponding PCIe device …”);
wherein before the target transmitting device obtains the internal address of the target receiving device, the target transmitting device … to cause the host end to: register the target transmitting device and return the internal address of the target receiving device (Cannata teaches an enumeration process initializing the PCIe device in the host processor, the host processor assigning a BAR and address range for the PCIe device, and establishing peer-to-peer relationship for the PCIe devices; FIG. 1, FIG. 2; para. [0045] “… while establishing compute unit 160 (e.g. compute unit 160 of domain 'x' of PCIe fabric 151), management processor 110 may configure one or more PCIe switches 150 communicatively coupling the physical components of the domain to provide functionality for peer-to-peer data transfers using peer-to-peer relationship 180 … processor 120 may establish address ranges associated with peer-to-peer data transfers for one or more of the PCIe endpoint devices of the domain (e.g. during or following PCIe enumeration) …”; para. [0060] “… An enumeration process discovers the PCIe device as able to communicate with the host processor, and initializes the PCIe device in the host processor for later interaction over a corresponding PCIe interface. This enumeration process also includes the host processor assigning a base address register (BAR) and address range or space within a system memory space of the host processor. This BAR and address range is used for memory mapped access to the PCIe device, and does not typically correspond to physical memory or RAM coupled to the host processor …”);
wherein the device key information of the target transmitting device at least comprises a device identification (Cannata teaches PCIe enumeration including identifying PCIe devices via device identifiers; Examiner notes that the limitation “at least comprises A, B, and C” is considered to limit a conjunctive list of all items; para. [0060] “… An enumeration process discovers the PCIe device as able to communicate with the host processor, and initializes the PCIe device in the host processor for later interaction over a corresponding PCIe interface …”; para. [0076] “… Processing resources can have unique identifiers assigned thereto for use in identification by the management processor and for identification on the PCIe fabric …”), a type of matched receiving device (Cannata teaches establishing peer-to-peer relationship for the compatible PCIe devices, therefore the device type being identifiable to the peer devices; FIG. 1, FIG. 2; para. [0045] “… while establishing compute unit 160 (e.g. compute unit 160 of domain 'x' of PCIe fabric 151), management processor 110 may configure one or more PCIe switches 150 communicatively coupling the physical components of the domain to provide functionality for peer-to-peer data transfers using peer-to-peer relationship 180 … processor 120 may establish address ranges associated with peer-to-peer data transfers for one or more of the PCIe endpoint devices of the domain (e.g. during or following PCIe enumeration) …”), …;
Cannata teaches PCIe data transmission/routing comprises the target PCIe destination addresses (Cannata, FIG. 1, FIG. 7; para. [0051], para. [0098]). Cannata does not explicitly teach, but Harriman teaches the target data packet that is generated … and carries a target protocol and the target protocol is a protocol that is constructed, according to a preset protocol format, after the target transmitting device obtains an internal address of the target receiving device and comprises the internal address of the target receiving device (Harriman teaches generating PCIe TLP packets according to a PCIe protocol format, the protocol format comprising address fields identifying the destination device; Examiner notes that the applicant has claimed “constructing/construct a target protocol” in independent claims 1 and 20, also claimed “the target protocol is a protocol that is constructed” in independent claim 18. According to the instant Specification [0069], “the target protocol” includes the internal address of the target receiving device, and is a specially designed general-purpose communication protocol. Applying the broadest reasonable interpretation in light of the specification and taking into account the meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, “the target protocol” is considered as a set of rules to determine the addresses used for communication between the devices; FIG. 5, FIG. 6; para.[0056] “… Turning to FIG. 5, a simplified block diagram 500 is shown illustrating an example PCIe link 505 coupling a first device 510 to a second device 515 … The port ( e.g., 520, 525) may include transmit and receive circuitry as well as logic (e.g., implemented in hardware circuitry) to implement one or more interconnect protocols governing operation of a corresponding connection. For instance, ports 520, 525 may each include circuitry to implement a layered protocol stack of a PCIe-based protocol … The corresponding protocol circuitry (e.g., of ports 520, 525) may be utilized to generate packets (e.g., 530, 535) with packet headers according to each of the flit mode and non-flit mode …”; para. [0059] “… Turning to FIG. 6, a representation 600 is illustrated of an example flit-mode packet (e.g., TLP) format. For instance, the flit-mode packet format may include a header base 605 composed of a set of fields (e.g., 640, 645) that may be parsed by a receiver to determine an overall length of the packet, as well as other information, such as an identifier of the source of the packet, address information (e.g., for a destination of the packet), a transaction identifier, among other example information. The fields and format of the header base 605 may be based on and correspond to the type of packet …”).
Harriman and Cannata are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the generating packets according to a PCIe protocol format techniques of Harriman with the system of Cannata to facilitate the PCIe communication in point-to-point interconnects, switch-based technology, and packetized protocol (Harriman, para. [0023]).
Cannata-Harriman does not explicitly teach, but Moertl teaches transmits device key information of the target transmitting device to a host end for registration (Moertl teaches a PCIe device driver passing structured information (including device driver memory data structure address and parameters) to a host device driver services for registration; para. [0018] “… The device driver services are responsible for managing memory accessible by the PCIe endpoint, including the address translation and protection table (ATPT) and the address translation caches (ATCs) of the PCIe endpoint. …”; para. [0036] “… a method is provided for managing address translations. The method may comprise invoking, by a device driver, device driver services for initializing address translation entries in an address translation data structure of a root complex of the data processing system and passing, from the device driver to the device driver services, an address of a device driver memory data structure and registration modifiers …”).
Moertl and Cannata-Harriman are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the structured communication between a PCIe device and a host techniques of Moertl with the system of Cannata-Harriman to facilitate the PCIe device address translation (Moertl, para. [0016]).
Cannata-Harriman-Moertl does not explicitly teach, but Foong teaches a PCIe device information may include a quantity of addresses (Foong exemplifies that PCIe device 110 may include three BARs (i.e. Base Address Register) 111, 112, 113 in FIG. 1, therefore a PCIe device information may include multiple addresses; para. [0020] “… Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous ….”), an internal available device address (Foong teaches a BAR identifies an internal address (base address and size) for device communication; para. [0020] “… Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous ….”), …;
the internal available device address at least comprises a host mapping address, an internal address, an address length and an address type (Foong teaches that a PCIe device address being associated with a host assigned BAR address, a device address within an address range, an address range/length and an address type (e.g. memory vs I/O access addresses, 32-bit vs 64-bit); Examiner notes that the limitation “at least comprises A, B and C” is considered to limit a conjunctive list of all items; para. [0011] “… PCIe BAR mapping involves mapping a PCIe device into the memory-mapped address space (or other I/O address space) of the computer system. This mapping enables the computer system to address PCIe devices …”; para. [0020] “… In general, PCIe devices provide three address ranges. PCIe functionality allows memory-mapped I/O access to device control registers of up to six non-contiguously mapped memory regions, via six 32-bit BARs. At least one BAR is required for 32-bit operating systems, and two BARs are required for 64-bit operating systems. For 64-bit devices, these can be identified as Bar 0/1, Bar 2/3, and Bar 4/5.ABARis a pointer to a base address as well as identifying a length. Thus, a BAR identifies a starting address and a length. Across different BARs addressing can be discontinuous, but within a bar it is continuous …”).
Foong and Cannata-Harriman-Moertl are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe device addressing structures techniques of Foong with the system of Cannata-Harriman-Moertl to facilitate the PCIe device communication connections (Foong, para. [0002]).
Cannata-Harriman-Moertl-Foong does not explicitly teach, but Xu teaches a PCI device is associated with a callback function (Xu, para. [0014] “… a generic callback framework is provided which comprises (a) callback function definitions pertaining to device-specific state management that are defined by the hypervisor, and (b) implementations of those callback functions that are defined by PCI device vendors and included in each PCI device's host device driver …”).
Xu and Cannata-Harriman-Moertl-Foong are analogous art because they are both related to PCI communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe device specific callback function techniques of Xu with the system of Cannata-Harriman-Moertl-Foong to facilitate the PCI device state management (Xu, para. [0014]).
Cannata-Harriman-Moertl-Foong-Xu does not explicitly teach, but Khatri teaches the step of the target transmitting device obtains the internal address of the target receiving device comprises: receiving the internal address of the target receiving device and a corresponding address type, which are returned by the host end in a way of calling the callback function in the device key information of the target transmitting device (Khatri teaches the host management entity sending messages/packets to the PCIe device through event/interrupt handler techniques; Examiner notes that the event/interrupt handler technique is used here to teach calling the callback function; FIG. 1; para. [0041] “… The BIOS SMI handler can be configured to receive the notification from the management controller 170 indicating that the management controller has a packet bound for a PCIE I/O device associated with the processor 104. The BIOS SMI handler can be configured to generate an SMI in response to the notification. The BIOS SMI handler can be configured to retrieve the data packet from the management controller 170 and to send a payload of the data packet to the PCIE I/O device using, for example, the assigned PCIE capability identifier. …”)
Khatri and Cannata-Harriman-Moertl-Foong-Xu are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices communication techniques of Khatri with the system of Cannata-Harriman-Moertl-Foong-Xu to facilitate handling user specific information communications (Khatri, para. [0003]).
For Claim 20, the claim is substantially similar to claim 1 and therefore is rejected for the same reasoning set forth above. Additionally, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches a system for peer-to-peer communication between devices, comprising a target transmitting device and a target receiving device (Cannata, para. [0005] “… The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers …”).
For Claim 25, the claim is substantially similar to claim 1 and therefore is rejected for the same reasoning set forth above. Additionally, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches an electronic device, comprising a processor and a memory, wherein the memory is configured to store a computer program; and the computer program is loaded and executed by the processor to implement the method for the peer-to-peer communication between the devices according to claims 1 (Cannata, Claim 15 “… An apparatus comprising: one or more computer readable storage media; a processor operatively coupled with the one or more computer readable storage media; and program instructions stored on the one or more computer readable storage media, that when executed by the processor, direct the processor to …”).
For Claim 26, the claim is substantially similar to claim 1 and therefore is rejected for the same reasoning set forth above. Additionally, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches a non-transitory computer-readable storage medium, configured to store computer-executable instructions, wherein the computer-executable instructions, in response to being loaded and executed by a processor, implement the method for the peer-to- peer communication between the devices according to claims 1 (Cannata, Claim 15 “… An apparatus comprising: one or more computer readable storage media; a processor operatively coupled with the one or more computer readable storage media; and program instructions stored on the one or more computer readable storage media, that when executed by the processor, direct the processor to …”).
Claim Rejections - 35 USC § 103
Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), in view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 11281967 B1 (hereinafter Volpe), and in further view of US 20170243005 A1 (hereinafter Kinder).
For Claim 5, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches the method for the peer-to-peer communication between the devices according to claim 1.
Cannata-Harriman-Moertl-Foong-Xu-Khatri does not explicitly teach, but Volpe teaches wherein before the step of registering, by the host end, the target transmitting device, the method further comprises: determining whether a preset information transmitting condition is currently satisfied (Volpe teaches monitoring hardware/software state via registers and waiting for an event condition to occur; FIG. 2, FIG. 4; col. 6, ll. 19-27 “… Host interface 214 may enable communications between the host device and accelerator 202. For example, host interface 214 may be configured to transmit the memory descriptors including the memory addresses of the stored data (e.g., input data, weights, results of computations, etc.) between the host device and accelerator 202. Host interface 214 may include, for example, a peripheral component interconnect express (PCie) interface or any suitable interface for communicating with the host device. …”; col. 12, ll. 5-26 “… As noted above, processor 410 can execute the instructions at steps 412 and 414 without waiting for a reply or acknowledgment from either first DMA engine 446a or second DMA engine 446b. Processor 410 can thus proceed to step 416, at which processor 410 decodes and executes an 10 instruction to wait for an event. Waiting on an event can include, for example, monitoring a particular register or memory location for a write to the register or memory location …”), and
in response to the preset information transmitting condition being currently satisfied, transmitting the device key information of the target transmitting device to the host end (Volpe teaches transmitting a notification message out upon detecting an event condition; FIG. 4; col. 12, ll. 27-35 “… In the example of FIG. 4, processor 410 waits, at step 416, for a first event to occur. In this example, the first event indicator is set by second DMA engine 446b, and setting of the event indicator by second DMA engine 446b may occur some time after processor 410 reaches the instruction at step 416 …”; col. 12, ll. 56-67 “… At step 420, processor 410 may next decode and execute an instruction to initiate accelerator 402. This instruction can, for example, cause processor 410 to send a write transaction to accelerator 402, which sets an event indicator at accelerator 402 …”)
… after the host end has monitored the device key information by using a preset service driver program (Volpe teaches a driver or software module monitoring queue entries or registers for incoming notification/messages; FIG. 4; col. 10, ll. 59-67 “… Step 412 illustrates a first instruction, in which processor 410 increments a descriptor queue pointer for a first DMA engine 446a. Descriptors may have been added to the first DMA engine's descriptor queue in advance, for example by a driver program …”; col. 12, ll. 54-67 “… Events at accelerator 402 can operate in a similar fashion as events in processor 410, in that accelerator 402 may be able to watch particular registers or memory addresses for values to be written to these registers or memory locations. In the example of FIG. 4, accelerator 402 can thus, at step 442, see that an activation event has been triggered, which can cause accelerator 402 to begin executing accelerator code 404 …”).
Volpe and Cannata-Harriman-Moertl-Foong-Xu-Khatri are analogous art because they are both related to PCI communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the event based monitoring and processing of device information techniques of Volpe with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri to facilitate high performance of the computing system communications (Volpe, col. 1, ll. 59-67).
Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe does not explicitly teach, but Kinder teaches to cause the host end to execute the step of registering the target transmitting device after monitoring (Kinder teaches initializing/registering the resource/device once the resource/device information is detected and processed by BIOS/driver program; FIG. 1; para. [0026] “… BIOS/EFI module 140, disk controller 150, and I/O interface 170 are connected to chipset 110 via an I/O channel 112. An example of I/O channel 112 includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface … BIOS/EFI module 140 includes BIOS/EFI code operable to detect resources within information handling system 100, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module 140 includes code that operates to detect resources within information handling system 100, to provide drivers for the resources, to initialize the resources, and to access the resources …”).
Kinder and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe are analogous art because they are both related to PCI communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the initializing/registering resources/devices in an information handling system techniques of Kinder with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe to facilitate the event data collection and analysis in the information handling system (Kinder, para. [0009]).
For Claim 6, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder teaches the method for the peer-to-peer communication between the devices according to claim 5, wherein the preset service driver program is a program that is run on the host end in advance and performs device registration (Kinder teaches the BIOS/EFI module providing drivers for resource/device initialization/registration; FIG. 1; para. [0026] “… BIOS/EFI module 140 includes BIOS/EFI code operable to detect resources within information handling system 100, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module 140 includes code that operates to detect resources within information handling system 100, to provide drivers for the resources, to initialize the resources, and to access the resources …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the initializing/registering resources/devices in an information handling system techniques of Kinder with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe to facilitate the event data collection and analysis in the information handling system (Kinder, para. [0009]).
For Claim 7, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder teaches the method for the peer-to-peer communication between the devices according to claim 5, wherein the step of transmitting the device key information of the target transmitting device to the host end to cause the host end to execute the step of registering the target transmitting device after the host end has monitored the device key information by using the preset service driver program comprises:
transmitting the device key information of the target transmitting device to the host end in a way of calling a pre-generated register function interface to cause the host end to monitor a calling state of the pre-generated register function interface by using the preset service driver program (Xu teaches that PCI device drivers interact with host systems through a predefined registration function interfaces, including callback registration mechanisms in which a driver invokes a predefined function to register device-specific behavior with the host system; FIG. 3; para. [0027] “… generic callback framework 304 (which comprises callback function definitions defined by hypervisor 102 and corresponding callback function implementations implemented by device vendors within respective host device drivers) can provide hypervisor 102 with a common interface for handling device-specific state migration in a generic fashion. For example, when the live migration of VM 104 reaches the switch-over phase, hypervisor 102 can leverage framework 304 and invoke the callback functions implemented by the vendor of physical PCI device 106 in order to properly quiesce, save, and restore the device-specific state of device 106. By offloading the implementation of device-specific state management to device vendors, generic callback framework 104 avoids the need for hypervisor 102 to implement custom state handling logic for every possible passthrough PCI device …”; para. [0043] “… hypervisor 102 can invoke the Save() callback to get a blob of the device's state (which can subsequently be copied to the destination host system), and can invoke the Restore( ) callback to restore the state of a device that was saved on another host system and is being migrated to the current host system …”), and …
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe device specific callback function techniques of Xu with the system of Cannata-Harriman-Moertl-Foong to facilitate the PCI device state management (Xu, para. [0014]).
Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder also teaches in response to it being monitored that the pre-generated register function interface is called, determining that the device key information has been monitored (Volpe teaches a driver or software module monitoring queue entries or registers for incoming notification/messages; FIG. 4; col. 10, ll. 59-67 “… Step 412 illustrates a first instruction, in which processor 410 increments a descriptor queue pointer for a first DMA engine 446a. Descriptors may have been added to the first DMA engine's descriptor queue in advance, for example by a driver program …”; col. 12, ll. 54-67 “… Events at accelerator 402 can operate in a similar fashion as events in processor 410, in that accelerator 402 may be able to watch particular registers or memory addresses for values to be written to these registers or memory locations. In the example of FIG. 4, accelerator 402 can thus, at step 442, see that an activation event has been triggered, which can cause accelerator 402 to begin executing accelerator code 404 …”), and …
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the event based monitoring and processing of device information techniques of Volpe with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri to facilitate high performance of the computing system communications (Volpe, col. 1, ll. 59-67).
Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder further teaches executing the step of registering the target transmitting device (Kinder teaches initializing/registering the resource/device once the resource/device information is detected and processed by BIOS/driver program; FIG. 1; para. [0026] “… BIOS/EFI module 140, disk controller 150, and I/O interface 170 are connected to chipset 110 via an I/O channel 112. An example of I/O channel 112 includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface … BIOS/EFI module 140 includes BIOS/EFI code operable to detect resources within information handling system 100, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module 140 includes code that operates to detect resources within information handling system 100, to provide drivers for the resources, to initialize the resources, and to access the resources …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the initializing/registering resources/devices in an information handling system techniques of Kinder with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe to facilitate the event data collection and analysis in the information handling system (Kinder, para. [0009]).
Claim Rejections - 35 USC § 103
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), in view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 11281967 B1 (hereinafter Volpe), in view of US 20170243005 A1 (hereinafter Kinder), in further view of US 20220283928 (hereinafter Liu).
For Claim 8, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder teaches the method for the peer-to-peer communication between the devices according to claim 7. Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder does not explicitly teach, but Liu teaches wherein the pre-generated register function interface is exported by the preset service driver program through an execution symbol export library function (Liu teaches that exported functions are made available via symbol tables used during execution; FIG. 2; para. [0039] “… With continued reference to FIG. 2, in an embodiment, the Kwasm engine 103 may further include a symbol table generation module 205. The symbol table generation module 205 is configured to generate export function symbol tables on the basis of system symbol tables and kernel header files. The export function symbol tables are correspondence tables between interface functions exported from the kernel and actual kernel addresses when the system is running, and thus through the export function symbol tables, a kernel export function (i.e., an interface function defined in kernel codes) to be called can be quickly found in the process of executing the object files …”).
Liu and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder are analogous art because they are both related to computing systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the execution symbol export library function techniques of Liu with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder to facilitate an easy-to-use kernel debugging system (Liu, para. [0004]).
Claim Rejections - 35 USC § 103
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), in view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 11281967 B1 (hereinafter Volpe), in view of US 20170243005 A1 (hereinafter Kinder), in view of US 20220283928 (hereinafter Liu), and in further view of Bissyande et al. (Diagnosys: automatic generation of a debugging interface to the linux kernel. In Proceedings of the 27th IEEE/ACM International Conference on Automated Software Engineering (pp. 60-69), published 09/2012; hereinafter Bssyande).
For Claim 9, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder-Liu teaches the method for the peer-to-peer communication between the devices according to claim 8. Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder-Liu does not explicitly teach, but Bissyande teaches wherein the execution symbol export library function is an EXPORTSYMBOLGPL function (Bissyande teaches an exported function is EXPORT_SYMBOL_GPL – section 4.1, page 64).
Bissyande and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder-Liu are analogous art because they are both related to computing systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the EXPORT_SYMBOL_GPL function techniques of Bissyande with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Volpe-Kinder-Liu to facilitate the analysis of the kernel exported functions (Bissyande, section 4.1, page 64).
Claim Rejections - 35 USC § 103
Claims 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), and in further view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), and in further view of US 20150261701 A1 (hereinafter Craddock).
For Claim 11, Cannata-Harriman-Moertl-Foong-Xu-Khatri teaches the method for the peer-to-peer communication between the devices according to claim 10, wherein after the step of transmitting the device key information of the target transmitting device to the host end to cause the host end to locally store the device key information transmitted by the target transmitting device, the method further comprises:
transmitting a device matching instruction to the host end to cause the host end to (Khatri teaches a PCIe device sending messages/packets to host management entity, the host management entity performing logic based on the messages/packets; FIG. 1; para. [0042] “… the BIOS 140 can be configured to detect an event at the secondary processor 104. For instance, the disk controller 150 or another PCIE I/O device can assert the event, such as any interrupt, at the secondary processor 104 after uploading a VDM packet or another data packet from a data source. In response to detecting the event, the BIOS 140 can be configured to query a buffer, a control register, or both, at the PCIE I/O device to determine the presence of the data packet. After determining the presence of the data packet at the PCIE I/O device, the BIOS SMI handler can be configured to generate an SMI. Further, the BIOS SMI handler can be configured to retrieve the data packet from the PCIE I/O device. The BIOS SMI handler can be configured to send a payload of the data packet to the management controller 170 …”; para. [0043] “… In a particular embodiment, the management controller 170 can be configured to send the data packet to another PCIe I/O device that is associated with the primary processor 102. In another particular embodiment, the management controller 170 can send the data packet to another PCIe I/O device that is associated with another secondary processor …”): …
return the internal address of the target receiving device (Khatri teaches the host management entity sending messages/packets to the PCIe device; Examiner notes that the later Jain reference teaches resolving the matched PCIe device information which could be included in the messages/packets in Khatri; FIG. 1; para. [0041] “… The BIOS SMI handler can be configured to receive the notification from the management controller 170 indicating that the management controller has a packet bound for a PCIE I/O device associated with the processor 104. The BIOS SMI handler can be configured to generate an SMI in response to the notification. The BIOS SMI handler can be configured to retrieve the data packet from the management controller 170 and to send a payload of the data packet to the PCIE I/O device using, for example, the assigned PCIE capability identifier. …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices communication techniques of Khatri with the system of Cannata-Harriman-Moertl-Foong-Xu to facilitate handling user specific information communications (Khatri, para. [0003]).
Cannata-Harriman-Moertl-Foong-Xu-Khatri does not explicitly teach, but Craddock teaches match, from registered devices according to the device matching instruction, the target receiving device having a device type consistent with the type of matched receiving device in the device key information transmitted by the target transmitting device (Craddock teaches translating the requested device addresses using a device table in the host memory; FIG. 1; para. [0014] “… To access the system memory 104, one of the CPUs 102 issues a read or write request that includes an address used to access the system memory 104. The address included in the request is typically not directly usable to access the system memory 104, and therefore, it is translated to an address that is directly usable in accessing the system memory 104. The address is translated via an address translation mechanism (ATM) 108, as shown in FIG. 1 …”; para. [0021] “… The DTE 210 may be located in one or both of a device table 211 located in the system memory 104 and a device table cache 2110 located in the host bridge 112 …”),
read the internal address in locally stored device key information of the target receiving device (Craddock, FIG. 1; para. [0027] “… The manage instruction serves as an indicator that the device table entry (DTE) cache 2110 of the host bridge 112 is to be accessed for any DMA read/write operation initiated by the adapter 110 or the PCI function and is to be managed in the host bridge 112 for coherency for DTE configuration changes …”), and …, wherein the target receiving device has been registered at the host end (Craddock teaches the PCI devices being registered ; FIG. 1; para. [0021] “… An operating system running on the computing environment 100 may be configured to assign the DMA address space 200 to one of the PCI functions of the adapters 110. This assignment may be performed via a registration process, which causes an initialization (via, e.g., trusted software) of a device table entry (DTE) 210 for the PCI function of a corresponding one of the adapters 110. …”).
Craddock and Cannata-Harriman-Moertl-Foong-Xu-Khatri are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices address translation techniques of Craddock with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri to facilitate processor I/O interfacing within a computing environment (Craddock, para. [0001]).
For Claim 12, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock teaches the method for the peer-to-peer communication between the devices according to claim 11, wherein the host end further transmits the device key information of the target transmitting device to the target receiving device in the way of calling the callback function in the device key information of the target transmitting device (Khatri teaches the host management entity also sending the messages/packets to other PCIe devices; FIG. 1; para. [0043] “… In a particular embodiment, the management controller 170 can be configured to send the data packet to another PCIe I/O device that is associated with the primary processor 102. In another particular embodiment, the management controller 170 can send the data packet to another PCIe I/O device that is associated with another secondary processor, as described herein …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the PCIe devices communication techniques of Khatri with the system of Cannata-Harriman-Moertl-Foong-Xu to facilitate handling user specific information communications (Khatri, para. [0003]).
Claim Rejections - 35 USC § 103
Claims 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), and in further view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 20150261701 A1 (hereinafter Craddock), and in further view of US 20110161703 A1 (hereinafter Ajanovic).
For Claim 13, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock teaches the method for the peer-to-peer communication between the devices according to claim 12. Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock does not explicitly teach, but Ajanovic teaches wherein the data processing comprises one of reading data in the internal address or writing data into the internal address (Ajanovic, para. [0041] “… four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location …”);
a type of the data processing depends on a type of the target data packet received by the target receiving device (Ajanovic teaches the type of data processing based on the type of received packet; FIG. 11; para. [0081] “… In flow 1115, a type of the first packet is determined. In a first embodiment, the first packet is a read/write request message including an ACH. The read/write request message may also include a prefetch hint. In another embodiment, the packet is a prefetch message including a prefetch hint …”; para. [0082] “… If the packet includes an ACH and no prefetch hint, then in flow 1120 the first element is fetched, if the ACH indicates the first element is to be fetched …”); and
the type of the target data packet depends on the address type of the internal address of the target receiving device (Ajanovic, para. [0081] “… A packet type may be determined by an opcode field, a message code field, or other field to specify a packet type. In addition, an ACH field and/or a prefetch hint field may be read to determine the packet type …”).
Ajanovic and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the data processing techniques of Ajanovic with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock to facilitate the PCIe point-to-point interconnection (Ajanovic, para. [0031]).
Claim Rejections - 35 USC § 103
Claims 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), and in further view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 20150261701 A1 (hereinafter Craddock), in view of US 20110161703 A1 (hereinafter Ajanovic), and in further view of US 20160302197 A1 (hereinafter Xie).
For Claim 14, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock-Ajanovic teaches the method for the peer-to-peer communication between the devices according to claim 13. Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock-Ajanovic does not explicitly teach, but Xie teaches wherein after the step of transmitting the target data packet to the target receiving device to cause the target receiving device to perform data processing on the internal address, the method further comprises:
receiving a confirm data packet returned by the target receiving device, wherein the confirm data packet is generated and returned by the target receiving device according to the device key information of the target transmitting device (Xie teaches the packet receiving device generating and sending an ACK packet according to the received packet (e.g. the packet sending device address); FIG. 1; para. [0025] “… the communication device 102 can be configured to generate an ACK packet in response to receipt of a data packet(s). The communication device 102 can be further configured to add the ACK packet to a transmit queue that can be maintained by the communication device 102 for packets to be sent to the network 104 …”).
Xie and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock-Ajanovic are analogous art because they are both related to communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the acknowledging the received packet techniques of Xie with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock-Ajanovic to facilitate the network communication between devices (Xie, para. [0003]).
Claim Rejections - 35 USC § 103
Claims 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200250117 A1 (hereinafter Cannata), in view of US 20200226091 A1 (hereinafter Harriman), in view of US 20080091915 A (hereinafter Moertl), in view of US 20140006659 A1 (hereinafter Foong), and in further view of US 20190146853 A1 (hereinafter Xu), in view of US 20130124768 A1 (hereinafter Khatri), in view of US 20150261701 A1 (hereinafter Craddock), and in further view of US 20200301863 A1 (hereinafter Long).
For Claim 15, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock teaches the method for the peer-to-peer communication between the devices according to claim 12. Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock does not explicitly teach, but Long teaches wherein after the step of obtaining the internal address of the target receiving device, the method further comprises:
receiving a host mapping address in the device key information of the target receiving device, … to cause the target data packet to further carry the host mapping address in the device key information of the target receiving device (Long teaches the host assigning and maintaining device-specific address mappings (e.g. BARs, translated address ranges), the mapping information being used for communication and routing between devices; FIG. 1; para. [0045] “… Management processor 110 may configure the host processor to generate PCIe data traffic using expanded addressing (e.g. using a management driver operating on the host processor) and the PCIe switches to perform monitoring of the PCIe data traffic to trap and route the PCIe data traffic based on expanded addresses. For example, host processor 120 may be configured to assign one or more bits of another field of the PCIe data traffic to select one of multiple tables to store routing information for each PCIe endpoint devices of the domain (e.g. during or following PCIe enumeration and discovery) …”; para. [0062] “… An enumeration process discovers the PCIe devices able to communicate with the host processor, and initializes the PCIe devices in the host processor for later interaction over a corresponding PCIe interface. This enumeration process also includes the host processor assigning a base address register (BAR) and address range or space within a system memory space of the host processor. This BAR and address range is used for memory mapped access to the PCIe device, and does not typically correspond to physical memory or RAM coupled to the host processor. When applications desire to interface with the PCIe device, such as GPU, these applications typically interact with an API or interface of the device driver. The application can issue commands through the API for handling by the PCIe device, such as reads, writes, data transfers, data processing commands, status information requests, configuration changes, or other commands. When the expanded addressing functionality is enabled, the enumeration process may further include assigning values for one or more expanded address bits. …”).
Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock further teaches an address information which is returned by the host end in the way of calling the callback function in the device key information of the target transmitting device (Khatri teaches the host management entity sending messages/packets to the PCIe device through event/interrupt handler techniques; Examiner notes that the event/interrupt handler technique is used here to teach calling the callback function; FIG. 1; para. [0041] “… The BIOS SMI handler can be configured to receive the notification from the management controller 170 indicating that the management controller has a packet bound for a PCIE I/O device associated with the processor 104. The BIOS SMI handler can be configured to generate an SMI in response to the notification. The BIOS SMI handler can be configured to retrieve the data packet from the management controller 170 and to send a payload of the data packet to the PCIE I/O device using, for example, the assigned PCIE capability identifier. …”).
Long and Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock are analogous art because they are both related to PCIe communication systems.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the host maintained address mapping techniques of Long with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock to facilitate host managed expanded address to support a communication arrangement for PCIe traffic (Long, para. [0005]).
For Claim 16, Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock-Long teaches the method for the peer-to-peer communication between the devices according to claim 15, wherein the step of transmitting the target data packet to the target receiving device comprises:
transmitting the target data packet to the target receiving device to cause the target receiving device to: analyze the target data packet to obtain the host mapping address in the device key information of the target receiving device (Long teaches the host management entity managing mapping information to determine a destination address; FIG. 1, FIG. 4; para. [0084] “… Management processor 110 then can use the host domain addresses and expanded addressing bits to populate (406) address traps and look up tables to establish the expanded addressing functionality. For example, management processor 110 may populate control circuitry or control elements within various PCIe switches of the PCIe fabric to establish the address traps and may establish and populate look-up tables (LUTs). A LUT may be established for each value of the expanded addressing bits and then populated with a record for each PCIe device assigned the associated expanded addressing bit. These LUTs indicate relationships between the host domain addresses (for each destination PCIe device assigned the corresponding expanded addressing bit value) and routing information to reach the corresponding destination PCIe devices through the PCIe fabric …”),
determine whether the host mapping address is a host mapping address for peer-to-peer communication, and in response to the host mapping address being the host mapping address for peer-to-peer communication, execute the step of performing data processing on the internal address (Long teaches examining the packet address to determine if the data transfers to another device (e.g. PCIe link 656 to FPGA devices 667-668 and then to destination device in FIG. 6, referring to peer-to-peer traffic) or to host management entity (e.g. PCIe link 655 to the management CPU 610 in FIG. 6); para. [0094] “… The address traps 631 comprise an address monitoring portion and, depending on the implementation, a redirection portion. The address monitoring portion monitors PCIe frames or other PCIe traffic to determine if data transfers from a compute unit utilizing expanded addressing functionality are encountered. If data transfers from a compute unit utilizing expanded addressing functionality are encountered, then the address traps forwards the PCI traffic to a FPGA device. The FPGA devices 667-668 may include redirection portions of the address trap. For example, the FPGA devices may use the expanded address bits to select a look up table 632 associated with the value of the expanded addressing bits of the forwarded data transfer. In some implementations, the look up tables of the address traps may comprise ‘content addressable memories’ (CAMs). The FPGA devices may then use the host domain address to determine routing information stored in the selected look up table for the destination device. …”).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to use the host maintained address mapping techniques of Long with the system of Cannata-Harriman-Moertl-Foong-Xu-Khatri-Craddock to facilitate host managed expanded address to support a communication arrangement for PCIe traffic (Long, para. [0005]).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed below, thank you:
i. US 2014/0281106 A1 (Saghi) teaches that a system includes a PCie controller coupled to a device through a nontransparent PCie bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCie driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCie controller to the host system as well as from the host system to the PCie controller. The PCie controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCie controller generates I/O commands that contain routing information for the device ( e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCie controller (Abstract).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Z.D./Examiner, Art Unit 2444
/SCOTT B CHRISTENSEN/Primary Examiner, Art Unit 2444
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