DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made wherein this application is claimed continuation of the PCT Application PCT/EP2023/062338, being filed on May 10, 2023.
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application filed on December 19, 2024.
Information Disclosure Statement
The information disclosure statements filed December 16,2024 have been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered.
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 18, the limitation “the control terminal contact pad extends into a region of the underside of the first circuit carrier which region corresponds to the first load terminal surface.” is indefinite for failing to particularly point out and distinctly claim the subject matter
A term “correspond” is also unclear. It is not clear how it corresponds such as on, in, toward, away to the first load terminal surface.
Rejection of claim 19, the limitation “wherein the control terminal contact pad includes a section which extends into the region of the underside of the first circuit carrier corresponding to the first load terminal surface and has a region that cannot be contacted.” is indefinite for failing to particularly point out and distinctly claim the subject matter.
It is not clear that the control terminal contact pad includes a section which extends into the region of the underside of the first circuit carrier corresponding to the first load terminal surface and has a region that cannot be contacted to what. Please clarify.
Alos, term “cannot be contacted” is showing possibility which is improper and has negative limitation. term “correspond” is also unclear. It is not clear how it corresponds such as on, in, toward, away to the first load terminal surface.
A proper way to mention the limitation is that the control terminal contact pad includes a section exposed from the control terminal surface and extends into the region of the underside of the first circuit carrier above the first load terminal surface (it appears that a region is insulating layer region between two pads 18 and 19 and is already not contacted the first terminal surface).
Appropriate correction is required.
Rejection of claim 20, the limitation “wherein a region of the underside of the first circuit carrier is located between the control terminal contact pad and the first load terminal contact pad and has a region which cannot be contacted” is indefinite for failing to particularly point out and distinctly claim the subject matter.
It is not clear that a region of the underside of the first circuit carrier, located between the control terminal contact pad and the first load terminal contact pad, has a region which is not contacted to what. Please clarify.
Alos, term “cannot be contacted” is showing possibility which is improper and negative language. A term “correspond” is also unclear. It is not clear how it corresponds such as on, in, toward, away to the first load terminal surface.
A proper way to mention the limitation that a region of the underside of the first circuit carrier is located between the control terminal contact pad and the first load terminal contact pad and is electrically isolated disposed above the first terminal surface (it appears that a region is insulating layer region between two pads 18 and 19 and is already not contacted the first terminal surface ).
Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-22 are rejected under 35 U.S.C. 103 as being unpatentable over by Robert et al. (US20120243192, herein referred to as Robert), Nishihara et al. (US20230411274, herein referred to as Nishihara), Murayama et al. (US20220028774, herein referred to as Murayama) , and Iwane et al. (US20060081999, herein referred to as Iwane).
Rejection of claim 13, Robert (see figure 6, and specification of Robert) discloses a circuit assembly, comprising:
an at least two-layer first circuit carrier (top metalized substrate assembly 110 in Robert and see figures 6, and paragraphs 0033-0038);
a second circuit carrier (bottom metalized substrate assembly 120 in Robert and see figures 6, and paragraphs 0033-0038);
a semiconductor component arranged between the first circuit carrier and the second circuit carrier (second power electronics device 132 is positioned between the top metalized substrate assembly 110 and the bottom metalized substrate assembly 120 wherein the power electronics devices 132 is power semiconductor devices, see specification) and
the semiconductor component comprises a first load terminal and a second load terminal (see top and bottom electrical connection of 132 in paragraphs 0025-0038 and figure 6),
with the first load terminal including a first load terminal surface which faces the first circuit carrier (see a top surface region of 132, paragraphs 0025-0038 and figure 6), and
with the second load terminal including a second load terminal surface which faces the second circuit carrier and is sized larger than the first load terminal surface (see bottom surface region of 132, paragraphs 0025-0038 and figure 6),
said first load terminal surface being electrically connected to a first load terminal contact pad ( a third conductive region 116) arranged on an underside of the first circuit carrier in facing relation to the semiconductor component (see paragraphs 0025-0038 and figure 6),
wherein the first circuit carrier has a first through-contact (vias 115) which connects the first load terminal contact pad (116) to a first conductor path which runs inside the first circuit carrier or on a top side of the first circuit carrier (a first conductive region 113) remote from the semiconductor component (see figure 6);
a first electrically conductive layer (a first bottom conductive layer 124) formed on a top side of the second circuit carrier in facing relation to the semiconductor component and electrically connected to the second load terminal surface (see specification and figure 6);
a second electrically conductive layer (a second bottom conductive layer 125) formed on an underside of the second circuit carrier, which underside is remote from the semiconductor component; and
an electrically insulating layer (a bottom insulating dielectric substrate 122) arranged between the first electrically conductive layer and the second electrically conductive layer,
wherein the first circuit carrier has an underside with a second load terminal contact pad (a fourth conductive region 118) which is electrically connected to the first electrically conductive layer (124) of the second circuit carrier, and
Robert fails to disclose the second load terminal including a second load terminal surface is sized larger than the first load terminal surface.
wherein the first load terminal contact pad is arranged completely within a region of the underside of the first circuit carrier which region corresponds to a region of the semiconductor component surrounded by the edging structure.
a first load terminal surface around which an electrically insulating edging structure is arranged.
Nishihara or Murayama discloses the second load terminal including a second load terminal surface is sized larger than the first load terminal surface (see terminal surface of 30 at bottom is larger than terminal surface on top; and all connection regions of first circuit board arranged on device 30 within the boundary range of device 30, see figure 3 or 4 of Nishihara; or see terminal surface of 30 at bottom of 30 is larger than terminal surface at top of 30; and all connection regions of first circuit board arranged on device 30 within the boundary range of device 30, see figure 3 or 4 of Nishihara; or see similarly in figures 1a-1b of Murayama).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit assembly of Roberts to have structural arrangement as taught by Nishihara or Murayama to reduce the manufacturing cost of the circuit assembly with improved overall electrical and heat performance of the circuit assembly.
Murayama or Iwane discloses a first load terminal surface around which an electrically insulating edging structure is arranged (see insulating edging structure 42 around terminal surface of 30, see figures 1a-1b of Murayama; or see 13 of device 11 in figure 5 of Iwane ) .
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit assembly of Roberts to have structural arrangement as taught by Murayama or Iwane so that a portion except pads on that surface of the semiconductor element on which the pads are provided covered with insulating layer to protects the semiconductor element, whereby, the reliable semiconductor device is achieved.
Rejection of claim 14, Robert in view of Nishihara Murayama, and Iwane discloses the circuit assembly of claim 13, wherein the first through-contact runs parallel to a first straight line which forms a non-vanishing angle with a normal vector of the underside of the first circuit carrier (see 115 in Robert).
Rejection of claim 15, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 13, wherein the first conductor path runs inside the first circuit carrier and is connected by a further through-contact to another conductor path which runs on the top side of the first circuit carrier (this limitation is optional or do not apply and do not get patentable weight when a first conductor path which runs conductor path which runs on the top side of the first circuit carrier, see specification).
Rejection of claim 16, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 13, wherein the semiconductor component comprises a control terminal with a control terminal surface which faces the first circuit carrier (see connection region of semiconductor device in Robert) and is arranged inside the region of the semiconductor component surrounded by the insulating edging structure (see Robert in view of Nishihara, Murayama, and Iwane disclose wherein all connection regions within the Semiconductors boundary region in Nishihara or Murayama; see insulating layer in Murayama or Iwane), and wherein the first circuit carrier comprises on the underside a control terminal contact pad (119) which is electrically connected to the control terminal surface (see connection between semiconductor device and control terminal contact pad in Robert in view of Nishihara, Murayama, and Iwane), said first circuit carrier having a second through-contact (111 in Roberts) which connects the control terminal contact pad to a second conductor path which runs inside the first circuit carrier or on the top side of the first circuit carrier (see conductor on the top side of the first circuit carrier connected to via conductor 111 in figure 6 of Robert) .
Rejection of claim 17, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, wherein the control terminal contact pad (119 in Robert in view of Nishihara, Murayama, and Iwane) is arranged completely within the region of the underside of the first circuit carrier.
Rejection of claim 18, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, wherein the control terminal contact pad extends into a region of the underside of the first circuit carrier which region corresponds to the first load terminal surface (a region of 116 under extends into a region of the underside of the first circuit carrier away to (corresponds to defines as away to, see first USC 112 about term corresponds) the first terminal side surface in Roberts also, see also other references).
Rejection of claim 19, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, wherein the control terminal contact pad includes a section which extends into the region of the underside of the first circuit carrier corresponding to the first load terminal surface and has a region that cannot be contacted (a region of 116 under extends into a region of the underside of the first circuit carrier away to (corresponds to defines as away from, see first USC 112 about term corresponds) the first terminal side surface, therefore, is not contacted to the first terminal side surface in Roberts also, see other references also support this limitation).
Rejection of claim 20, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, wherein a region of the underside of the first circuit carrier is located between the control terminal contact pad and the first load terminal contact pad and has a region which cannot be contacted (a region of 112 between 116 and 119 has a region which is away to terminal surface of semiconductor).
Rejection of claim 21, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, wherein the second through-contact runs parallel to the first through-contact (see via conductors 115 and 111 in Robert).
Rejection of claim 22, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 13, wherein the first circuit carrier includes a third through-contact, which connects the second load terminal contact pad to a third conductor path which runs inside the first circuit carrier or on the top side of the first circuit carrier (see via conductors 117 connects pad 118 to the conductor path 114 on the top side of the first circuit carrier 110 in Robert).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over by Robert in view of Nishihara, Murayama, and Iwane and further in view of Peng et al. (US20210235581, herein referred to as Peng) or Buvid et al. (US9875958, herein referred to as Buvid).
Rejection of claim 23, Robert in view of Nishihara, Murayama, and Iwane disclose the circuit assembly of claim 16, but fail to disclose wherein the third through-contact runs parallel to a second straight line which forms a non-vanishing angle with a normal vector of the underside of the first circuit carrier, so that a spacing of the third through-contact from the first through-contact in a plane parallel to the underside of the first circuit carrier increases with a spacing of the plane from the underside of the first circuit carrier.
Peng or Buvid disclose wherein the third through-contact runs parallel to a second straight line which forms a non-vanishing angle with a normal vector of the underside of the first circuit carrier, so that a spacing of the third through-contact from the first through-contact in a plane parallel to the underside of the first circuit carrier increases with a spacing of the plane from the underside of the first circuit carrier (see two vias in upside figure 2 of Peng; or upside figures 8-14 of having a straight via and angled via Buvid).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit assembly of Robert in view of Nishihara, Murayama, and Iwane to have structural arrangement as taught by Peng or Buvid so that board (carrier) is used to electrically connect and arrange electronic components with different connection pad spans at both ends as well as provide enough gaps between electronic components to properly organized at both ends.
Pertinent Prior Arts
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various circuit board assemblies.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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