DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Regarding Claim 20
Claim 20 recites:
A computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising…
Claim 20 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “a computer program” encompasses software per se. (MPEP 2106.03 I, “Products that do not have a physical or tangible form, such as information (often referred to as "data per se") or a computer program per se (often referred to as "software per se") when claimed as a product without any structural recitations” are not directed to any of the statutory categories)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 16, 19-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bannow (US 11042143 B2).
Regarding Claim 1:
Bannow teaches:
An apparatus comprising: processing circuitry to execute instructions; (Bannow, Col. 2, line 4-6, The device for computing data models, in particular comprising the possibility to detect errors occurring during the computation, has at least two processing units)
wherein the processing circuitry comprises: calculation circuitry responsive to one or more instructions requiring a calculation to be performed to compute the result of the calculation; (Bannow, Col. 6, line 50-53, Control unit 106 may be designed to execute the computation of at least one main data model essentially on a first processing unit, for example 102)
approximation circuitry responsive to said one or more instructions to calculate an approximate result of the calculation independently of the calculation circuitry; (Bannow, Col. 6, line 52-55, and the computation of at least one associated approximation data model on the other processing unit, essentially on the second processing unit, for example 104.)
and integrity checking circuitry (Bannow, Fig. 1, comparator unit 108) configured to perform an integrity check by: comparing the result of the calculation performed by the calculation circuitry and the approximate result of the calculation performed by the approximation circuity; (Bannow, Col. 6, line 14-17, One of the microprocessors may comprise a comparator unit 108, which is designed to compare the first result with the second result, and to determine the information about the deviation.)
and detecting an error in the processing circuitry in response to determining that a difference between the result of the calculation and the approximate result of the calculation is greater than a deviation threshold. (Bannow, Col. 6, line 17-18, The comparator unit 108 detects the error as a function of the information about the deviation. Col. 5, line 64-67, the comparator unit being designed to detect an error, as a function of the information about the deviation, if the deviation exceeds a maximally admissible deviation.)
Regarding Claim 4:
Bannow teaches:
The apparatus according to claim 1, wherein: the calculation operates on one or more operands; (Bannow, Col. 5, line 13-15, The input data of the system required for computing the main data model and the associated approximation data model as well as the model data may be stored in separate or in the same memory)
and the approximation circuitry is configured to obtain the one or more operands from one or more predetermined registers. (Bannow, Col. 5, line 16-17, The memory may be designed for example as a register or as RAM (random access memory). )
Regarding Claim 16:
Bannow teaches:
The apparatus according to claim 1,wherein: the integrity checking circuitry is configured to obtain the deviation threshold from a system register. (Bannow, Col. 5, line 60-67, The comparator unit is designed to compare a first result of a first computation of the main data model with a second result of a second computation of the approximation data model in order to determine information about a deviation between the first result and the second result, the comparator unit being designed to detect an error, as a function of the information about the deviation, if the deviation exceeds a maximally admissible deviation. Col. 7, line 45-48, The at least two processing units may be designed to compute, as a function of the state of the system, the maximally admissible deviation from a deviation data model. Col. 7, line 50-51, The non-volatile memory 128 in this case comprises the data of the deviation data model. Col. 5, line 16-17, The memory may be designed for example as a register or as RAM (random access memory))
Regarding Claim 19:
The method of claim 19 performs the same method steps as the apparatus of claim 1, and claim 19 is therefore rejected using the same rationale set forth above in the rejection of claim 1
Regarding Claim 20:
The computer program of claim 20 performs the same method steps as the apparatus of claim 1, and claim 20 is therefore rejected using the same rationale set forth above in the rejection of claim 1
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bannow (US 11042143 B2) in view of MORRISON (US 20120042153 A1).
Regarding Claim 14:
Bannow doesn’t explicitly teach:
The apparatus according to claim 1,wherein: the calculation circuitry is an arithmetic logic unit (ALU) or part of an ALU.
However, MORRISON teaches:
The apparatus according to claim 1,wherein: the calculation circuitry is an arithmetic logic unit (ALU) or part of an ALU. ( MORRISON, [0017] Execution units 38 may include, for example, arithmetic logic units (ALUs))
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Bannow with ALU(s) as taught by MORRISON, So Execution units 38 can perform arithmetic, logical, shifting, or other operations using data stored in register file 40 as needed for executing the instructions received from instruction fetch unit 20. (MORRISON, [0017])
Regarding Claim 15:
Bannow doesn’t explicitly teach:
The apparatus according to any of claim 1, wherein: the calculation circuitry is a floating point unit (FPU) or part of an FPU.
However, MORRISON teaches:
The apparatus according to any of claim 1, wherein: the calculation circuitry is a floating point unit (FPU) or part of an FPU. (MORRISON, [0017] Execution units 38 may include, for example, arithmetic logic units (ALUs), floating point units, etc.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Bannow with floating point units as taught by MORRISON, So Execution units 38 can perform arithmetic, logical, shifting, or other operations using data stored in register file 40 as needed for executing the instructions received from instruction fetch unit 20. (MORRISON, [0017])
Allowable Subject Matter
Claims 2-3, 5-13, 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bannow (US 11042143 B2): A device for computing data models, in particular comprising the possibility to detect errors occurring during the computation, has at least two processing units, at least one of the at least two processing units being designed to compute a main data model as a function of at least one state of a system, at least one other of the at least two processing units being designed to compute, as a function of this at least one state of the system, an approximation data model associated with the main data model, the main data model comprising at least one property of the system as a first data model, the approximation data model comprising at least the same property of the system approximately as a second data model, a comparator unit being designed to compare a first result of a first computation of the main data model with a second result of a second computation of the approximation data model associated with the main data model, in order to determine information about a deviation between the first result and the second result, the comparator unit being designed to detect an error as a function of the information about the deviation if the deviation exceeds a maximum admissible deviation.
Nara (US 11408747 B2): An in-vehicle apparatus mounted in a vehicle includes: a map information storage unit that stores map information; a communication control unit that acquires traffic information; a travel history database in which a travel history of the vehicle with respect to each road is recorded; a route estimation unit that estimates a travel route of the vehicle by using the map information and the travel history database; a traveling time calculation unit that calculates actual traveling time of the vehicle with respect to the travel route and calculates predicted traveling time required when traveling the travel route estimated by the route estimation unit by using the traffic information; and a display control unit that performs control to display a map screen indicating the travel route and display the actual traveling time and the predicted traveling time together with the map screen.
MORRISON (US 20120042153 A1): In a data processing system having execution circuitry, a method includes providing a reference instruction to the execution circuitry, the reference instruction having an operand; providing a cross-check instruction to the execution circuitry; executing the reference instruction to obtain a first result, wherein, during the step of executing the reference instruction, residual information is derived from execution of the reference instruction; executing the cross-check instruction using the residual information to obtain a second result; and comparing the second result obtained from execution of the cross-check instruction to the operand of the reference instruction to determine whether an error occurred during execution of the reference instruction or the cross-check instruction.
ÖZER (US 20190012242 A1): An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
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/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113