DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is responsive to the application Nº 18/878,093 filed on December 23rd, 2024 in which claims 1-15 are pending and ready for examination.
Information Disclosure Statement
3. Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
5. The examiner contends that the drawings submitted on 12/23/2024 are acceptable for examination proceedings.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1 and 7-9 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Nakatani (US Pub. Nº 2014/0071207).
9. Regarding independent claim 1: Nakatani disclosed a device manufacturing method for manufacturing a piezoelectric device ([0014], lines 1-2; also see Figs. 4A to 4S), the device manufacturing method comprising:
forming a CMOS element on a first surface ([0057], lines 1-2; also see Fig. 4A - Fig. 4K and Fig. 2 reference 22) of a substrate ([0057], line 2; also see Fig. 2, reference 2);
forming a piezoelectric element on the first surface of the substrate on which the CMOS element is formed (Fig. 4L – Fig. 4N; the formation of piezoelectric element 6);
forming a first insulating film in a region where the piezoelectric element is formed when forming the CMOS element or the piezoelectric element (Fig. 4K, reference 5),
forming a lower electrode layer (Fig. 4N, reference 7), a piezoelectric layer (Fig. 4N, reference 8), an upper electrode layer (Fig. 4N, reference 9), and a second insulating film on the first insulating film when forming the piezoelectric element (Fig. 4R, reference 61);
forming a CMOS wiring layer of the CMOS element and a piezoelectric wiring layer of the piezoelectric element after forming the CMOS element and the piezoelectric element on the substrate (The CMOS and the piezoelectric elements are formed in Fig. 4N; wiring 58 is formed in Fig. 4O; further wiring 53 and 54 are formed in Fig. 4Q; this proves that the CMOS wiring and Piezoelectric element wiring are formed after forming the CMOS and the piezoelectric elements); and
forming a void in the substrate from a second surface opposite to the first surface of the substrate after forming the CMOS wiring layer and the piezoelectric wiring layer on the substrate (The transition from Fig. 4R to Fig. 4S shows that void 62/63 is formed after forming the CMOS wiring layer and the piezoelectric wiring layer on substrate 2).
10. Regarding claim 7: Nakatani disclosed the device manufacturing method according to claim 1, wherein; the forming the piezoelectric element uses a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method to form the piezoelectric layer ([0095], lines 1-4).
11. Regarding claim 8: Nakatani disclosed the device manufacturing method according to claim 1, further comprising: forming a through hole penetrating through the piezoelectric element and communicating with the void after forming the void ([0102], lines 3-9; also see Figs. 4S and Fig. 6 which show that the void is first created, then the penetrating trough hole is formed).
12. Regarding claim 9: Nakatani disclosed a head manufacturing method for manufacturing a liquid discharge head ([0014], lines 1-2; also see Figs. 4A to 4S), the head manufacturing method comprising: performing the device manufacturing method according to claim 8 (see the rejection of claim 8); forming the void in the substrate as a liquid chamber ([0074], line 1; also see Fig. 2, reference 62 and Fig. 4S); and forming the through hole as a nozzle hole from which a liquid in the liquid chamber is discharged ([0076], line 1; also see Fig. 2, reference 10 and Fig. 6).
Claim Rejections - 35 USC § 103
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
14. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
15. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakatani (US Pub. Nº 2014/0071207), in view of Arai et al. (US Pub. Nº 2016/0279933).
16. Regarding claim 2: Nakatani disclosed the device manufacturing method according to claim 1, wherein the first insulating film is closer to the first surface of the substrate than the second insulating film (see Fig. 2; insulating film 5 is closer to the surface of substrate 2 than insulating film 61 is).
Nakatani is silent about the forming the first insulating film forms the first insulating film to be thinner than the second insulating film.
Arai et al. disclosed a similar invention with a piezoelectric element (see Fig. 3), including a substrate (Fig. 3, reference 200), including a void (Fig. 3, reference 201), a first insulating film (Fig. 3, reference 105), a lower electrode (Fig. 3, reference 106), a piezoelectric layer (Fig. 3, reference 111), an upper electrode (Fig. 3, reference 107) and a second insulating film (Fig. 3, reference 108), wherein the second insulating film has a thickness thicker than the first insulating film ([0059], lines 3-4 and [0071], line 1; also see Fig. 3 which shows layer 111 thicker than layer 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nakatani with those of Arai et al. by providing a thicker second insulating film than the first insulating film as needed in order to provide adequate heat resistance and insulation properties as disclosed by Arai et al. in paragraph [0067].
17. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nakatani (US Pub. Nº 2014/0071207), in view of Misawa et al. (US Pub. Nº 2014/0184704).
18. Regarding claim 10: Nakatani disclosed the head manufacturing method according to claim 9.
Nakatani is silent about further comprising: forming a liquid contact film on an inner surface of the liquid chamber; and forming a water-repellent film on a nozzle surface on which the nozzle hole is formed.
Misawa et al. disclosed wherein the substrate includes: a liquid contact film on an inner surface of the liquid chamber ([0026], lines 11-13; also see Fig. 1B, reference 201), and a water-repellent film on a nozzle surface on which the nozzle hole is formed ([0032], lines 1-2; also see Fig. 1B, reference 203).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Misawa et al. with those of the combination of Nakatani and Arai et al. by providing a coating in the pressure chamber in order to prevent corrosion by the ink and by providing a liquid repellent coating on the nozzle formation surface in order to prevent clogging of the nozzle due to dried ink residue left around the nozzle opening.
19. Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Nakatani (US Pub. Nº 2014/0071207), in view of McAvoy (US Pub. Nº 2019/0283424).
20. Regarding claim 3: Nakatani disclosed the device manufacturing method according to claim 1.
Nakatani is silent about further comprising: performing heat treatment for impurity diffusion for forming a NMOS source electrode and a drain electrode or a PMOS source electrode and a drain electrode in the CMOS element at a first temperature, wherein the forming the piezoelectric element forms the piezoelectric element at a second temperature lower than the first temperature of the heat treatment for the impurity diffusion.
McAvoy disclosed a method of manufacturing a piezoelectric element comprising a substrate (Fig. 2, reference 102), a CMOS element ([0152], line 1; also see Fig. 2, reference 200) and a piezoelectric element ([0143], line 2; also see Fig. 2, reference 400), and further comprising performing heat treatment for impurity diffusion for forming a NMOS source electrode and a drain electrode or a PMOS source electrode and a drain electrode in the CMOS element at a first temperature (Fig. 2, part of the manufacturing steps of CMOS element 200 (not shown)), wherein the forming the piezoelectric element forms the piezoelectric element at a second temperature lower than the first temperature of the heat treatment for the impurity diffusion ([0070], lines 1-6; [0071], lines 1-4 and [0072], lines 1-3. The piezoelectric element is formed at a temperature that is lower than a treatment and/or degradation temperature of the CMOS element).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of McAvoy with those of Nakatani by forming the piezoelectric element at or below a predetermined temperature in order to prevent degradation of the CMOS element as disclosed by McAvoy in paragraph [0072].
21. Regarding claim 4: The combination of Nakatani and McAvoy disclosed the device manufacturing method according to claim 3, wherein; the second temperature is lower by 100°C or more than the first temperature (McAvoy [0073], lines 1-2; for manufacturing temperature of the piezoelectric element at a temperature of 100°C or less, while the degradation temperature of the CMOS is at or above 450°C).
22. Regarding claim 5: The combination of Nakatani and McAvoy disclosed the device manufacturing method according to claim 4, wherein; the forming the piezoelectric element forms the piezoelectric element at the second temperature of 800°C or lower (McAvoy [0071], lines 1-2).
23. Claims 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nakatani (US Pub. Nº 2014/0071207), in view of Arai et al. (US Pub. Nº 2016/0279933).
24. Regarding independent claim 11: Nakatani disclosed a piezoelectric device comprising:
a substrate ([0057], line 2; also see Fig. 2, reference 2) having a void ([0074], line 1; also see Fig. 2, reference 62);
a CMOS element on a first surface of the substrate ([0057], lines 1-2; also see Fig. 2, reference 22);
a first insulating film on the first surface of the substrate (Fig. 2, reference 5);
a piezoelectric element on the first insulating film ([0046], line 1; also see Fig. 2, reference 6),
the piezoelectric element including:
a lower electrode layer having a first surface on the first insulating film ([0046], line 2; also see Fig. 2, reference 7);
a piezoelectric layer having a first surface on a second surface opposite to the first surface of the lower electrode layer ([0046], line 2; also see Fig. 2, reference 8); and
an upper electrode layer having a first surface on a second surface opposite to the first surface of the piezoelectric layer ([0046], line 3; also see Fig. 2, reference 9); and
a second insulating film on the second surface of the upper electrode layer ([0073], line 1; also see Fig. 2, reference 61).
Nakatani is silent about the second insulating film having a thickness thicker than the first insulating film.
Arai et al. disclosed a similar invention with a piezoelectric element (see Fig. 3), including a substrate (Fig. 3, reference 200), including a void (Fig. 3, reference 201), a first insulating film (Fig. 3, reference 105), a lower electrode (Fig. 3, reference 106), a piezoelectric layer (Fig. 3, reference 111), an upper electrode (Fig. 3, reference 107) and a second insulating film (Fig. 3, reference 108), wherein the second insulating film has a thickness thicker than the first insulating film ([0059], lines 3-4 and [0071], line 1; also see Fig. 3 which shows layer 111 thicker than layer 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nakatani with those of Arai et al. by providing a thicker second insulating film than the first insulating film as needed in order to provide adequate heat resistance and insulation properties as disclosed by Arai et al. in paragraph [0067].
25. Regarding claim 12: The combination of Nakatani and Arai et al. disclosed the piezoelectric device according to claim 11 further comprising: a through hole penetrating through the piezoelectric element and communicating with the void, wherein the piezoelectric element is around the through hole (Nakatani [0076], line 1; also see Fig. 2, reference 10).
26. Regarding claim 13: The combination of Nakatani and Arai et al. disclosed a liquid discharge head (Nakatani [0044], line 1; also see Fig. 2, reference 1) comprising: the piezoelectric device according to claim 12 (see the rejection of claim 12), wherein the void has a liquid chamber accommodating a liquid (Nakatani [0074], lines 4-5; also see Fig. 2, reference 62), and the through hole has a nozzle hole from which the liquid in the liquid chamber is discharged (Nakatani [0076], line 1; also see Fig. 2, reference 64).
27. Regarding claim 15: The combination of Nakatani and Arai et al. disclosed a liquid discharge apparatus comprising: the liquid discharge head according to claim 13; and at least one of: a head tank storing a liquid to be supplied to the liquid discharge head ([0074], lines 4-5); a carriage mounting the liquid discharge head; a supply unit configured to supply the liquid to the liquid discharge head; a maintenance unit configured to maintain the liquid discharge head; or a main scan moving unit configured to move the liquid discharge head in a main scanning direction, combined with the liquid discharge head to form a single unit.
28. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nakatani (US Pub. Nº 2014/0071207), in view of Arai et al. (US Pub. Nº 2016/0279933) as applied to claims 11-13 and 15 above, and further in view of Misawa et al. (US Pub. Nº 2014/0184704).
29. Regarding claim 14: The combination of Nakatani and Arai et al. disclosed the liquid discharge head according to claim 13.
The combination of Nakatani and Arai et al. is silent about wherein the substrate includes: a liquid contact film on an inner surface of the liquid chamber, and a water-repellent film on a nozzle surface on which the nozzle hole is formed.
Misawa et al. disclosed wherein the substrate includes: a liquid contact film on an inner surface of the liquid chamber ([0026], lines 11-13; also see Fig. 1B, reference 201), and a water-repellent film on a nozzle surface on which the nozzle hole is formed ([0032], lines 1-2; also see Fig. 1B, reference 203).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Misawa et al. with those of the combination of Nakatani and Arai et al. by providing a coating in the pressure chamber in order to prevent corrosion by the ink and by providing a liquid repellent coating on the nozzle formation surface in order to prevent clogging of the nozzle due to dried ink residue left around the nozzle opening.
Allowable Subject Matter
30. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
31. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAOVI M. AMEH whose telephone number is (571)272-4578. The examiner can normally be reached M-F: 9:00 AM - 6:00 PM.
32. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
33. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICARDO MAGALLANES can be reached at (571)272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
34. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YAOVI M AMEH/Primary Examiner, Art Unit 2853
Prosecution Insights