DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (CN 109509494).
Regrading Claim 1 Yu discloses: An integrated circuit system for management of wake-up (a circuit for waking up an SRAM memory array, Para. [0034], Fig. 4) process comprising: a plurality of electronic devices; (SRAM array, Para. [0034], Fig. 5); and a wake-up management circuit, (wake up circuit, Para. [0034], Fig. 4) the wake-up management circuit electrically coupled with the plurality of electronic devices, the wake-up management circuit configured to wake up at least one of the plurality of electronic devices in multi-stages. (waking up a first set of SRAM cells VCC1 before waking up a second set of SRAM cells VCC2, , Para. [0035])
Regrading Claim 2 Yu discloses: the plurality of electronic devices comprises a plurality of memory devices. (The devices are SRAM memory array, Para. [0034])
Regrading Claim 3 Yu discloses: the plurality of memory devices comprises at least one of static random-access memory (SRAM), dynamic random-access memory (DRAM), phase change memory (PCM), or resistive random-access memory (RRAM). (the devices are SRAM memory array, Para. [0043]).
Regrading Claim 9 Yu discloses: the wake-up circuit comprises the wake-up circuit configured to strongly discharge responsive to a supply voltage being close to a final value. (the wake up circuit sending a strong signal when the supply voltage is at a high level, Para. [0038]).
Regrading Claim 10 Yu discloses: the wake-up circuit comprises the wake-up circuit configured to have a power-on reset (POR) signal rise from a low voltage to a high voltage level. (a wake up circuit that sends a low voltage signal to initiate waking up an SRAM and raises the voltage to a high level to start all components, , Paras. [0036]-[0038])
Regrading Claim 11 Yu discloses: the wake-up circuit comprises a plurality of metal-oxide semiconductor (MOS) transistors. (MOS transistors PM 11, PM 12, PM 13 and PM 14 in the wake up circuit, , Para. [0037])
Regrading Claim 12 Yu discloses: the plurality of MOS transistors comprises a plurality of positive-MOS (pMOS) transistors. (the MOS transistors PM 11 and P12 are pMOS transistors. (, Para. [0035])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 109509494) in view of Li (Pub No. US 2020/0212894)
Regarding Claim 4, Yu fails to explicitly disclose the integrated circuit system of claim 1, wherein the wake-up circuit comprises a timing resistor capacitor (TRC) circuit. Li, in the analogous art of controlling power circuits (Abstract), teaches a wake up circuit comprising a resistor capacitor circuit (Li teaches a resistor capacitor circuit that is used for timing to eliminate static power consumption of a timer, Li, Para. [0025]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the resistor capacitor circuit of Sichuan for the purpose of improving the power consumption of a device. (Li, Para. [0025]).
Claims 5-8, 13, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 109509494) in view of Li (Pub No. US 2020/0212894) in view of Ning (Pub No. US 2021/0083504)
Regarding Claim 5, Yu fails to explicitly disclose the integrated circuit system of claim 1, wherein the wake-up circuit comprises a plurality of power switches. Ning is in the field of a power supply apparatus (Abstract) and teaches a wake up circuit having a first power switch (330, Ning, Para. [0036]) and a second power switch (220, Ning, Para. [0036]; Ning discloses a wake up circuits including a first and second switching circuit, Ning, Para. [0028]-[0036]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the power switches of Ning for the purpose of adapting the wake up circuit to different configurations (Ning, Para. [0042]).
Regarding Claim 6, Yu fails to explicitly disclose the integrated circuit system of 5 further comprising a control system. Ning teaches an integrated circuit including a control circuit (Ning discloses a control circuit 40 in the integrated circuit, Ning, Para. [0029], Fig. 3). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the control circuit of Ning for the purpose of providing control signals to devices connected to the integrated circuit (Ning, Para. [0029]).
Regarding Claim 7, Yu fails to explicitly disclose the integrated circuit system of claim 6, wherein the control system comprises a ramp up control system. Ning teaches a control circuit (40) ramps the voltage signal up (Ning discloses the control circuit ramping up from sleep mode to a low power mode, Ning, Para. [0029]-[0036]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the ramp up control system of Ning for the purpose of ramping up a signal to move an electrical device from a sleep state to an operational state (Ning, Para. [0034]).
Regarding Claim 8, Yu fails to explicitly disclose the integrated circuit system of claim 1, wherein the wake-up circuit comprises the wake-up circuit configured to slowly discharge responsive to a supply voltage rising above an analog output signal. Ning teaches monitoring the voltage between two points (VM and VDD) and changes the output state of the wake up circuit when the difference is larger than a threshold (Ning discloses monitoring VM and VDD and changing the wake up circuit operating when the difference between VM and VDD is larger than a predetermined voltage signal, Ning, Para. [0034]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the wake up circuit operation of Ning for the purpose of adapting the wake up circuit to different applications (Ning, Para. [0042]).
Regarding Claim 13, Yu fails to explicitly disclose the integrated circuit system of claim 8, wherein the plurality of MOS transistors comprises a plurality of negative-MOS (nMOS) transistors. Ning teaches the use of a negative MOS transistors. (Ning teaches a negative MOS transistor (10), Para. [0027]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the pMOS transistors of Ning for the purpose of releasing a low power consumption rate. (Ning, Para. [0027]-[0028]),
Regarding Claim 15, Yu fails to explicitly discloses the integrated circuit system of claim 1, wherein the wake-up circuit comprises a plurality of power switches. Ning teaches a wake up unit having a plurality of power switches (Ning discloses a wake up circuits including a first and second switching circuit, Ning, Para. [0028]-[0036]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the power switches of Ning for the purpose of adapting the wake up circuit to different configurations (Ning, Para. [0042]).
Regarding Claim 16, Yu discloses a method of managing a wake-up circuit (a circuit for waking up an SRAM memory array, Yu, Para. [0034], Fig. 4) for waking up an electronic device, the method comprising: receiving an indication to wake up the electronic device; responsive to receiving the indication (Yu discloses waking up a first set of SRAM cells VCC1 before waking up a second set of SRAM cells VCC2, Yu, Para. [0035]). Yu fails to explicitly disclose activating a plurality of power switches substantially simultaneously; and modulating a control signal of the plurality of power switches, wherein the modulating reduces a peak value of current draw during waking up of the electronic device. Ning teaches activating a plurality of power switches substantially simultaneously; and modulating a control signal of the plurality of power switches, (Ning discloses a wake up circuits including a first and second switching circuit that are simultaneously activated by a control signal, Ning, Para. [0028]-[0036]); and modulating a control signal to reduce a peak value of current draw during waking up of the electronic device (Ning teaches using a PWM circuit to modulate the control signal (Ning, Para. [0021]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the power switches in Ning for the purpose of reducing the peak value of current draw during a wake up cycle (Ning, Para. [0021]).
Regarding Claim 17, Yu fails to explicitly disclose the method of claim 16, wherein receiving the indication comprises receiving an indication to power up a memory device. Ning teaches receiving an indicator from a user to power up devices (Ning teaches a user initiating a wake up sequence by engaging a switch, Ning, Para. [0016]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the user indicator of Ning for the purpose of initiating a device wake up sequence (Ning, Para. [0016]).
Regarding Claim 18, Yu fails to explicitly discloses the method of claim 16, wherein activating the plurality of power switches comprises activating the plurality of power switches using a ramp-up control system. Ning teaches a control circuit (40) ramps the voltage signal up (Ning discloses the control circuit ramping up from S sleep mode to a low power mode, Ning, Para. [0029]-[0036]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the ramping control circuit of Ning for the purpose of ramping up a signal to move an electrical device from a sleep state to an operational state (Ning, Para. [0034]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 109509494) in view of Audi Ag (EP 1408415)
Regarding Claim 14, Yu fails to explicitly disclose the integrated circuit system of claim 1, wherein the wake-up circuit comprises a plurality of inverters. Audi Ag, in the analogous art of wake up circuit controllers (Abstract), teaches a wake up circuit including a plurality of inverters (Audi Ag teaches a wake up circuit including inverters used to invert a control signal, Audii Ag, Paras. [0012]-[0015]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Yu with the wake up circuit in Audi Ag for the purpose of inverting a control signal (Audi Ag, Paras, [0012]-[0015]).
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Prior art Lee (Pub No. US 2006/0206737) teaches power in a processor that operates with a plurality of sequential stages, the method comprising: providing a memory that stores a wake-up latency of a logic block corresponding to each of the sequential stages, respectively; doing at least one of the following, providing power to the stages at different times when returning to a normal mode from a sleep mode based on the wake-up latencies in the memory, respectively, and cutting off power of the logic blocks sequentially according to completion of operations in each logic block when switching to a sleep mode from a normal mode
Prior art Cabler (Pub No. US 2002/0099966) teaches multi-stage wakeup circuit [Fig.4]
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175
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