DETAILED ACTION
1. This Office Action is responsive to claims filed for No. 18/878,550 on November 17, 2025. Please note Claims 1-18 are pending.
Notice of Pre-AIA or AIA Status
2. The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on December 23, 2024, two entries. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
4. Applicant’s election without traverse of Species 1, Figure 5 and Claims 1-18 in the reply filed on November 17, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-11, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hugon et al. ( US 2020/0161520 A1 ).
Hugon teaches in Claim 1:
A display pixel ( Figure 1, [0063] disclose display pixels with LEDs ) comprising
at least one light-emitting source and an electronic circuit comprising a storage circuit for storing at least one digital signal and a driver circuit for driving said light-emitting source based on the stored digital signal ( Figures 3 and 5, [0094], [0099] discloses the LEDs are connected to a control circuit 20. [0084] discloses the electronic components for control circuit as well as the ability to control the LEDs, i.e. using digital signals. [0136] discloses aspects of the potentials which are applied to the row and column electrodes, using capacitors, etc )
said display pixel comprising at least a first electrically conductive pad intended to receive a first binary signal ( Figures 3 and 4A, [0093] disclose electrode layer 34 for receiving a voltage from the control circuit 20. [0102] disclose rows and clearly control of rows for the connected pixels. [0130]+ disclose details of the binary data for the voltages described above ) and
a second electrically conductive pad intended to receive a second binary signal ( Figures 3 and 4A, [0093] disclose electrode layer 18 for receiving a voltage from the control circuit 20. [0102] disclose columns and clearly control of columns for the connected pixels. [0130]+ disclose details of the binary data for the voltages described above ),
each of the first binary signal and the second binary signal alternating between a low logical state and a high logical state, the low logical state corresponding to a low reference potential and the high logical state corresponding to a power supply voltage ( Figures 13 and 18, [0123] disclose the low and high states for the potentials which are applied. [0105] discloses the modulation of VE for powering the pixels through the rows and columns, i.e. the interpreted first and second binary signals ),
the first and second electrically conductive pads being connected to said electronic circuit ( Figure 3, [0094], [0099] disclose ethe connection of control circuit 20 to electrodes layer 18 and 34 ),
said electronic circuit being configured to update said stored digital signal from the second binary signal after the detection of a first pattern of the first binary signal simultaneously with a second pattern of the second binary signal. ( Figures 13-14, 17, [0131]-[0132] disclose the updated in each of the periods of SR, SG and SB in which a voltage having a duration of activation is transmitted/updated to the sub-pixel. This is applied to electrode layers 18 and 34. Furthermore, Figures 13-14, [0124]-[0129] disclose the potential difference between electrodes 18 and 34 and seeks to have a constant potential reference during one of the phases, for processing the signals by the display pixel. Furthermore, during period S1, the pixel detects whether the potential difference between electrodes 18 and 34 is greater than a predefined limit. More particularly, the pixel detects that the potential V3 is applied to the first electrode and that the potential VO is simultaneously applied to the second electrode so that the difference is equal to V3-VO. The potential V3 present on the first electrode therefore forms the first pattern and the potential VO present on the first electrode therefore forms the second pattern within the meaning of the claim )
Hugon teaches in Claim 2:
The display pixel of claim 1, wherein said electronic circuit is configured not to update said stored digital signal from the second binary signal when the first pattern of the first binary signal is not detected simultaneously with the second pattern of the second binary signal. ( [0125]-[0126] discloses the pixel performs an update only if potential V3 and potential V0 are present simultaneously on both electrodes during period S1. If not, then there is no update for V3 )
Hugon teaches in Claim 3:
The display pixel of claim 1, wherein said electronic circuit is configured to end the update of said stored digital signal from the second binary signal after the detection of a third pattern of the first binary signal simultaneously with a fourth pattern of the second binary signal. ( Respectfully, the third and fourth patterns of the interpreted first and second binary signals, i.e. row and column aspects, are for the next frame and/or row and column of pixels. As the next iteration is done, the current one ends/stops )
Hugon teaches in Claim 4:
The display pixel of claim 3, wherein the third pattern is identical to the first pattern and wherein the fourth pattern is different from the second pattern. ( The potentials detailed in [0124]-[0129] are different for each sub-pixel and Hugon simply wants to maintain the potential difference/reference potential between electrodes 18 and 34; the specific values are or can be different for the sub-pixels )
Hugon teaches in Claim 5:
The display pixel of claim 4, wherein the fourth pattern is the logical complement of the second pattern. ( [0134] discloses Vpix+ and Vpix- as examples of column and row electrodes being opposite/logical complement. Respectfully, the above reasoning is applicable as well given the values can be different based on the sub-pixel values )
Hugon teaches in Claim 6:
The display pixel of claim 1, wherein the first pattern corresponds to the first binary signal remaining at a given logical state. ( [0126] disclose pixels of a same row have defined values, as well as columns of sub-pixels (read as corresponding to/remaining at) )
Hugon teaches in Claim 7:
The display pixel of claim 1, wherein the second pattern corresponds to the second binary signal comprising one rising edge, or two successive rising edges, or one falling edge, or two successive falling edges, or one rising edge followed by one falling edge, or one falling edge followed by one rising edge. ( Figure 13, [0123]-[0124] disclose various low and high levels for Vpix, including rising edges, falling edges, etc. Please note Examiner interprets this claim constructively, given the alternative language )
Hugon teaches in Claim 8:
The display pixel of claim 1, wherein, after the detection of the first pattern of the first binary signal simultaneously with the second pattern of the second binary signal, the electronic circuit is configured to update the digital signal in the storage circuit clocked by a clock signal equal to the first binary signal. ( Figure 24, [0163] disclose flip-flops which receive clock signals and provide outputs. For reference, [0159] discloses M3 are units coupled to the column and row electrodes )
Hugon teaches in Claim 9:
The display pixel of claim 8, wherein the electronic circuit is configured to update successive bits of the digital signal in the storage circuit equal to the successive logical states of the second binary signal at only the rising edges, or at only the falling edges, or at the rising and falling edges of the clock signal. ( To further expand on the reasoning of Claim 8, [0163] discloses updates and this is realized, for examples in Figure 26, which shows b0, b1 and b2 having rising and falling edges )
Hugon teaches in Claim 10:
The display pixel of claim 8, wherein the driver circuit is configured to drive said light-emitting source by pulse-width modulation based of the digital signal and pulses of the first binary signal. ( [0130] discloses pulse width modulation for the transmitted data to be modulated. Furthermore, it notes this data may be binary data as well )
Hugon teaches in Claim 11:
The display pixel of claim 3, wherein said electronic circuit is configured to perform the update of said stored digital signal without needing the simultaneous reception of the first and second patterns and without needing the simultaneous reception of the third and fourth patterns and said driver circuit is configured to perform the driving of said light-emitting source without needing the simultaneous reception of the first and second patterns and without needing the simultaneous reception of the third and fourth patterns. ( To clarify, as Examiner best understands these limitations, the potentials can still be updated without necessarily driving (read as simultaneous reception) of the first/second and third/fourth binary patterns. [0118] discloses active pixels and inactive pixels, which can be ignored the transmitted data. As such, some pixels can be updated without requiring simultaneous reception for the inactive pixels (having their own binary patterns) )
Hugon teaches in Claim 17:
A display screen comprising: display pixels according to claim 1 arranged in rows and in columns ( Figure 11, [0116]+ disclose rows and columns of display pixels );
first electrically conductive tracks extending along the rows and connected to the electronic circuits of the display pixels; a circuit for supplying the first signal comprising the first pattern successively on each first electrically conductive track ( Figure 11, [0115] discloses rows 84. As detailed above, the control circuit provides signals to these aspects, such as row drivers, etc, along the row track, as shown );
second electrically conductive tracks extending along the columns and connected to the electronic circuits of the display pixels; a circuit for supplying the second signals on the second electrically conductive tracks, at least some of the second signals comprising each the second pattern, so that each display pixel receiving simultaneously the first and second patterns performs an update of said stored digital signal. ( Figure 11, [0117] discloses columns 92. As detailed above, the control circuit provides signals to these aspects, such as column drivers, etc, along the column track, as shown. As for the first and second patterns, please note the reasoning in Claim 1 and the intersections of these rows and columns, i.e. simultaneous receiving by/at the pixel )
Hugon teaches in Claim 18:
The display screen of claim 17, wherein the circuit for supplying the first signal and the circuit for supplying the second signals are configured, after the supply of the first pattern on one of said first electrically conductive tracks, not to supply simultaneously the first pattern on said first electrically conductive track and the second pattern on the second electrically conductive tracks during the update performed by the display pixels connected to said first electrically conductive track. ( Respectfully, the same reasoning for Claim 2 is also applicable here as well: [0125]-[0126] discloses the pixel performs an update only if potential V3 and potential V0 are present simultaneously on both electrodes during period S1. If not, then there is no update for V3 )
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hugon et al.
( US 2020/0161520 A1 ), as applied to Claim 1, further in view of Hussell
( US 2021/0043821 A1 ).
As per Claim 12:
Hugon does not explicitly teach “wherein the driver circuit comprises a finite-state machine comprising at least three states, the first state corresponding to the update of said digital signal, the second state corresponding to the driving of said light-emitting source and the third state corresponding to the switching off of said light-emitting source without update of the digital signal.”
However, in the same field of endeavor, display systems, Hussell teaches of an LED driving system, ( Hussell, [0166] ). Furthermore, Hussell teaches of a finite state machine which is configured to identify and take actions based on states of the LED package, [0166]. [0167]+ detail some of the finite or current states and how this impacts operation. Respectfully, in light of Hussell teaching of the finite state machine and various display-related states, one of ordinary skill in the art would realize the states could include aspects such as updating the signal, driving the signal to the LEDs, etc.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the finite state machine, as taught by Hussell, with the motivation that these are well known in the art and can provide the system with a way to update display conditions based on various factors, as is known when using a state machine, ( Hussell, [0166] ).
Hugon and Hussell teach in Claim 13:
The display pixel of claim 12, wherein the transition of the finite-state machine from the second state to the first state corresponds to the detection by said electronic circuit of the first pattern of the first signal simultaneously with the second pattern of the second signal. ( As detailed above, Hugon teaches of the simultaneous detection of the interpreted first and second binary and Hussell teaches of embodying this operation using a finite state machine )
Hugon teaches in Claim 14:
The display pixel of claim 13, wherein the transition of the finite-state machine from the first state to the second state corresponds to the detection by said electronic circuit of the third pattern of the first signal simultaneously with the fourth pattern of the second signal. ( As detailed above, Hugon teaches of the simultaneous detection of the interpreted first and second binary and Hussell teaches of embodying this operation using a finite state machine. To clarify, the transition from a first state to a second state is part of the operation of a finite state machine in general, as one of ordinary skill in the art knows )
Hugon teaches in Claim 15:
The display pixel of claim 12, wherein the transition of the finite-state machine from the second state to the third state corresponds to the detection by said electronic circuit of the third pattern of the first signal simultaneously with the fourth pattern of the second signal. ( As detailed above, Hugon teaches of the simultaneous detection of the interpreted first and second binary and Hussell teaches of embodying this operation using a finite state machine. To clarify, the transition from a second state to a third state is part of the operation of a finite state machine in general, as one of ordinary skill in the art knows )
Hugon teaches in Claim 16:
The display pixel of claim 12, wherein the transition of the finite-state machine from the third state to the second state corresponds to the detection by said electronic circuit of the third pattern of the first signal simultaneously with the fourth pattern of the second signal. ( As detailed above, Hugon teaches of the simultaneous detection of the interpreted first and second binary and Hussell teaches of embodying this operation using a finite state machine. To clarify, the transition from a third state to a second state is part of the operation of a finite state machine in general, as one of ordinary skill in the art knows )
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621