DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The examined claims reflect the preliminary amendment filed 23 December 2024. Accordingly, claims 11, 17 and 19 are amended, claims 21-22 are new, and claims 18 and 20 are cancelled.
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
“a third storage domain” from claim 9.
“a third PCIe switch” from claim 9.
“a third port” from claim 9.
“a plurality of second external storage devices” from claim 9.
“a fifth port” from claim 10.
“a fourth storage domain” from claim 10.
“a fourth PCIe switch” from claim 10.
“a forth port” from claim 10.
“a plurality of third external storage devices” from claim 10.
“a non-transitory storage medium” from claim 19.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 17 and 19 are objected to because of the following informalities:
Claim 17 recites, “wherein the mapping the PCIe request from the first address space of the first port to the second address space of the second port means converting the PCIe request from the first storage domain to the second storage domain” which as best understood by the Examiner in light of the specification should be amended to recite, “wherein the mapping the PCIe request from the first address space of the first port to the second address space of the second port includes converting the PCIe request from the first storage domain to the second storage domain”.
Claim 19 recites, “map the PCIe request from a first address space of the first port”, which as best understood by the Examiner in light of the specification should be amended to recite, “map the PCIe request from a first address space of [[the]]a first port”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 9 and 10:
Claims 9 and 10 recite that the “first PCIe switch is further configured to map the PCIe request transmitted by the central processing unit from the first address space of the first port to a third address space of the third port, and the third PCIe switch is configured to map the PCIe request from the third address space to a second target external storage device” and “the second PCIe switch is further configured to map the PCIe request from the second address space to an address space of the fifth port, and… the fourth PCIe switch is configured to map the PC le request from the address space of the fifth port to an address space of the fourth port, and to map the PC le request from the address space of the fourth port to a third target external storage device”, respectively. However, claim 1 recites “wherein the second PCIe switch is configured to map the PCIe request from the second address space to a first target external storage device”. Accordingly, in each of claims 9 and 10 it is unclear if the second PCIe switch continues to map the PCIe request to the first target external storage device, or if the limitations in claims 9 and 10 are meant to supersede that mapping such that the PCIe request is mapped to the second and third target external storage devices instead of the first, or whether claims 9 and 10 were meant to refer to another, distinct, PCIe request. The specification does not resolve this ambiguity because the specification only ever talks about a PCIe request being routed to a single target storage device and not multiple and are discussed in different embodiments discussed in the specification in the alternative [pg. 3, lines 6-20, CLEAN], [pg. 11, line 17 – pg. 12, line 30, CLEAN].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 8, 11-12, 14-15, 17, 19 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2022/0365899 A1 (Wan) in view of US Patent Application Publication No. US 2019/0197000 A1 (Kurokawa) in further view of the paper by Jack Regula titled, “Using Non-transparent Bridging in PCI Express Systems) published by PLX Technology in 2004 (Regula).
Regarding claim 1 and analogous claims 11, 17 and 19:
Wan teaches, a storage system (where the disclosed methods for operating the storage system may be performed by a computer-readable storage medium including instructions that when executed, perform the method [0180-0181]), comprising: a first storage domain (everything on the left-hand side of [Fig. 2] from the link between Switch 2 and 3 – “The root 2 and the switch and the endpoint that are managed by the root 2 belong to one PCIe system,” where the root is a bridge to the CPU on the left-hand side (i.e., all one domain) [0082]) comprising a central processing unit (the CPU on the left-hand side), a first peripheral component interconnect express (PCIe) switch (Switch 2) and a first port (the connection point at Switch 2 for the link between Switch 2 and Switch 3), wherein the first PCIe switch maps a PCIe request transmitted by the central processing unit from a first address space (the root is responsible for managing all buses and nodes in the PCIe system, and is a bridge for communication between a CPU and an endpoint in the PCIe system (i.e., requests from the CPU to the endpoints and responses back from the endpoints) [0003], which includes endpoints in the right-hand side of [Fig. 2] with communication through the NTB [0082]. Communication through the NTB requires coordination and transformation because they may be using conflicting addresses and accordingly, the NTB controls the addressing between the two PCIe systems [0082[) of the first PCIe system to a second address space of the second PCIe system (the connection point at Switch 3 for the link between Switch 2 and Switch 3 [Fig. 2] (second port)); and a second storage domain comprising a second PCIe switch, the second port and a of first device (by teaching that the second PCIe system includes the switch (3), endpoint (4) (first device) managed by root (2), where the switch (3) includes a connection to the link between Switch 2 and Switch 3 (second port) [0082], wherein the second PCIe switch is configured to map the PCIe request from the second address space to a first target device; and the of first device comprises the first target device (by teaching that the endpoints on the right-hand side PCIe system are accessible to the other PCIe system (on the left-hand side) through the NTB of the switches, where the addresses of the devices in the PCIe system on the right half are manage by the root (2), such that Switch 3 and the NTB can access the endpoint using the addresses assigned for the PCIe system on the right-hand side of [Fig. 2].
Wan does not explicitly disclose, but Kurokawa teaches that the request is to access a first target external storage device among a plurality of first external storage devices (by teaching that a processor is limited to a number of devices that they can use by the number of BDF numbers used by a PCIe domain. Accordingly, even if a number of NVMe SSDs that could be used by the processor are coupled to a PCIe switch, they cannot all be used because of other devices on the PCIe switch, such as a communication interface [0019]. Accordingly, a plurality of NVMe storage devices can be attached through a NTB to a different PCIe domain, which consume BDF numbers of the other PCIe domain, and therefore allow more NVMe-SSDs to be used than BDF numbers [0014] [0057-0063]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the multiple PCIe systems as taught by Wan to include a plurality of SSDs on the secondary (root 2) system domain as taught by Kurokawa.
One of ordinary skill in the art would have been motivated to make this modification because the NVMe SSDs could be used by the CPU, while not consuming BDF numbers for the drive on the PCIe domain of the CPU as taught by Kurokawa in [0063].
Wan in view of Kurokawa do not explicitly disclose, but Regula teaches that the of the NTB ports of the two switches have their own address spaces, by teaching than in a PCIe switch, a port would either identify itself as an upstream or downstream port, or an NTB port would identify itself as an endpoint [pg. 5, ¶5], as it masquerades as an endpoint while actually being a port [pg. 4, last ¶] [§Switch Port or Endpoint, pgs. 17-18]. When both the requester and completer are behind a non-transparent switch port (as disclosed in Wan), the requester ID is first translated from the address space of the non-transparent switch port to the address space of the other non-transparent switch port [see Fig. 8, pg. 16]. As can also be seen in [Fig. 8, pg. 16], the request is also mapped by the receiving NTB port from the address space of the second NTB port to the target device in the CAM [§Requester ID Translation: pgs. 11-15]. Moreover, the NTB ports translate the address of the transactions that cross the bridge [pg. 4: last ¶] [pg. 5, ¶2] [pg. 7: ¶4-5] [§Transaction Forwarding with Address Translation, pgs. 7-11]. The translation is required because the addressing of the two systems is isolated [Figs 1-3, 8] [pg. 5, ¶2] [pg. 4, ¶3-7]. [Fig. 15] shows a dual host system with both hosts active, in which each host serves as the secondary to the other, similar to the description of the PCIe network disclosed in Wan.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switches as taught by Wan to use the NTB ports with their own address spaces and which translate transactions passing through them into the address space of the receiving port as taught by Regula.
One of ordinary skill in the art would have been motivated to make this modification because a non-transparent bridge can be used to link a secondary host within the hierarchy of a primary host while providing isolation and communication between the two systems as taught by Regula in [pg. 5. ¶2]. Furthermore, the NTB ports allow implementing a multiprocessor system while using industry standard practices in the PCI paradigm, which is important as distributed systems are gaining popularity [pg. 4, ¶1-4].
Regarding claim 3 and analogous claim 21:
The storage system as claimed in claim 1 is made obvious by Wan in view of Kurokawa in further view of Regula (Wan-Kurokawa-Regula).
Wan in view of Kurokawa does not explicitly disclose, but Regula teaches, wherein the first port is a non-transparent bridge virtual port, and the second address space is an address space of the non-transparent bridge virtual port (by teaching that the of the NTB ports of the two switches have their own address spaces, by teaching than in a PCIe switch, a port would either identify itself as an upstream or downstream port, or an NTB port would identify itself as an endpoint [pg. 5, ¶5], as it masquerades as an endpoint while actually being a port (i.e., virtual port) [pg. 4, last ¶] [§Switch Port or Endpoint, pgs. 17-18]. When both the requester and completer are behind a non-transparent switch port (as disclosed in Wan), the requester ID is first translated from the address space of the non-transparent switch port to the address space of the other non-transparent switch port [see Fig. 8, pg. 16]. As can also be seen in [Fig. 8, pg. 16], the request is also mapped by the receiving NTB port from the address space of the second NTB port to the target device in the CAM [§Requester ID Translation: pgs. 11-15]. Moreover, the NTB ports translate the address of the transactions that cross the bridge [pg. 4: last ¶] [pg. 5, ¶2] [pg. 7: ¶4-5] [§Transaction Forwarding with Address Translation, pgs. 7-11]. [Fig. 15] shows a dual host system with both hosts active, in which each host serves as the secondary to the other, similar to the description of the PCIe network disclosed in Wan.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switches as taught by Wan to use the NTB ports with their own address spaces and which translate transactions passing through them into the address space of the receiving port as taught by Regula.
One of ordinary skill in the art would have been motivated to make this modification because a non-transparent bridge can be used to link a secondary host within the hierarchy of a primary host while providing isolation and communication between the two systems as taught by Regula in [pg. 5. ¶2]. Furthermore, the NTB ports allow implementing a multiprocessor system while using industry standard practices in the PCI paradigm, which is important as distributed systems are gaining popularity [pg. 4, ¶1-4].
Regarding claim 4 and analogous claim 22:
The storage system as claimed in claim 3 is made obvious by Wan-Kurokawa-Regula.
Wan in view of Kurokawa does not explicitly disclose, but Regula teaches, wherein the second port is a non-transparent bridge connection port, and the second address space is an address space of the non-transparent bridge connection port (by teaching that the of the NTB ports of the two switches have their own address spaces, by teaching than in a PCIe switch, a port would either identify itself as an upstream or downstream port, or an NTB port would identify itself as an endpoint [pg. 5, ¶5], as it masquerades as an endpoint while actually being a port [pg. 4, last ¶] [§Switch Port or Endpoint, pgs. 17-18]. When both the requester and completer are behind a non-transparent switch port (as disclosed in Wan), the requester ID is first translated from the address space of the non-transparent switch port to the address space of the other non-transparent switch port [see Fig. 8, pg. 16]. As can also be seen in [Fig. 8, pg. 16], the request is also mapped by the receiving NTB port (the second port is a non-transparent bridge connection port) from the address space of the second NTB port to the target device in the CAM (and the second address space is an address space of the non-transparent bridge connection port) [§Requester ID Translation: pgs. 11-15]. Moreover, the NTB ports translate the address of the transactions that cross the bridge (i.e., into the address space of the non-transparent bridge connection port) [pg. 4: last ¶] [pg. 5, ¶2] [pg. 7: ¶4-5] [§Transaction Forwarding with Address Translation, pgs. 7-11]. [Fig. 15] shows a dual host system with both hosts active, in which each host serves as the secondary to the other, similar to the description of the PCIe network disclosed in Wan.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switches as taught by Wan to use the NTB ports with their own address spaces and which translate transactions passing through them into the address space of the receiving port as taught by Regula.
One of ordinary skill in the art would have been motivated to make this modification because a non-transparent bridge can be used to link a secondary host within the hierarchy of a primary host while providing isolation and communication between the two systems as taught by Regula in [pg. 5. ¶2]. Furthermore, the NTB ports allow implementing a multiprocessor system while using industry standard practices in the PCI paradigm, which is important as distributed systems are gaining popularity [pg. 4, ¶1-4].
Regarding claim 6:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan-Kurokawa-Regula further make obvious, wherein the first address space and the second address space are isolated in terms of addressing (through the analysis performed for claim 1).
Regarding claim 8:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan-Kurokawa-Regula further disclose, wherein a type of the first external storage device comprises at least one of a PCIe device, an external interface card, and a solid state disk (through the analysis performed in claim 1 where Kurokawa teaches the secondary domain may have a plurality of NVMe SSDs attached).
Regarding claim 12:
The method as claimed in claim 11 is made obvious by Wan-Kurokawa-Regula.
Wan in view of Kurokawa do not explicitly disclose, but Regula teaches, wherein the first address space comprises a plurality of first address fields, each of the first address fields comprises a plurality of second address fields, (by teaching that the non-transparent bridge uses the BARs (plurality of address fields) to define the size and type of its aperture as well as address translation. The BARs are used to translate a memory address from the primary address map to the secondary address map. The primary address map includes a Base, Index and Offset fields of the address (plurality of second address fields) [Fig. 2, pg. 8] [pg. 7, ¶4] [pg. 8, ¶2]) each second address space comprises a plurality of third address fields, all the third address fields are located in the second address space, (by teaching that the third address fields include the translated base and offset in the secondary address map, which are all in the secondary address map and within the second domain as the domains are isolated [pg. 8, ¶2] [Fig. 2, pg. 8], [pg. 7, ¶4] [pg. 5, ¶2] [pg. 4, last ¶]) and the mapping the PCIe request from the first address space of the first port to the second address space of the second port by the first PCIe switch comprises: locating the PCIe request to a target second address field in the plurality of second address fields; and mapping the PCIe request from the target second address field to a target third address field in the plurality of third address fields according to a relation between the plurality of second address fields and the plurality of third address fields (by teaching that the index of the address (target second address field) is used to index into a table to determine the translated base address (target third address field) according to the lookup table (according to a relation between the plurality of second address fields and the plurality of third address fields) [see Fig. 2, pg. 8]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switches as taught by Wan to use the NTB ports with their own address spaces and which translate transactions passing through them into the address space of the receiving port as taught by Regula.
One of ordinary skill in the art would have been motivated to make this modification because a non-transparent bridge can be used to link a secondary host within the hierarchy of a primary host while providing isolation and communication between the two systems as taught by Regula in [pg. 5. ¶2]. Furthermore, the NTB ports allow implementing a multiprocessor system while using industry standard practices in the PCI paradigm, which is important as distributed systems are gaining popularity [pg. 4, ¶1-4].
Regarding claim 14:
The method as claimed in claim 11 is made obvious by Wan-Kurokawa-Regula.
Wan further discloses, wherein in a case that the PCIe request is a reading request, after the mapping the PCIe request from the second address space to the target endpoint in the plurality of external storage devices connected to the second PCIe switch by the first PCIe switch, the method further comprises (by teaching that there are six PCIe command types that may be sent in a transaction layer packet (TLP) as part of the PCIe protocol: memory read/write, input output read/write, configuration read/write, message request, completion, and atomic operations [0084] [0087]).
Wan does not explicitly disclose, but Kurokawa teaches that the target endpoint may be an external storage device, such that performing the command on it would include reading data indicated by the reading request from the target external storage device (by teaching that the endpoints may be NVMe-SSDs, which are accessible from a different domain than the root complex which issued the request (i.e., such as the read request as taught by Wan), and therefore a CPU can use more NVMe-SSDs than it has BDF numbers for on its local PCIe bus [0014] [0019] [0062-0064].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the multiple PCIe systems as taught by Wan to include a plurality of SSDs on the secondary (root 2) system domain usable by the root on the first domain as taught by Kurokawa.
One of ordinary skill in the art would have been motivated to make this modification because the NVMe SSDs could be used by the CPU, while not consuming BDF numbers for the drive on the PCIe domain of the CPU as taught by Kurokawa in [0063].
Regarding claim 15:
The method as claimed in claim 11 is made obvious by Wan-Kurokawa-Regula.
Wan further discloses, wherein in a case that the PCIe request is a writing request, after the mapping the PCIe request from the second address space to the target endpoint in the plurality of external storage devices connected to the second PCIe switch by the first PCIe switch, the method further comprises (by teaching that there are six PCIe command types that may be sent in a transaction layer packet (TLP) as part of the PCIe protocol: memory read/write, input output read/write, configuration read/write, message request, completion, and atomic operations [0084] [0087]).
Wan does not explicitly disclose, but Kurokawa teaches that the target endpoint may be an external storage device, such that performing the command on it would include writing data indicated by the reading request from the target external storage device (by teaching that the endpoints may be NVMe-SSDs, which are accessible from a different domain than the root complex which issued the request (i.e., such as the read request as taught by Wan), and therefore a CPU can use more NVMe-SSDs than it has BDF numbers for on its local PCIe bus [0014] [0019] [0062-0064].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the multiple PCIe systems as taught by Wan to include a plurality of SSDs on the secondary (root 2) system domain usable by the root on the first domain as taught by Kurokawa.
One of ordinary skill in the art would have been motivated to make this modification because the NVMe SSDs could be used by the CPU, while not consuming BDF numbers for the drive on the PCIe domain of the CPU as taught by Kurokawa in [0063].
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wan-Kurokawa-Regula in further view of US Patent Application Publication No. US 2016/0134564 A1 (Egi).
Regarding claim 2:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan does not explicitly disclose, but Regula teaches, wherein the first address space comprises a plurality of first address fields, each of the first address fields comprises a plurality of second address fields (by teaching that the non-transparent bridge uses the BARs (plurality of address fields) to define the size and type of its aperture as well as address translation. The BARs are used to translate a memory address from the primary address map to the secondary address map. The primary address map includes a Base, Index and Offset fields of the address (plurality of second address fields) [Fig. 2, pg. 8] [pg. 7, ¶4] [pg. 8, ¶2]) each second address space comprises a plurality of third address fields, all the third address fields are located in the second address space, (by teaching that the third address fields include the translated base and offset in the secondary address map, which are all in the secondary address map and within the second domain as the domains are isolated [pg. 8, ¶2] [Fig. 2, pg. 8], [pg. 7, ¶4] [pg. 5, ¶2] [pg. 4, last ¶]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switches as taught by Wan to use the NTB ports with their own address spaces and which translate transactions passing through them into the address space of the receiving port as taught by Regula.
One of ordinary skill in the art would have been motivated to make this modification because a non-transparent bridge can be used to link a secondary host within the hierarchy of a primary host while providing isolation and communication between the two systems as taught by Regula in [pg. 5. ¶2]. Furthermore, the NTB ports allow implementing a multiprocessor system while using industry standard practices in the PCI paradigm, which is important as distributed systems are gaining popularity [pg. 4, ¶1-4].
Wan in view of Regula do not explicitly disclose, but Egi teaches, and there is a mapping relation between the third address fields and address fields of an external storage device wherein a preset number of third address fields are address fields of one endpoint (i.e., external storage device as taught by Wan in view of Kurokawa) by teaching that resources attached to a switch are enumerated with addresses (Y0, Y1, Y2, X0, X1, X2, X3) and the resources can be end-point devices. Various mapping approaches can be used to map addresses allocated to the NTB to the addresses of the resources on the other side [0046]. One mapping approach is an address translation table to map the address range of a NTB to an address range of the resources next to each other in the mapped address region. Such that the length or size of the address range allocated on one side of the NTB is equivalent to the sum of addresses of the resources on the other side of the NTB, and an address translation table is used to map each resources addresses to the address space allocated to the NTB [0048]. The size of the address range allocated to the resources is determined during enumeration (preset number) [0046]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the address space of the NTB ports that are used to access the endpoints on the other side, such as SSDs, as taught by Wan in view of Kurokawa in further view of Regula to be mapped to the resources on the other side with an address translation table that corresponds the addresses of the NTB to the addresses of the endpoint resources as taught by Egi.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that the resources can be accessed through the NTB as taught by Egi in [0050].
Regarding claim 13:
The method as claimed in claim 12 is made obvious by Wan-Kurokawa-Regula.
Wan in view of Kurokawa do not explicitly disclose, but Egi teaches, wherein there is a mapping relation between the third address fields and address fields of an endpoint, and the mapping the PCIe request from the second address space to the target endpoint in the plurality of endpoints connected to the second PCIe switch by the first PCIe switch comprises: mapping the PCIe request from a preset number of target third address fields to the target external endpoint according to the mapping relation between the third address fields and the endpoints (i.e., a target external storage device among a plurality of external storage devices as taught by Wan in view of Kurokawa) by teaching that resources attached to a switch are enumerated with addresses (Y0, Y1, Y2, X0, X1, X2, X3) and the resources can be end-point devices. Various mapping approaches can be used to map addresses allocated to the NTB to the addresses of the resources on the other side [0046]. One mapping approach is an address translation table to map the address range of a NTB to an address range of the resources next to each other in the mapped address region. Such that the length or size of the address range allocated on one side of the NTB is equivalent to the sum of addresses of the resources on the other side of the NTB, and an address translation table is used to map each resources addresses to the address space allocated to the NTB [0048]. The size of the address range allocated to the resources is determined during enumeration (preset number) [0046]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the address space of the NTB ports that are used to access the endpoints on the other side, such as SSDs, as taught by Wan in view of Kurokawa in further view of Regula to be mapped to the resources on the other side with an address translation table that corresponds the addresses of the NTB to the addresses of the endpoint resources as taught by Egi.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that the resources can be accessed through the NTB as taught by Egi in [0050].
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wan-Kurokawa-Regula in further view of US 2018/0059939 A1 (He).
Regarding claim 7 and analogous claim 16:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan in view of Kurokawa do not explicitly disclose, but He teaches, wherein the central processing unit is configured to map the PCIe request from an address space of the central processing unit to the first address space of the first port (by teaching that MMIO is specified in the PCIe standard, such that an address space of a PCIe device (like the NTB of the switch as taught by Wan) is mapped to the addressing space of a CPU. When accessing the address space of the PCIe device, the CPU accesses the PCIe device by accessing the addressing space, which may use an instruction the same as that used for reading and writing to a data buffer address [0107]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the access by the CPU to the NTB port of the switch as taught by Wan-Kurokawa-Regula to include mapping the PCIe request from the address space of the CPU to the address space of the PCIe device (such as the NTB of the switch as taught by Wan) as taught by He.
One of ordinary skill in the art would have been motivated to make this modification because it reduces program design difficulty and interface complexity as taught by He in [0107].
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wan-Kurokawa-Regula in further view of US Patent No. US 8,917,734 B1 (Brown).
Regarding claim 9:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan-Kurokawa-Regula do not explicitly disclose, but Brown teaches, further comprising: a third storage domain comprising a third PCIe switch, a third port, and a plurality of second external storage devices, wherein the first PCIe switch is further configured to map the PCIe request transmitted by the central processing unit from the first address space of the first port to a third address space of the third port, and the third PCIe switch is configured to map the PCIe request from the third address space to a second target external storage device, wherein the plurality of second external storage devices comprise the second target external storage device (by teaching that an NT port (404) of first switch (402) in a first domain (domain of RC 400) may be used to communicate in a fan-out fashion with more than one domain, for example, the domain encompassing Switch 1 through NT port (428) or the domains encompassing Switch N or Switch 2 through NT ports (432) or (460) respectively [Fig. 4] [Col 4: lines 4-55] [Col 1: lines 42-45] [Col 6: lines 11-36]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the NT-Bridge used to access another domain with the address translation and other teachings of Wan-Kurokawa-Regula (i.e., such as the other domains to include NVMe SSDs) to include accessing more than one domain by connecting to other switches in a fan-out fashion as taught by Brown.
One of ordinary skill in the art would have been motivated to make this modification because a PCIe switch may be coupled together with others in a tree topology in order to accommodate multiple root complexes so that they can share a group of input/output devices, and support functions like mirroring or failover as taught by Brown in [Col 4: lines 4-55] [Col 1: lines 42-45].
Regarding claim 10:
The storage system as claimed in claim 1 is made obvious by Wan-Kurokawa-Regula.
Wan-Kurokawa-Regula do not explicitly disclose, but Brown teaches, wherein the second storage domain further comprises a fifth port, the second PCIe switch is further configured to map the PCIe request from the second address space to an address space of the fifth port, and the system further comprises: a fourth storage domain comprising a fourth PCIe switch, a fourth port, and a plurality of third external storage devices, wherein the fourth PCIe switch is configured to map the PCIe request from the address space of the fifth port to an address space of the fourth port, and to map the PCIe request from the address space of the fourth port to a third target external storage device, wherein the plurality of third external storage devices comprise the third target external storage device (by teaching that a first switch (Switch 0) may be connected to a second Switch in a second domain (Switch 1), which may then be connected to a third switch (Switch N) in a third domain, such that the switches and domains may be cascaded, with each switch and each domain connected to a plurality of endpoints (EP) (i.e., NVMe SSDs as taught by Kurokawa) [Fig. 3] [Col 4: lines 4-55] [Col 1: lines 42-45] [Col 5: lines 30-59]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the NT-Bridge used to access another domain with the address translation and other teachings of Wan-Kurokawa-Regula (i.e., such as the other domains to include NVMe SSDs) to include accessing more than one domain by connecting to other switches in a cascading fashion as taught by Brown.
One of ordinary skill in the art would have been motivated to make this modification because a PCIe switch may be coupled together with others in a tree topology in order to accommodate multiple root complexes so that they can share a group of input/output devices, and support functions like mirroring or failover as taught by Brown in [Col 4: lines 4-55] [Col 1: lines 42-45].
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach, “wherein the non-transparent bridge virtual port and the non-transparent bridge connection port are both arranged on the first PCIe switch” as recited in claim 5 because the prior art teaches the two ports being on separate switches within separate domains as disclosed in Wan and Regula. Furthermore, one of ordinary skill in the art would not have been motivated to modify the prior art to arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2018/0341619 A1 (Slik) – teaches that a non-transparent bridge may be used to connect a plurality of modules so that they can communicate with each other and share resource [Fig. 2].
US Patent Application Publication No. US 2016/0098372 A1 (Boyle) – teaches a system where a primary domain can access endpoint devices on a secondary PCIe domain [Fig. 2].
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139