DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-16 are objected to because of the following informalities:
“processors (202a, 202b)” in line 2 of claim 1 includes references in parentheses to items 202a and 202b in Figure 2 of Applicant’s Drawings filed 12/24/2024, however there is no mention and/or illustration of the items 202a and 202b in Applicant’s Drawings.
“a first processor (202a)” and “a second processor (202b)” in lines 2 and 3 of claim 9, respectively, includes citations in parentheses to items in Figure 2 of the Drawings filed 12/24/2024, however there is no mention and/or illustration of the items 202a and 202b in the Drawings.
“a first processor (202a)” and “a second processor (202b)” in lines 2 and 3-4 of claim 16, respectively, includes citations in parentheses to items in Figure 2 of the Drawings filed 12/24/2024, however there is no mention and/or illustration of the items 202a and 202b in the Drawings.
Claims 2-8 and 10-15 are objected to because they dependent on the objected claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-7, 9, 11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Griffin (US 10,095,543) in view of Bonola (US 2011/0047310).
Regarding claim 1, Griffin teaches a system for data transfer, the system comprising: processors (Fig. 1A, Cores 3; Col. 7, Lines 8-10, Each of the tiles 3 is a functional unit that includes a processor (or “processor core”)); and a memory operatively coupled with the processors (Fig. 1B, Cores 3 includes memory 14 and 16 that performs instructions; Col. 7, Lines 59-63, a tile 3 includes a processor 10… The processor 10 includes a program counter 12, an instruction memory 14, a data memory 16), wherein the memory comprises processor-executable instructions, which on execution, cause a first processor of the processors to: determine that data is set for transmission from the first processor to a second processor of the processors (Fig. 1A, First core 3 determines memory access request with write data to transmit data from second core 3; Col. 7, Lines 8-11, Each of the tiles 3 is a functional unit that includes a processor (or “processor core”) and a switch that forwards data from other tiles to the processor and to switches of other tiles over data paths 4); copy the data to at least one memory address of the first processor based on the determination (Fig. 6A, Writer process 52 (i.e. first core 3 of Figure 1A) writes data (i.e. copy) to a memory location 56; Col. 23, Lines 39-40, a writer process 52 has acquired a lock 54 and is allowed to write to a memory location 56), wherein the at least one memory address of the first processor is directly mapped with at least one memory address of the second processor (Figs. 6A and 6B, Memory location 56 is a memory address that is mapped to writer process 52 (i.e. first processor 3 of Figure 1A) and reader process 58a (i.e. second processor 3 of Figure 1A); Col. 23, Lines 42-44, a reader process 58a has acquired the lock 54 and is allowed to read from the memory location 56); trigger an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 1A, Inter-processor interrupts are transmitted between cores 3 via channels 4 of the on-chip network; Col. 22, Lines 48-50, To send an interrupt, the core performs a store operation to a page that is marked as memory-mapped-IO (MMIO)… Col. 22, Lines 22-24, sending an interrupt or IPI using a special IPI interface implemented in hardware through IPI reflector circuitry in the on-chip network); and transmit to the second processor via the IPI (Fig. 1A, Interrupts are transmitted between cores 3; Col. 21, Lines 51-54, Causing interrupts or notifications on a remote core includes mechanisms to notify the remote core (or a process running on the remote core) of an event (e.g., that data has been written into a ring buffer)… Col. 22, Lines 52-55, reflector forwards the interrupt message to the target core. Once the message reaches the target core, an appropriate interrupt is signaled on the target core).
Griffin does not teach the system comprising: in response to the copying of the data, trigger an inter-processor interrupt (IPI) over at least one channel of the second processor; and transmit the data to the second processor via the IPI.
Bonola teaches the system comprising: in response to the copying of the data (Fig. 11A, Core 1102 (i.e. first processor) writes data into FIFO queue 1106 and generates IPI in response; Paragraph 0044, first core 1102 configures an internal LAPIC 1103 to automatically generate IPIs by writing a description of the memory region 1104 containing a FIFO queue 1106 into an IMR register 1108), trigger an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 11A, Interrupt is triggered in response to writing to the register 1108; Paragraph 0044, By writing this information into the IMR 1108, the first core directs the LAPIC to generate and transmit a specified type of IPI to one or more specified target cores); and transmit the data to the second processor via the IPI (Fig. 11B, Interrupt is transmitted from first core 1102 to second core 1120 (i.e. second processor) via channel 1106, which in response causes transmission of data between 1102 and 1120 via FIFO 1106; Paragraph 0045, FIG. 11B, the first core 1102 places an entry 1110… placing the entry into the queue involves a WRITE operation to the shared-memory region specified in an IMR, the LAPIC 1116 of the first core 1102 automatically generates an interrupt that is transmitted to the LAPIC 1118 of the second core 1120. Upon receiving the interrupt, the second core then calls an appropriate interrupt handler for retrieving information from the FIFO queue).
Griffin and Bonola are analogous arts because they are in the same field of endeavor of using inter-processor interrupts between cores to facilitate data transfer between cores.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin’s system to incorporate the teachings of Bonola and enable the inter-processor interrupt of Griffin to be triggered via copying the data and transfer the data using the inter-processor interrupt.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an efficient and easily-applied inter-core communication mechanism via interrupt notifications, thus increasing throughput in a multi-core system (See Bonola: Paragraphs 0004 and 0040).
Regarding claim 3, Griffin in view of Bonola teaches the system of claim 1. Griffin teaches the system comprising wherein the first processor is to trigger the IPI over the at least one channel of the second processor by being configured to: establish a connection between the first processor and the second processor once the data is copied (Figs. 14 and 17A, Channel is created in 174 based on contexts 180, see Fig. 17A, 260; Col. 37, Lines 34-40, A mesh interface 174 includes network interface circuitry 176 for coupling data to or from the tiles of a tiled processor, for example. The network interface circuitry 176 is coupled to a context module 180 including context registers 182, global registers 184, a TLB, and storage for context specific state 188… Col. 41, Lines 15-18, decompression scheduler 238 selects (260) the particular context corresponding to the context register, and a channel for the sending the transaction packet 244 to one of the decompression engines 240a); generate the IPI based on the established connection (Figs. 6A and 6B, When data is written to memory location 56 and a channel is selected, an IPI is generated; Col. 21, Lines 51-54, Causing interrupts or notifications on a remote core includes mechanisms to notify the remote core (or a process running on the remote core) of an event (e.g., that data has been written into a ring buffer)); and trigger the IPI over the at least one channel of the second processor in response to the generation of the IPI (Col. 22, Lines 48-50, To send an interrupt, the core performs a store operation to a page that is marked as memory-mapped-IO (MMIO)).
Regarding claim 6, Griffin in view of Bonola teaches the system of claim 1. Griffin teaches the system comprising wherein the memory comprises processor-executable instructions, which on execution, cause the first processor to store the data in a buffer region, and wherein the buffer region comprises at least one of: a Downlink (DL) buffer region, a DL queue region, a DL queue control region, a slot indication region, an uplink (UL) buffer region, an UL queue region, and an UL queue control region (Figs. 4A and 4B, Shared memory is ring buffer which goes downlink from source to sink and includes slot regions; Col. 17, Lines 11-14, shared memory queues use a “ring buffer” with storage for a static number of data items. As data items are produced, they are written at a “tail” location within the ring buffer and the tail pointer is advanced to the next slot in the ring buffer).
Regarding claim 7, Griffin in view of Bonola teaches the system of claim 6. Griffin teaches the system comprising wherein the DL queue region provides pointers to indicate a memory address of the data to be transmitted upon generation of the IPI (Figs. 4A and 4B, Head and tail pointers on the ring buffer are used to indicate a memory address; Col. 17, Lines 12-16, As data items are produced, they are written at a “tail” location within the ring buffer and the tail pointer is advanced to the next slot in the ring buffer. Similarly, a “head” pointer points to the buffer slot that contains the next item to be dequeued).
Regarding claim 9, Griffin teaches a method for data transfer, the method comprising: determining, by a first processor associated with a system, that data is set for transmission to a second processor (Fig. 1A, First core 3 determines memory access request with write data to transmit data from second core 3; Col. 7, Lines 8-11, Each of the tiles 3 is a functional unit that includes a processor (or “processor core”) and a switch that forwards data from other tiles to the processor and to switches of other tiles over data paths 4); copying, by the first processor, the data to at least one memory address of the first processor based on the determination (Fig. 6A, Write data (i.e. copy) to a memory location 56; Col. 23, Lines 39-40, a writer process 52 has acquired a lock 54 and is allowed to write to a memory location 56), wherein the at least one memory address of the first processor is directly mapped with at least one memory address of the second processor (Figs. 6A and 6B, Memory location 56 is a memory address that is mapped to first processor 52 and second processor 58a; Col. 23, Lines 42-44, a reader process 58a has acquired the lock 54 and is allowed to read from the memory location 56); triggering, by the first processor, an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 1A, Inter-processor interrupts are transmitted between cores 3 via channels 4 of the on-chip network; Col. 22, Lines 48-50, To send an interrupt, the core performs a store operation to a page that is marked as memory-mapped-IO (MMIO)… Col. 22, Lines 22-24, sending an interrupt or IPI using a special IPI interface implemented in hardware through IPI reflector circuitry in the on-chip network); and transmitting, by the first processor, to the second processor via the IPI (Fig. 1A, Interrupts are transmitted between cores 3; Col. 21, Lines 51-54, Causing interrupts or notifications on a remote core includes mechanisms to notify the remote core (or a process running on the remote core) of an event (e.g., that data has been written into a ring buffer)… Col. 22, Lines 52-55, reflector forwards the interrupt message to the target core. Once the message reaches the target core, an appropriate interrupt is signaled on the target core).
Griffin does not teach the method comprising: triggering an inter-processor interrupt (IPI) over at least one channel of the second processor in response to the copying of the data; and transmitting the data to the second processor via the IPI.
Bonola teaches the method comprising: triggering an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 11A, Interrupt is triggered in response to writing to the register 1108; Paragraph 0044, By writing this information into the IMR 1108, the first core directs the LAPIC to generate and transmit a specified type of IPI to one or more specified target cores) in response to the copying of the data (Fig. 11A, Core 1102 (i.e. first processor) writes data into IMR register 1108 (i.e. copying the data); Paragraph 0044, first core 1102 configures an internal LAPIC 1103 to automatically generate IPIs by writing a description of the memory region 1104 containing a FIFO queue 1106 into an IMR register 1108); and transmitting, by the first processor, the data to the second processor via the IPI (Fig. 11B, Interrupt is transmitted from first core 1102 to second core 1120 via channel 1106, which in response causes transmission of data between 1102 and 1120 via FIFO 1106; Paragraph 0045, FIG. 11B, the first core 1102 places an entry 1110… placing the entry into the queue involves a WRITE operation to the shared-memory region specified in an IMR, the LAPIC 1116 of the first core 1102 automatically generates an interrupt that is transmitted to the LAPIC 1118 of the second core 1120. Upon receiving the interrupt, the second core then calls an appropriate interrupt handler for retrieving information from the FIFO queue).
Griffin and Bonola are analogous arts because they are in the same field of endeavor of using inter-processor interrupts between cores to facilitate data transfer between cores.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin’s method to incorporate the teachings of Bonola and enable the inter-processor interrupt of Griffin to be triggered via copying the data and transfer the data using the inter-processor interrupt.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an efficient and easily-applied inter-core communication mechanism via interrupt notifications, thus increasing throughput in a multi-core system (See Bonola: Paragraphs 0004 and 0040).
Regarding claim 11, Griffin in view of Bonola teaches the method of claim 9. Griffin teaches the method comprising wherein triggering, by the first processor, the IPI over the at least one channel of the second processor comprises: establishing a connection between the first processor and the second processor once the data is copied (Figs. 14 and 17A, Channel is created in 174 based on contexts 180, see Fig. 17A, 260; Col. 37, Lines 34-40, A mesh interface 174 includes network interface circuitry 176 for coupling data to or from the tiles of a tiled processor, for example. The network interface circuitry 176 is coupled to a context module 180 including context registers 182, global registers 184, a TLB, and storage for context specific state 188… Col. 41, Lines 15-18, decompression scheduler 238 selects (260) the particular context corresponding to the context register, and a channel for the sending the transaction packet 244 to one of the decompression engines 240a); generating the IPI based on the established connection (Figs. 6A and 6B, When data is written to memory location 56 and a channel is selected, an IPI is generated; Col. 21, Lines 51-54, Causing interrupts or notifications on a remote core includes mechanisms to notify the remote core (or a process running on the remote core) of an event (e.g., that data has been written into a ring buffer)); and triggering the IPI over the at least one channel of the second processor in response to the generation of the IPI (Col. 22, Lines 48-50, To send an interrupt, the core performs a store operation to a page that is marked as memory-mapped-IO (MMIO)).
Regarding claim 14, Griffin in view of Bonola teaches the method of claim 9. Griffin teaches the method comprising storing, by the first processor, the data in a buffer region (Fig. 6A, First processor 52 stores data in memory location 56 which is the ring buffer), wherein the buffer region comprises at least one of: a Downlink (DL) buffer region, a DL queue region, a DL queue control region, a slot indication region, an uplink (UL) buffer region, an UL queue region, and an UL queue control region (Figs. 4A and 4B, Shared memory is ring buffer which goes downlink from source to sink and includes slot regions; Col. 17, Lines 11-14, shared memory queues use a “ring buffer” with storage for a static number of data items. As data items are produced, they are written at a “tail” location within the ring buffer and the tail pointer is advanced to the next slot in the ring buffer).
Regarding claim 15, Griffin in view of Bonola teaches the method of claim 14. Griffin teaches the method comprising wherein the DL queue region provides pointers to indicate a memory address of the data to be transmitted upon generation of the IPI (Figs. 4A and 4B, Head and tail pointers on the ring buffer are used to indicate a memory address; Col. 17, Lines 12-16, As data items are produced, they are written at a “tail” location within the ring buffer and the tail pointer is advanced to the next slot in the ring buffer. Similarly, a “head” pointer points to the buffer slot that contains the next item to be dequeued).
Regarding claim 16, Griffin teaches a non-transitory computer-readable medium (Fig. 1B, Cores 3 includes memory 14 and 16 that performs instructions; Col. 7, Lines 59-63, a tile 3 includes a processor 10… The processor 10 includes a program counter 12, an instruction memory 14, a data memory 16) comprising processor-executable instructions cause a first processor of the processors to: determine that data is set for transmission from the first processor to a second processor of the processors (Fig. 1A, First core 3 determines memory access request with write data to transmit data from second core 3; Col. 7, Lines 8-11, Each of the tiles 3 is a functional unit that includes a processor (or “processor core”) and a switch that forwards data from other tiles to the processor and to switches of other tiles over data paths 4); copy the data to at least one memory address of the first processor based on the determination (Fig. 6A, Write data (i.e. copy) to a memory location 56; Col. 23, Lines 39-40, a writer process 52 has acquired a lock 54 and is allowed to write to a memory location 56), wherein the at least one memory address of the first processor is directly mapped with at least one memory address of the second processor (Figs. 6A and 6B, Memory location 56 is a memory address that is mapped to first processor 52 and second processor 58a; Col. 23, Lines 42-44, a reader process 58a has acquired the lock 54 and is allowed to read from the memory location 56); trigger an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 1A, Inter-processor interrupts are transmitted between cores 3 via channels 4 of the on-chip network; Col. 22, Lines 48-50, To send an interrupt, the core performs a store operation to a page that is marked as memory-mapped-IO (MMIO)… Col. 22, Lines 22-24, sending an interrupt or IPI using a special IPI interface implemented in hardware through IPI reflector circuitry in the on-chip network); and transmit to the second processor via the IPI (Fig. 1A, Interrupts are transmitted between cores 3; Col. 21, Lines 51-54, Causing interrupts or notifications on a remote core includes mechanisms to notify the remote core (or a process running on the remote core) of an event (e.g., that data has been written into a ring buffer)… Col. 22, Lines 52-55, reflector forwards the interrupt message to the target core. Once the message reaches the target core, an appropriate interrupt is signaled on the target core).
Griffin does not teach the medium comprising: in response to the copying of the data, trigger an inter-processor interrupt (IPI) over at least one channel of the second processor; and transmit the data to the second processor via the IPI.
Bonola teaches the medium comprising: in response to the copying of the data (Fig. 11A, Core 1102 (i.e. first processor) writes data into IMR register 1108 (i.e. copying the data); Paragraph 0044, first core 1102 configures an internal LAPIC 1103 to automatically generate IPIs by writing a description of the memory region 1104 containing a FIFO queue 1106 into an IMR register 1108), trigger an inter-processor interrupt (IPI) over at least one channel of the second processor (Fig. 11A, Interrupt is triggered in response to writing to the register 1108; Paragraph 0044, By writing this information into the IMR 1108, the first core directs the LAPIC to generate and transmit a specified type of IPI to one or more specified target cores); and transmit the data to the second processor via the IPI (Fig. 11B, Interrupt is transmitted from first core 1102 to second core 1120 via channel 1106, which in response causes transmission of data between 1102 and 1120 via FIFO 1106; Paragraph 0045, FIG. 11B, the first core 1102 places an entry 1110… placing the entry into the queue involves a WRITE operation to the shared-memory region specified in an IMR, the LAPIC 1116 of the first core 1102 automatically generates an interrupt that is transmitted to the LAPIC 1118 of the second core 1120. Upon receiving the interrupt, the second core then calls an appropriate interrupt handler for retrieving information from the FIFO queue).
Griffin and Bonola are analogous arts because they are in the same field of endeavor of using inter-processor interrupts between cores to facilitate data transfer between cores.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin’s medium to incorporate the teachings of Bonola and enable the inter-processor interrupt of Griffin to be triggered via copying the data and transfer the data using the inter-processor interrupt.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an efficient and easily-applied inter-core communication mechanism via interrupt notifications, thus increasing throughput in a multi-core system (See Bonola: Paragraphs 0004 and 0040).
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Griffin (US 10,095,543) in view of Bonola (US 2011/0047310) and further in view of Lai (US 2001/0032287)
Regarding claim 2, Griffin in view of Bonola teaches the system of claim 1. Griffin teaches the system comprising wherein the memory comprises processor-executable instructions, which on execution, cause the first processor to receive an acknowledgement in a form of an interrupt over the at least one channel of the second processor, once the second processor receives the data from the first processor (Fig. 14, Write Acks/IPI interrupts sent from first core to second core in 172; Col. 37, Lines 61-67, The writes by the user process into the context registers of a corresponding function-specific engine are able to use a standard store operation at the requesting processor core… Col. 38, Lines 38-40, mechanism has the function-specific engine notify the user process of completion of the operation via an interprocessor interrupt).
Neither Griffin nor Bonola teaches the system comprising an acknowledgement in a form of a Message Signalled interrupt.
Lai teaches the system comprising an acknowledgement in a form of a Message Signalled interrupt (Fig. 2, MSI Ack in MSI controller 210; Paragraph 0030, MSI detector 220 then outputs the message signaled interrupt acknowledging (MSI_ACK) signal to notice the MSI calculator 230 that the data to be processed).
Griffin, Bonola, and Lai are analogous arts because they are in the same field of endeavor of using interrupt signaling for notifications.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin/Bonola’s system to incorporate the teachings of Lai and use a message signaled interrupt (MSI) to signal an acknowledgement.
One of ordinary skill in the art would be motivated to make the modifications in order to create compatibility with the well-known and commonly used PCI protocol which use MSI’s, thus increasing the number of message types that can be sent over a high-speed serial protocol (See Lai: Paragraphs 0012-0014).
Regarding claim 10, Griffin in view of Bonola teaches the method of claim 9. Griffin teaches the method comprising receiving, by the first processor, an acknowledgement in a form of an interrupt over the at least one channel of the second processor, once the second processor receives the data from the first processor (Fig. 14, Write Acks/IPI interrupts sent from first core to second core in 172; Col. 37, Lines 61-67, The writes by the user process into the context registers of a corresponding function-specific engine are able to use a standard store operation at the requesting processor core… Col. 38, Lines 38-40, mechanism has the function-specific engine notify the user process of completion of the operation via an interprocessor interrupt).
Neither Griffin nor Bonola teaches the method comprising an acknowledgement in a form of a Message Signalled interrupt.
Lai teaches the method comprising an acknowledgement in a form of a Message Signalled interrupt (Fig. 2, MSI Ack in MSI controller 210; Paragraph 0030, MSI detector 220 then outputs the message signaled interrupt acknowledging (MSI_ACK) signal to notice the MSI calculator 230 that the data to be processed).
Griffin, Bonola, and Lai are analogous arts because they are in the same field of endeavor of using interrupt signaling for notifications.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin/Bonola’s method to incorporate the teachings of Lai and use a message signaled interrupt (MSI) to signal an acknowledgement.
One of ordinary skill in the art would be motivated to make the modifications in order to create compatibility with the well-known and commonly used PCI protocol which use MSI’s, thus increasing the number of message types that can be sent over a high-speed serial protocol (See Lai: Paragraphs 0012-0014).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Griffin (US 10,095,543) in view of Bonola (US 2011/0047310) and further in view of Steinmetz (US 2022/0334740).
Regarding claim 5, Griffin in view of Bonola teaches the system of claim 1. Neither Griffin nor Bonola teaches the system comprising wherein the at least one memory address of the first processor corresponds to a Double Data Rate (DDR) region, and wherein the at least one memory address of the second processor corresponds to a Peripheral Component Interconnect Express (PCIe) Base Address Register (BAR) 0.
Steinmetz teaches the system comprising wherein the at least one memory address of the first processor corresponds to a Double Data Rate (DDR) region (Fig. 2, Volatile memory device 210 with PMR address region 212 is a double data rate region; Paragraph 0017, the PMR can be implemented as a power protected region on a volatile memory device of the memory sub-system. Here, the volatile memory device can include a Dynamic Random-Access Memory (DRAM) device. More specifically, the DRAM device can be a Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) device), and wherein the at least one memory address of the second processor corresponds to a Peripheral Component Interconnect Express (PCIe) Base Address Register (BAR) 0 (Fig. 2, Non-volatile memory device 220 with PMR address region 222 uses base address register space of PCIe which is mapped to the first PMR region 212; Paragraph 0017, PMR can be implemented on a native non-volatile memory device, such as magnetic RAM (MRAM) or other similar non-volatile memory device. More specifically, the PMR can be a byte-addressable memory region accessible through a base address register (BAR)).
Griffin, Bonola, and Steinmetz are analogous arts because they are in the same field of endeavor of mapping memory regions of different devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin/Bonola’s system to incorporate the teachings of Steinmetz and include a DDR memory in the first processor of Griffin and a PCIe BAR 0 memory in the second processor of Griffin.
One of ordinary skill in the art would be motivated to make the modifications in order to create larger exposed memory regions using the same physical footprint while implementing transaction transparency using low cost, low power, and high-speed serial solutions such as PCIe and DDR (See Steinmetz: Paragraphs 0018 and 0023).
Regarding claim 13, Griffin in view of Bonola teaches the method of claim 9. Neither Griffin nor Bonola teaches the method comprising wherein the at least one memory address of the first processor corresponds to a Double Data Rate (DDR) region, and wherein the at least one memory address of the second processor corresponds to a Peripheral Component Interconnect Express (PCIe) Base Address Register (BAR) 0.
Steinmetz teaches the method comprising wherein the at least one memory address of the first processor corresponds to a Double Data Rate (DDR) region (Fig. 2, Volatile memory device 210 with PMR address region 212 is a double data rate region; Paragraph 0017, the PMR can be implemented as a power protected region on a volatile memory device of the memory sub-system. Here, the volatile memory device can include a Dynamic Random-Access Memory (DRAM) device. More specifically, the DRAM device can be a Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) device), and wherein the at least one memory address of the second processor corresponds to a Peripheral Component Interconnect Express (PCIe) Base Address Register (BAR) 0 (Fig. 2, Non-volatile memory device 220 with PMR address region 222 uses base address register space of PCIe which is mapped to the first PMR region 212; Paragraph 0017, PMR can be implemented on a native non-volatile memory device, such as magnetic RAM (MRAM) or other similar non-volatile memory device. More specifically, the PMR can be a byte-addressable memory region accessible through a base address register (BAR)).
Griffin, Bonola, and Steinmetz are analogous arts because they are in the same field of endeavor of mapping memory regions of different devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin/Bonola’s method to incorporate the teachings of Steinmetz and include a DDR memory in the first processor of Griffin and a PCIe BAR 0 memory in the second processor of Griffin.
One of ordinary skill in the art would be motivated to make the modifications in order to create larger exposed memory regions using the same physical footprint while implementing transaction transparency using low cost, low power, and high-speed serial solutions such as PCIe and DDR (See Steinmetz: Paragraphs 0018 and 0023).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Griffin (US 10,095,543) in view of Bonola (US 2011/0047310) and further in view of Kranski (US 2022/0318678).
Regarding claim 8, Griffin in view of Bonola teaches the system of claim 1. Neither Griffin nor Bonola teaches the system comprising wherein the first processor is a Layer 2/Layer 3 (L2/L3) NXP processor, and the second processor is a Layer 1 (L1) processor.
Kranski teaches the system comprising wherein the first processor is a Layer 2/Layer 3 (L2/L3) NXP processor, and the second processor is a Layer 1 (L1) processor (Fig. 2A, Multi-layered processors include layers 1-3; Paragraph 0038, special-purpose chipsets can take a variety of forms, including… NXP's S32V234 and S32 chips… Paragraph 0040, the ML subsystem 114 may include three layers of encoder models, with the layer-1 encoder models receiving inputs from sensors and providing output to layer-2 encoder models).
Griffin, Bonola, and Kranski are analogous arts because they are in the same field of endeavor of implementing multi-processor systems.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Griffin/Bonola’s system to incorporate the teachings of Kranski and include layer 1-3 NXP processors to the processor system of Griffin
One of ordinary skill in the art would be motivated to make the modifications in order to implement complex machine learning models for artificial intelligence, robotics, industrial processes, etc. (See Kranski: Paragraphs 0002 and 0003).
Allowable Subject Matter
Claims 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the Claim Objections are overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2019/0034107 to Kim discloses processor cores that use a shared memory to transfer data between processors.
US PGPUB 2017/0109082 to Govindaraju discloses a copy processor and copy manager for performing data transfer in a multi-processor system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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