DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because:
Contains more than 150 words.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DC-DC Converter with Auxiliary Regulation Branch.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 8, 10, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al NPL: (1 MHz 48–12 V Regulated DCX With Single Transformer); (hereinafter Liu et al).
Regarding claim 1, Liu et al [e.g., Figs. 3(c) and 14] discloses a voltage regulation circuit [e.g., RDCX converter with auxiliary DC-DC converter], comprising an input-output branch [e.g., RDCX stage (top branch)] and a regulation branch [e.g., auxiliary PWM DC - DC stage (bottom branch)], wherein the regulation branch comprises: a signal processor [e.g., Driver Integrated PWM IC], a rectification circuit [e.g., rectification switches SR3 and SR4], and a voltage regulator [e.g., PWM Buck converter], wherein the input-output branch outputs a direct-current voltage by controlling a switching frequency [e.g., RDCX stage outputs Vout base on controlled switching frequency via signals VgQ1 – VgQ4, Section IV. Experimental Verification recites “The duty cycle of each switch in DCX is fixed 0.42, and it is an empirical value to achieve ZVS operation with a fine efficiency. SRs are applied to reduce the conduction loss. And, the driving signals of these SRs are synchronized to the primary driving signals.”], and the regulation branch controls the direct-current voltage to be constant by adjusting a target input voltage of the input-output branch [e.g., -- refer to equation (1) --, auxiliary PWM buck converter controls voltage Vc to maintain regulated output voltage Vo, B. Voltage Regulating and Power Distribution section recites “When the duty cycle of the auxiliary PWM converter is adjusted, VC changes correspondingly. Thus, VDCX can be adjusted, and Vo is regulated.”]; the rectification circuit is connected to the voltage regulator [e.g., switches SR3 and SR4 connected to PWM Buck converter], an output voltage of the voltage regulator is a regulated voltage output by the regulation branch [e.g., output voltage Vc of PWM DC-DC converter is a regulated voltage of VA], and the regulated voltage and a previous-stage input voltage of the voltage regulation circuit are used as the target input voltage [e.g., voltage Vc and Vin used as input voltage to generate desired Vo, -- refer to equations (1) --, B. Voltage Regulating and Power Distribution recites “The second one, Pdc−dc, is the power dealt by the auxiliary dc–dc stage to make the output voltage regulated. Since VC and Vin are series connected, the power distribution in the RDCX converter is determined by the voltage relationship between VC and Vin.”]; and the signal processor is connected to the rectification circuit [e.g., Driver Integrated PWMIC connected to SR3 and SR4], and the signal processor is configured to output a first switching signal to the rectification circuit to control the regulated voltage [e.g., signal controlling SR3 and SR4 (VgSR3 – VgSR4) controlling Vc].
Regarding claim 2, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the voltage regulator [e.g., auxiliary PWM DC - DC stage (bottom branch)] comprises an energy storage inductor [e.g., inductor L] and an output filtering capacitor [e.g., capacitor C1], wherein a high-level output end of the rectification circuit is connected to one end of the energy storage inductor [e.g., top “positive” rail connected to switches SR3 and SR4 and connected to inductor L], the other end of the energy storage inductor is connected to one end of the output filtering capacitor [e.g., second end of inductor L connected capacitor C1], the other end of the output filtering capacitor is connected to a low-level output end of the rectification circuit [e.g., bottom “negative” rail connected to switches SR3 and SR4 connected to second end of capacitor C1], and a voltage across two ends of the output filtering capacitor is the output voltage of the voltage regulator [e.g., output voltage Vc].
Regarding claim 3, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the rectification circuit is a controllable rectification circuit [e.g., controllable switches SR3 and SR4], and the controllable rectification circuit comprises one or more controllable elements [e.g., switches SR3 and SR4], wherein when the controllable rectification circuit comprises a plurality of controllable elements [e.g., controllable switches SR3 and SR4], the signal processor is configured to output the first switching signal to all or part of the plurality of controllable elements [e.g., signals VgSR3 – VgSR4].
Regarding claim 4, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the one or more controllable elements form a bridge rectification circuit [e.g., half-bridge formed between SR3 and SR4], wherein one output end of the bridge rectification circuit as the high-level output end of the rectification circuit and is connected to the energy storage inductor [e.g., top “positive” rail connected to switch SR3 and connected to inductor L], and the other output end of the bridge rectification circuit as the low-level output end of the rectification circuit and is connected to the output filtering capacitor [e.g., bottom “negative” rail connected to switch SR4 and connected to capacitor C1].
Regarding claim 8, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the input- output branch is a logical link control (LLC) circuit topology [e.g., DCX converter comprising an LLC circuit, section II. PRINCIPLE OF OPERATION AND VOLTAGE REGULATION paragraph A. Operating Principle at Steady Stage recites “As shown in Fig. 3(c), the proposed RDCX converter consists of two parts. The LLC converter, with fixed switching frequency and duty cycle, works as a DCX stage. The auxiliary PWM dc–dc stage controlled by the feedback loop is utilized to keep the output voltage regulated.”], and the regulation branch is a BUCK circuit topology [e.g., auxiliary dc – dc stage comprising a PWM BUCK converter]; the LLC circuit topology comprises a primary-side primary winding circuit and a secondary-side secondary winding circuit [e.g., transformer with primary side (P) and secondary side (S)], the LLC circuit topology operates in a direct- current mode of MHz [e.g., operates at 1MHz to generate Vout] and transfers electric energy from the primary-side primary winding circuit to the secondary-side secondary winding circuit to output the direct- current voltage [e.g., B. Voltage Regulating and Power Distribution recites “As displayed in Fig.6, the power handled by the DCX stage, PDCX, can be divided into two parts. The first one, Po, is the power delivered to load directly. The second one, Pdc−dc, is the power dealt by the auxiliary dc–dc stage to make the output voltage regulated.”]; the BUCK circuit topology comprises an energy storage inductor and an output filtering capacitor [e.g., inductor L and output capacitor C1], and the rectification circuit is connected between a primary-side auxiliary winding and the BUCK circuit topology [e.g., switches SR3 and SR4 connected between primary auxiliary winding Sa and PWM Buck converter].
Regarding claim 10, Liu et al [e.g., Figs. 3(c) and 14] discloses a server power supply [e.g., power supply for telecom infrastructure, section I. INTRODUCTION recites “In the telecom infrastructure, intermediate bus converters (IBCs) are employed in the intermediate bus architecture (IBA), which is widely applied for the power supply”], comprising: a power supply circuit [e.g., -- refer to Fig. 14 --, input voltage Vin] and a voltage regulation circuit [e.g., RDCX converter], wherein the voltage regulation circuit is connected between the power supply circuit and a server load to be powered [e.g., RDCX converter connected between input voltage and load]; the voltage regulation circuit comprises an input-output branch [e.g., DCX stage (top branch)] and a regulation branch [e.g., auxiliary dc – dc stage (bottom branch)], wherein the regulation branch comprises a signal processor [e.g., Driver Integrated PWMIC], a rectification circuit [e.g., switches SR3 and SR4], and a voltage regulator [e.g., PWM Buck converter]; the input-output branch outputs a direct-current voltage to the server load by controlling a switching frequency [e.g., generates output voltage Vo, Section IV. Experimental Verification recites “The duty cycle of each switch in DCX is fixed 0.42, and it is an empirical value to achieve ZVS operation with a fine efficiency. SRs are applied to reduce the conduction loss. And, the driving signals of these SRs are synchronized to the primary driving signals.”], the regulation branch controls the direct- current voltage to be constant by adjusting a target input voltage of the input-output branch [e.g., -- refer to equation (1) --, auxiliary PWM buck converter controls voltage Vc to maintain regulated output voltage Vo, B. Voltage Regulating and Power Distribution section recites “In accordance with (3), since N and M are constant in a real transformer, GRDCX is determined by the value of f(D).When the duty cycle of the auxiliary PWM converter is adjusted, VC changes correspondingly. Thus, VDCX can be adjusted, and Vo is regulated.”]; the rectification circuit is connected to the voltage regulator [e.g., switches SR3 and SR4 connected to PWM Buck converter], an output voltage of the voltage regulator is a regulated voltage output by the regulation branch [e.g., voltage Vc is a regulated voltage of VA], the regulated voltage and an output voltage of the power supply circuit are used as the target input voltage [e.g., voltage Vc and Vin used as target input voltage to generate desired Vo, -- refer to equations (1) -- ]; the signal processor is connected to the rectification circuit [e.g., Driver Integrated PWMIC connected to SR3 and SR4], and the signal processor is configured to output a first switching signal to the rectification circuit to control the regulated voltage [e.g., signal controlling SR3 and SR4 (VgSR3 – VgSR4)].
Regarding claim 14, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the input- output branch is a logical link control (LLC) circuit topology [e.g., DCX converter comprising a LLC circuit, section II. PRINCIPLE OF OPERATION AND VOLTAGE REGULATION paragraph A. Operating Principle at Steady Stage recites “As shown in Fig. 3(c), the proposed RDCX converter consists of two parts. The LLC converter, with fixed switching frequency and duty cycle, works as a DCX stage. The auxiliary PWM dc–dc stage controlled by the feedback loop is utilized to keep the output voltage regulated.”], and the regulation branch is a BUCK circuit topology [e.g., auxiliary dc – dc stage comprising a PWM BUCK converter]; the LLC circuit topology comprises a primary-side primary winding circuit and a secondary-side secondary winding circuit [e.g., transformer with primary side (P) and secondary side (S)], the LLC circuit topology operates in a direct- current mode of MHz [e.g., operates at 1MHz to generate Vout] to transfer electric energy from the primary-side primary winding circuit to the secondary-side secondary winding circuit, to output a constant direct-current voltage to the server load [e.g., control signal supplied to switches generated according to Vin and Vo, Section B. Voltage Regulating and Power Distribution recites “According to (4), the power distribution is only determined by Vin and Vo. At a certain input voltage and output voltage, the ratio of circulating power to the load power is fixed, whether in light or heavy load condition. As (4) presented, when Po is constant, larger KRDCX means higher Pdc−dc and more loss. When Vo is constant, larger Vin means smaller KRDCX.”]; the BUCK circuit topology comprises an energy storage inductor and an output filtering capacitor [e.g., inductor L and output capacitor C1], and the rectification circuit is connected between a primary-side auxiliary winding and the BUCK circuit topology [e.g., switches SR3 and SR4 connected between primary auxiliary winding Sa and PWM Buck converter].
Regarding claim 16, Liu et al [e.g., Figs. 3(c) and 14] discloses a voltage regulation method [e.g., method of controlling RDCX converter], comprising: generating a first switching signal [e.g., generates regulated switching signals for auxiliary PWM DC-DC converter for voltage regulation] according to a previous-stage input voltage of a voltage regulation circuit [e.g., according to Vin] and a second switching signal of a rectification circuit in the voltage regulation circuit [e.g., normal switching signal supplied to SR3 and SR4, Section IV. Experimental Verification recites “The duty cycle of each switch in DCX is fixed 0.42, and it is an empirical value to achieve ZVS operation with a fine efficiency. SRs are applied to reduce the conduction loss. And, the driving signals of these SRs are synchronized to the primary driving signals.”], wherein the voltage regulation circuit comprises: an input- output branch and [e.g., DCX converter (top branch)] a regulation branch [e.g., auxiliary circuit (bottom branch)], the regulation branch comprises: the rectification circuit and a voltage regulator [e.g., rectification switches SR3 and SR4 and PWM DC-DC (Buck) Converter], wherein the input-output branch outputs a direct-current voltage by controlling a switching frequency [e.g., output Vout with fixed switching frequency f(D). Section II. Paragraph A recites “As shown in Fig. 3(c), the proposed RDCX converter consists of two parts. The LLC converter, with fixed switching frequency and duty cycle, works as a DCX stage. The auxiliary PWM dc–dc stage controlled by the feedback loop is utilized to keep the output voltage regulated.”], and the regulation branch controls the direct-current voltage to be constant by adjusting a target input voltage of the input- output branch [e.g., regulation circuit adjust voltage Vc to maintain regulated Vout, B. Voltage Regulating and Power Distribution recites “In accordance with (3), since N and M are constant in a real transformer, GRDCX is determined by the value of f(D). When the duty cycle of the auxiliary PWM converter is adjusted, VC changes correspondingly. Thus, VDCX can be adjusted, and Vo is regulated”], the rectification circuit is connected to the voltage regulator [e.g., rectification switches SR3 and SR4 connected to PWM Dc-Dc converter], an output voltage of the voltage regulator is a regulated voltage [e.g., voltage Vc is a regulated voltage from VA], the regulated voltage and the previous-stage input voltage are used as the target input voltage [e.g., input voltage Vin and voltage Vc used as target voltage for desired Vout, -- refer to equations (1) -- ], the second switching signal is used for rectifying an input voltage of the regulation branch [e.g., normal switching signal synchronized with primary driving signals used to regulate input voltage VA]; and outputting the first switching signal to the rectification circuit, wherein the first switching signal is used for controlling the regulated voltage [e.g., regulated switching signals for auxiliary PWM DC-DC converter for voltage regulation, Section II. Paragraph A recites “As shown in Fig. 3(c), the proposed RDCX converter consists of two parts. The LLC converter, with fixed switching frequency and duty cycle, works as a DCX stage. The auxiliary PWM dc–dc stage controlled by the feedback loop is utilized to keep the output voltage regulated.”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable in view of Liu et al NPL: (1 MHz 48–12 V Regulated DCX With Single Transformer) over Xue et al NPL: A 98.3% Efficient GaN Isolated Bidirectional DC–DC Converter for DC Microgrid Energy Storage System Applications; (hereinafter Liu et al and Xue et al).
Regarding claim 5, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the one or more controllable elements comprise a first controllable switch transistor [e.g., SR3], a second controllable switch transistor [e.g., SR4], …, and the signal processor is respectively connected to a control end of the first controllable switch transistor [e.g., Driver providing signal VgSR3], a control end of the second controllable switch transistor [e.g., Driver providing signal VgSR4].
Liu et al does not disclose a third controllable switch transistor, and a fourth controllable switch transistor, which together form a full-bridge rectification circuit; and the signal processor is respectively connected to a control end of the third controllable switch transistor, and a control end of the fourth controllable switch transistor.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Liu et al a third controllable switch transistor, and a fourth controllable switch transistor, which together form a full-bridge rectification circuit; and the signal processor is respectively connected to a control end of the third controllable switch transistor, and a control end of the fourth controllable switch transistor to replace the center tapped rectifier with a full-bridge rectifier to achieve full wave rectification without design drawback of a center tapped DAB converter. As suggested by Xue et al, center tapped DAB converter offer greater efficiency at a cost of less effective transformer usage and doubled secondary switch voltage stress [e.g., B. Conventional DAB Topology Issues recites “Comparing to a conventional DAB converter, although there are drawbacks such as ineffective transformer usage and doubled secondary switch voltage stress, the merits of the center-tap circuit are simple structure, low cost, and high efficiency”.]. Furthermore, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious.
Regarding claim 11, Liu et al [e.g., Figs. 3(c) and 14] discloses wherein the voltage regulator [e.g., auxiliary dc - dc stage] comprises an energy storage inductor [e.g., inductor L] and an output filtering capacitor [e.g., capacitor C1], the rectification circuit is a controllable rectification circuit [e.g., controllable switches SR3 – SR4], one or more controllable elements comprised in the controllable rectification circuit form a bridge rectification circuit [e.g., controllable switches SR3 – SR4]; a high-level output end of the bridge rectification circuit is connected to one end of the energy storage inductor [e.g., one end of inductor L connected to high end switch SR3], the other end of the energy storage inductor is connected to one end of the output filtering capacitor [e.g., second end of inductor L connected capacitor C1], the other end of the output filtering capacitor is connected to a low-level output end of the bridge rectification circuit [e.g., bottom end of capacitor C1 connected to low-level output via switch SR4], a voltage across two ends of the output filtering capacitor is the output voltage of the voltage regulator [e.g., output voltage Vc]; the one or more controllable elements comprise a first controllable switch transistor, a second controllable switch transistor [e.g., switches SR3 and SR4], …; and the signal processor is respectively connected to control ends of the one or more controllable elements [e.g., signals VgSR3 – VgSR4].
Liu et al does not disclose a third controllable switch transistor, and a fourth controllable switch transistor, which together form a full-bridge rectification circuit.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Liu et al with a third controllable switch transistor, and a fourth controllable switch transistor, which together form a full-bridge rectification circuit to replace the center tapped rectifier with a full-bridge rectifier to achieve full wave rectification without design drawback of a center tapped DAB converter. As suggested by Xue et al, center tapped DAB converter offer greater efficiency at a cost of less effective transformer usage and doubled secondary switch voltage stress [e.g., B. Conventional DAB Topology Issues recites “Comparing to a conventional DAB converter, although there are drawbacks such as ineffective transformer usage and doubled secondary switch voltage stress, the merits of the center-tap circuit are simple structure, low cost, and high efficiency”.]. Furthermore, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable in view of Liu et al NPL: (1 MHz 48–12 V Regulated DCX With Single Transformer) over Wahledow (US Pub. No. 2016/0268888 A1); (hereinafter Liu et al and Wahledow).
Regarding claim 21, Liu et al discloses the claimed invention except a non-volatile readable storage medium, storing a computer program, wherein the computer program, when executed by a processor, implements the operations of the method according to claim 16.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Liu et al with a non-volatile readable storage medium, storing a computer program, wherein the computer program, when executed by a processor, implements the operations of the method according to claim 16 since it is not uncommon to digitally control a power converter as discloses by Wahledow [e.g., p. 0002 – 0005 recites “The arrival of digitally controlled and configurable power converters has open up a vast amount of operating states and fault handling possibilities. If such a power converter shuts down, for any reason, it is virtually impossible to know the cause thereof, unless a hardware component was broken. Existing solutions use schemes rely on an external host, which store status data on a storage medium such as a flash memory in response to a shut down, by aid of which the reason for the shut down may be found. To constantly store status data on the flash memory is not an option, since this would wear out the flash memory in a short time, since a flash memory has a limited number of write cycles, e.g. typically around 20 000 write cycles. Another solution is to use hold-up capacitors to keep the power up during storage of the status data, but those are space demanding and expensive and may not be an option in many applications. It is common that microcontrollers are provided with an in-built feature referred to as “brown out” feature, allowing some actions to be performed before the microcontroller is reset due to low voltage supply. However, the time available will typically be too short to store status data on the flash memory, such that the cause to the shut down can be found by aid of the status data.”].
Examiner’s Note
Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Allowable Subject Matter
Claims 6 - 7, 9, 12 - 13, 15 and 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, the signal processor is configured to convert a second switching signal of the rectification circuit into the first switching signal by using the control signal, wherein the second switching signal is used for rectifying an input voltage of the regulation branch.”
The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, wherein the signal processor is configured to perform an AND logical operation on a switching signal of the rectification circuit and a switching signal of the BUCK circuit topology to obtain the first switching signal and input the first switching signal to the rectification circuit; wherein the switching signal of the rectification circuit is used for controlling a rectification function of the rectification circuit, and the switching signal of the BUCK circuit topology is used for controlling a step-down function of the BUCK circuit topology.”
The primary reason for the indication of the allowability of claim 12 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, the signal processor is configured to convert a second switching signal of the rectification circuit into the first switching signal by using the control signal, and the signal processor is configured to input the first switching signal to the rectification circuit, wherein the second switching signal is used for rectifying an input voltage of the regulation branch.”
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, wherein the signal processor is configured to perform an AND logical operation on a switching signal of the rectification circuit and a switching signal of the BUCK circuit topology to obtain the first switching signal and input the first switching signal to the rectification circuit; wherein the switching signal of the rectification circuit is used for controlling a rectification function of the rectification circuit, and the switching signal of the BUCK circuit topology is used for controlling a step-down function of the BUCK circuit topology.”
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… and using the control signal to convert the second switching signal of the rectification circuit into the first switching signal.”.
Conclusion
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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