DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 7, 9, 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PG. Pub. 2021/0111105) in view of Lu et al. (US PG. Pub. 2021/0398875).
Regarding claim 1 – Kim teaches an electrical power switch (figs. 1A-2) comprising: a pair of half bridges (12 & 14 [paragraph 0031] Kim states, “semiconductor dies 12, 14 may form more than one power stage, such as a half bridge”); power terminals (31 & 36 [paragraph 0046] Kim states, “voltage input pin 31…power supply pin 36”) for coupling a power source to the half bridges (12 & 14; see fig. 2); a power phase output terminal (38 [paragraph 0046] Kim states, “switching node pin 38”; pin 38 shown connected to component 52) for connecting a load (52 [paragraph 0054] Kim states, “a power drain 52, such as inductor or transformer”) to the half bridges (12 & 14); a printed circuit board (PCB) controller (60 [paragraph 0057] Kim states, “flexible circuit 60”) having control circuitry (16 [paragraph 0058] Kim states, “Control die 16 is configured to control switching of the high-side FET and the low-side FET of semiconductor dies 12, 14”) operable to turn ON and turn OFF the half bridges (12 & 14) to respectively connect and disconnect the load (52) to the power source (31); control terminals (34 & 35 [paragraph 0058] Kim states, “high-side gate driver control input pin 34 and low-side gate driver control input pin 35”) for connecting the control circuitry (16) on the PCB (60) to circuitry external to the power switch (see control terminals 34 & 35 that are shown to extend outside of the electrical power switch); wherein the half bridges (12 & 14), PCB (60), control terminals (34 & 35), power terminals (31 & 36), and power phase output terminal (38) are encapsulated in a same encapsulation envelope (fig. 1B-1C, 80 [paragraph 0026] Kim states, “package 10 showing mold compound 80 and a protruding set of pin terminals 30”) having a planar first face surface (upper surface shown in figure 1C) and at least one edge surface (surface that extends in the vertical direction); wherein all of the terminals (34, 35, 31, 36 & 38) have electrical contact surfaces that are exposed on and only on the first surface (upper surface shown in figure 1C) and all of the at least one edge surface are bare of electrical contact surfaces and terminal pins (claimed structure shown in figures 1A-2).
Kim does not explicitly teach a pair of substantially parallel half bridges.
Lu teaches an electrical power switch (figs. 7-9 & 16, 100 [paragraph 0080] Lu states, “power module 100”) comprising: a pair of substantially parallel half bridges (130 & 132 [paragraph 0084] Lu states, “There are a plurality of GaN HEMT switching devices, comprising HSS 130 and LSS 132. interconnected in parallel in a half-bridge configuration”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having a pair of half bridges as taught by Kim with the pair of half bridges being a pair of substantially parallel half bridges as taught by Lu because Lu states regarding this structure, “power module comprising paralleled GaN switches, which could be sized to retrofit existing systems, meeting current creepage and clearance standards, while providing improved performance, particularly with respect to reduced gate loop inductance and improved balancing of power commutation loop inductances” [paragraph 0101].
Regarding claim 2 – Kim in view of Lu teach the electrical power switch according to claim 1, but fail to teach wherein the contact surfaces of the power terminals and power phase output terminal are substantially flush with the first face surface.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the terminals being substantially flush with the first face surface, since it has been held that the provision of adjustability, where needed, involves routine skill in the art . In re Stevens, 101 USPQ 284 (CCPA 1954). Please note that in the instant application, paragraph 0016, applicant has not disclosed any criticality for the claimed limitations. Having the terminals being flush with the first face surface of the encapsulation envelope will reduce the thickness of the electrical power switch and will be desirable in thin applications.
Regarding claim 3 – Kim in view of Lu teach the electrical power switch according to claim 1 wherein an electrical contact surface of the power terminals (Kim; fig. 1C, 31 & 36) and/or the power phase output terminal (38) is raised or recessed relative to the plane of the first face surface (figure 1C shows the terminals 31, 36 & 38 being above the first face surface of the encapsulation envelope 80).
Regarding claim 5 – Lu in view of Wei teach the electrical power switch according to claim 4 wherein an electrical contact surface (Lu; fig. 1C, top surface of terminals 34 & 35) of a control terminal of the control terminals (34 & 35) is raised or recessed relative to the plane of the first face surface (claimed structure shown in figure 1C).
Regarding claim 7 – Kim in view of Lu teach the electrical power switch according to claim 1 wherein the encapsulation envelope (Kim ; fig. 1C, 80) is a rectangular parallelepiped that encapsulates all the components of the switch (figure 1C shows the claimed structure).
Regarding claim 9 – Kim in view of Lu teach the electrical power switch according to claim 1 and comprising a second face surface (Kim; figs. 1A-1C, 22) opposite the first face surface (top surface of encapsulation envelope 80) and having formed thereon a conductive thermal interface (25 [paragraph 0040] Kim states, “backside copper layer 25”).
Regarding claim 10 – Kim in view of Lu teach the electrical power switch according to claim 1 wherein when the switch is turned ON (Lu; figure 16 shows current flow in the pair of substantially parallel half bridges 130 & 132) current flows to the power phase output terminal parallel to a same direction in each half bridge (figure 16 shows the current of each half bridge going in a parallel direction to Vout).
Regarding claim 12 – Kim in view of Lu teach a power pack array comprising a plurality of electrical power switches according to claim 1 butted up against each other (Lu; [paragraph 0025 & 0021] Lu states, “For a half-bridge topology, the first and second rows of device mounting positions allow for multiple power switching devices to be interconnected in parallel…For high current applications, multiple GaN HEMTs may be connected in parallel for each switch position”).
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Lu et al. as applied to claim 1 above, and further in view of Wei et al. (US PG. Pub. 2022/0130768).
Regarding claim 2 – Kim in view of Lu teach the electrical power switch according to claim 1, having contact surfaces of the power terminals and power phase output terminals (discussed in the rejection of claim 1 above) but fail to teach wherein the contact surfaces of the terminals are substantially flush with the first face surface.
Wei teaches wherein the contact surfaces of the terminals (fig. 2, 123 [paragraph 0039] Wei states, “topside I/O interface 121, 122, 123, 124, 125”) are substantially flush with the first face surface ([paragraph 0015] Wei states, “a leadless package having a substantially planar topside surface with which the terminals or contact pads of the topside I/O interface are generally coplanar or flush”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having contact surfaces of the power terminals and power phase output terminals within an encapsulation envelope as taught by Kim in view of Lu with the control terminals being substantially flush with the first face surface of the encapsulation envelope as taught by Wei because having the terminals being flush with the first face surface of the encapsulation envelope will reduce the thickness of the electrical power switch and will be desirable in thin applications.
Regarding claim 4 – Kim in view of Lu teach the electrical power switch according to claim 1, but fail to explicitly teach wherein the contact surfaces of the control terminals are substantially flush with the first face surface.
Wei teaches wherein the contact surfaces of the control terminals (fig. 2, 123 [paragraph 0039] Wei states, “topside I/O interface 121, 122, 123, 124, 125”) are substantially flush with the first face surface ([paragraph 0015] Wei states, “a leadless package having a substantially planar topside surface with which the terminals or contact pads of the topside I/O interface are generally coplanar or flush”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having a control terminal within an encapsulation envelope as taught by Kim in view of Lu with the control terminals being substantially flush with the first face surface of the encapsulation envelope as taught by Wei because having the terminals being flush with the first face surface of the encapsulation envelope will reduce the thickness of the electrical power switch and will be desirable in thin applications.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Lu et al. as applied to claim 1 above, and further in view of Macheiner et al. (US PG. Pub. 2018/0277513).
Regarding claim 6 – Kim in view of Lu teach the electrical power switch according to claim 1 but fails to teach wherein the contact surface and the control terminal to which the surface belongs are configured to be coupled to an electrical conductor by soldering, ultrasonic or laser welding, or press fitting or screwing the conductor into a hole in the control terminal.
Macheiner teaches wherein the contact surface and the control terminal (fig. 4A, 42 & 44) to which the surface belongs are configured to be coupled to an electrical conductor by soldering ([paragraph 0044] Macheiner states, “Semiconductor die 40A and 40B may be electrically connected to elements 42 and 44 in any suitable manner, such as soldering, diffusion soldering, sintering, gluing, and/or fusion bonding”), ultrasonic or laser welding, or press fitting or screwing the conductor into a hole in the control terminal.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the contact surface and the control terminal to which the surface belong as taught by Kim in view of Lu with the contact surface of the control terminal being soldered to an electrical connector as taught by Macheiner because solder is known to form an effective and efficient electrical/mechanical connection.
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Lu et al. as applied to claim 1 above, and further in view of Martin et al. (KR20210136987).
Regarding claim 11 – Kim in view of Lu teach the electrical power switch according to claim 1 but fails to teach wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.5nH.
Martin teaches wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.5nH ([page 34] Martin sates, “the threshold power switch of the loop 114 shown in FIG. 1B of the power module 100 are 12 (nH) to 2 (nH), 10 (nH) to 2 (nH) and 4 (nH) to 2 (nH)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having ON and OFF states as taught by Kim in view of Lu with the total power loop inductance when transition between ON and OFF is less than about 2.5nH as taught by Martin because Martin states, “All of these advantages allow for lower switching losses, higher switching frequencies, improved controllability and reduced EMI. Ultimately, this helps system designers achieve more power-dense and robust power conversion systems” [page 20].
Regarding claim 20 – Kim in view of Lu teach the electrical power switch according to claim 1 but fails to teach wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.25nH.
Martin teaches wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.25nH ([page 34] Martin sates, “the threshold power switch of the loop 114 shown in FIG. 1B of the power module 100 are 12 (nH) to 2 (nH), 10 (nH) to 2 (nH) and 4 (nH) to 2 (nH)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having ON and OFF states as taught by Kim in view of Lu with the total power loop inductance when transition between ON and OFF is less than about 2.25nH as taught by Martin because Martin states, “All of these advantages allow for lower switching losses, higher switching frequencies, improved controllability and reduced EMI. Ultimately, this helps system designers achieve more power-dense and robust power conversion systems” [page 20].
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al in view of Lu et al. as applied to claim 1 above, and further in view of Azotea et al. (US Patent 6060795).
Regarding claim 21 – Kim in view of Lu teach the electrical power switch according to claim 1 but fails to teach wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.0nH.
Azotea teaches an electrical power switch ([claim 1] Azotea states, “a flat power semiconductor device as a main switch”) wherein having a total power loop inductance when transitioning between ON and OFF states is less than about 2.0nH ([column 8 lines 29-30] Azotea states, “a typical power loop inductance of 1.7nH can be approximately calculated from the stripline structure in Fig. 5”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the electrical power switch having ON and OFF states as taught by Kim in view of Lu with the total power loop inductance when transition between ON and OFF is less than about 2.00nH as taught by Azotea because Azotea states, “module that can operate at higher temperatures and higher frequencies” [column 5 line 21-23]. Reducing the power loop inductance allows for faster response times, higher power density and reduced voltage spikes.
Response to Arguments
Applicant's arguments filed 5/25/2026 have been fully considered but they are not persuasive.
Applicant argues, “all of Lu’s embodiments expressly teach power modules which “to meet creepage and clearance requirements”…and “to provide reduced parasitic inductance in the gate drive loop and in the power communication loop terminals” have terminals located at different heights and as a result, as expressly illustrated in Lu’s figures, are located on different surfaces…Lu explicitly teaches away from a configuration in which parallel half bridges of a power switch are packaged in an encapsulation envelope and all the terminals for the half bridges are exposed on and only on a first planar surface of the encapsulation. On the other hand Kim’s Figs. 1B and 1C show a configuration of Kim’s semiconductor package 10 in which all of the pin terminals that connect to circuitry in the Package are located on a same planar surface of the package” [REMARKS page 5-6].
Examiner disagrees. The secondary reference Lu is only relied upon to teach wherein the half bridges are substantially parallel as the primary reference Kim already teaches half bridges with an encapsulating envelope having a planar first surface with similar structural features to the instant application. Lu states in paragraph 0101, “improved performance, particularly with respect to reduced gate loop inductance and improved balancing of power commutations loop inductances”. These benefits being somewhat related to the overall structure are also related to the parallel half bridge configuration and would be beneficial within the primary reference Kim. Lu also states in paragraph 0021 & 0109, “For high current applications, multiple GaN HEMTs may be connected in parallel for each switch position…and balancing of inductances in the power commutation loops of parallel connected power switching devices, to take advantage of ultra-fast switching capabilities of wide-bandgap semiconductor power switching devices, such as GaN HEMTs”. Which gives further reasoning to have the half bridges arranged in parallel. Given that Kim itself already has half bridges (fig. 1A-1, 12 & 14) it would appear reasonable to form them in a parallel arrangement of Lu as discussed above.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/ Primary Examiner, Art Unit 2847
Prosecution Insights