Prosecution Insights
Last updated: October 25, 2026
Application No. 18/879,461

VIA HOLE STRUCTURE OF CIRCUIT BOARD, AND CIRCUIT BOARD

Non-Final OA §102§103
Filed
Dec 27, 2024
Priority
Jun 30, 2022 — CN 202210769999.0 +1 more
Examiner
MCALLISTER, MICHAEL F
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ZTE Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
534 granted / 622 resolved
+17.9% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
19 currently pending
Career history
634
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.6%
+10.6% vs TC avg
§102
36.4%
-3.6% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings The drawings are objected to because in Fig. 1, 110b has no indication line to referenced structure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 12-14, 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Benham (US 20060118332 hereinafter Benham). In regards to claim 1, Benham discloses;” A via hole structure of a circuit board (paragraphs 0005, 0008), comprising at least one pair of differential signal (Title) holes, wherein each pair of differential signal holes comprises a first differential signal hole and a second differential signal hole (Fig. 3A (shows a differential pair on different layers), paragraph 0029); and in a thickness direction of the circuit board (Fig. 1), there are several distances between a central axis of the first differential signal hole and a central axis of the second differential signal hole, and numerical values of at least two distances are different (Fig. 1 (shown)).” In regards to claim 2, Benham discloses;” The via hole structure according to claim 1, wherein the first differential signal hole comprises at least two first signal aperture segments communicated with each other in the thickness direction of the circuit board, and the second differential signal hole comprises at least two second signal aperture segments communicated with each other in the thickness direction of the circuit board (Fig. 3A (shown) paragraph 0017).” In regards to claim 3, Benham discloses;” The via hole structure according to claim 2, wherein the first signal aperture segments and/or the second signal aperture segments are set in a step shape in the thickness direction of the circuit board (Fig. 3A (shown)).” In regards to claim 4, Benham discloses;” The via hole structure according to claim 2, wherein apertures of the first signal aperture segment and the second signal aperture segment located in the same horizontal direction are the same ((Fig. 1 ) shows 116a in same layout as 114a)).” In regards to claim 5, Benham discloses;” The via hole structure according to claim 4, wherein the first differential signal hole and the second differential signal hole are arranged symmetrically in the thickness direction of the circuit board(Fig’s 2 and 3A).” In regards to claim 6, Benham discloses;” The via hole structure according to claim 2, wherein an aperture of each first signal aperture segment is completely the same, partially the same or completely different; and an aperture of each second signal aperture segment is completely the same, partially the same or completely different (Fig. 3A (shown)).” In regards to claim 12, Benham discloses;” A circuit board, comprising a via hole structure (paragraphs 0005, 0008), the via hole structure comprises at least one pair of differential (Title) signal holes, wherein each pair of differential signal holes comprises a first differential signal hole and a second differential signal hole (Fig. 3A (Shown)); and in a thickness direction of the circuit board (paragraph 0029), there are several distances between a central axis of the first differential signal hole and a central axis of the second differential signal hole. and numerical values of at least two distances are different (Fig. 3A (shown)).” In regards to claim 13, Benham discloses;” The via hole structure according to claim 3, wherein apertures of the first signal aperture segment and the second signal aperture segment located in the same horizontal direction are the same (Fig. 3A (shows the via segments are horizontal to each other).” In regards to claim 14, Benham discloses;” The via hole structure according to claim 13, wherein the first differential signal hole and the second differential signal hole are arranged symmetrically in the thickness direction of the circuit board (Fig. 3A Fig. 1 ) shows (116a in same layout as 114a, paragraph 0017)).” In regards to claim 16, Benham discloses;” The circuit board according to claim 12, wherein the first differential signal hole comprises at least two first signal aperture segments communicated with each other in the thickness direction of the circuit board, and the second differential signal hole comprises at least two second signal aperture segments communicated with each other in the thickness direction of the circuit board (Fig. 3A (shown)).” In regards to claim 17, Benham discloses;” The circuit board according to claim 16, wherein the first signal aperture segments and/or the second signal aperture segments are set in a step shape in the thickness direction of the circuit board (Fig. 3A (Shown)).” In regards to claim 18, Benham discloses;” The circuit board according to claim 16, wherein apertures of the first signal aperture segment and the second signal aperture segment located in the same horizontal direction are the same ((Fig. 1 ) shows 116a in same layout as 114a)).” In regards to claim 19, Benham discloses;” The circuit board according to claim 18, wherein the first differential signal hole and the second differential signal hole are arranged symmetrically in the thickness direction of the circuit board (Fig’s 2 and 3A).” In regards to claim 20, Benham discloses;” The circuit board according to claim 16, wherein an aperture of each first signal aperture segment is completely the same, partially the same or completely different; and an aperture of each second signal aperture segment is completely the same, partially the same or completely different (Fig. 3A (shown)).” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Benham (US 20060118332 hereinafter Benham) as applied to claim 6 above, and further in view of PCB Tolerances: Standards, Practical Limits, and Design Guidance, attached (hereinafter PBC standard). In regards to claim 7, Benham discloses;” The via hole structure according to claim 6, wherein when the aperture of each first signal aperture segment is partially the same or completely different, and when the aperture of each second signal aperture segment is partially the same or completely different”, but does not directly disclose;” an absolute value of a difference between the apertures is ≥ 0.001 mm” However PBC standard discloses a table indication accepted tolerances for various features including via structures that suggest manufacturing variations between via that are greater than .0001 mm. It would have been obvious to a skilled artisan to know that in making a PCB a variation in manufacturing occurs. Therefore using the guideline suggested by PBC standard with the structure by Benham, the claimed invention is disclosed. In regards to claim 8, a modified Benham discloses;” The via hole structure according to claim 6, wherein in the thickness direction of the circuit board, center distances between the first signal aperture segments and the second signal aperture segments are completely the same, partially the same or completely different, and an absolute value of a difference between the different center distances is ≥ 0.001 mm when the center distances are partially the same or completely different (based on tolerances of PBC standard). Claim(s) 9-11, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Benham (US 20060118332 hereinafter Benham) as applied to claims 1 and 9 in view of Kushta et al. (US 20060255876 hereinafter Kushta). In regards to claim 9, Benham discloses;” The via hole structure according to claim 1”, but does not directly disclose;” wherein at least two ground via holes are configured around each pair of differential signal holes.” However, Kushta discloses a differential pair structure that has ground vias (Fig. 12 (1202)) adjacent to each signal vias (Fig. 12 (1201)). It would have been obvious to a skilled artisan to include grounding vias adjacent to signals to control impedance mismatch and to promote better signal integrity in high speed applications. Therefore, using the grounding via structure as disclosed by Kushta with the PCB structure of Benham, the claimed invention is disclosed. In regards to claim 10, a modified Benham discloses;” The via hole structure according to claim 9, wherein a length between the central axis of the first differential signal hole and a central axis of the adjacent ground via hole is equal in the thickness direction of the circuit board. The grounding via as disclosed by Kushta (Fig. 4B) is the same length as the signal via. It would have been obvious to a skilled artisan to form the signal via and ground via structures to be equal in design and layout. Therefore, the claimed invention is disclosed. In regards to claim 11, a modified Benham discloses;” The via hole structure according to claim 9, wherein a length between the central axis of the second differential signal hole and a central axis of the adjacent ground via hole is equal in the thickness direction of the circuit board (Kushta Fig. 2B and Fig. 12). In regards to claim 15, a modified Benham discloses;” The via hole structure according to claim 10, wherein a length between the central axis of the second differential signal hole and a central axis of the adjacent ground via hole is equal in the thickness direction of the circuit board (Kushta Fig. 2B and Fig. 12). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL F MCALLISTER/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Dec 27, 2024
Application Filed
Oct 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+6.4%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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