CTNF 18/879,551 CTNF 79412 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to Applicant’s preliminary amendment filed December 27, 2024. Claim 14 has been cancelled. Claims 1-13 have been amended and are currently pending. Information Disclosure Statement The IDS filed December 27, 2024 has been considered. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1, 5, and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 9 recite the limitations " the field devices," " the downlink direction," and “ the uplink direction” in the claim. There are insufficient antecedent basis for these limitations in the claims. Claim 5 recites the limitation “ the cycles.” There is insufficient antecedent basis for this limitation. Claim 13 recites “ the updating frequency and data volume requirements.” There is insufficient antecedent basis for this limitation. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 6, 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Speasl et al., (US 20210377137, hereinafter referred to as “Speasl.” NOTE: this reference is cited in the IDS filed 12/27/2024) in view of Wing et al. (US 10324773, hereinafter referred to as “Wing”) . Regarding claim 1, Speasl teaches an edge computing device (figure 1: computing device 150 configured to communicate with IoT device 110; figure 2: computing device 250) comprising: a processing unit (figure 8: processor 810); and a programmable logic unit ([0019] Functionality consistent with data collection-distribution controller 120 may be implemented partially or entirely by a processor executing instructions out of a memory, in firmware, as a state machine, in a software application program, in an application specific integrated circuit (ASIC), or in a field programmable gate array (FPGA).) having a first memory, a second memory (figure 8: memory 320), an instruction distribution module, and a data collection module (figure 1: data collection-distribution controller 120); wherein the processing unit receives instructions from a cloud computing system (figure 1: cloud/internet 140) and writes the instructions into the first memory, and reads data from the field devices from the second memory and sends the data to the cloud computing systems ([0020] Communications 130A may be sent to or via the cloud from IOT device 110 according to settings, policies, or rules that control the collection and distribution of data by data collection-distribution controller 120.); the instruction distribution module reads the instructions from the first memory and sends them to the corresponding field devices ([0020] Communications 130A may be sent to or via the cloud from IOT device 110 according to settings, policies, or rules that control the collection and distribution of data by data collection-distribution controller 120. Communications sent via communication channels 130A and 130B may include updating operating constraints, settings, policies, or rules associated with data collection-distribution controller 120. Updates to the data collection-distribution controller 120 may be provided by computing devices in the cloud 140 or may be provided by computing device 150.); and the data collection module collects data from the field devices and stores the data in the second memory ([0019] FIG. 1 includes an internet of things (IOT) device 110 that includes data collection-distribution controller 120 that may collect data from sensors or electronic devices and share/synchronize that collected data with computing device 150 via the cloud or Internet 140 using communication channels 130A and 130B. Functionality consistent with data collection-distribution controller 120 may be implemented partially or entirely by a processor executing instructions out of a memory, in firmware, as a state machine, in a software application program, in an application specific integrated circuit (ASIC), or in a field programmable gate array (FPGA).). However, Speasl does not explicitly teach the programmable logic unit generates periodic first time base signals and second time base signals; a first state machine is provided in the instruction distribution module; and a second state machine is provided in the data collection module so that in the downlink direction, the processing unit, the first memory, and the instruction distribution module implement downlink instruction distribution based on the first time base signal and the first state machine; and in the uplink direction, the processing unit, the second memory, and the data collection module implement uplink data transmission based on the second time base signal and the second state machine. In an analogous art, Wing teaches: the programmable logic unit generates periodic first time base signals and second time base signals; a first state machine is provided in the instruction distribution module; and a second state machine is provided in the data collection module so that in the downlink direction, the processing unit, the first memory, and the instruction distribution module implement downlink instruction distribution based on the first time base signal and the first state machine (col. 25, lines 15-27: the electronic device is periodically pinged to receive state information about the device such as the device's battery levels and network connectivity levels. The states depicted in state processing network 300 include: a started state 302, 48 hours still bad 306, no events in long time state 310, create or update a case state 314, waiting for response state 318 and success state 328. Further, state processing network 300 includes two types of transition triggers: event triggers 301, 309, and 320 and time triggers 303, 307, 311 and 313; col. 40, lines 28-30: data download); and in the uplink direction, the processing unit, the second memory, and the data collection module implement uplink data transmission based on the second time base signal and the second state machine (col. 25, lines 15-27: the electronic device is periodically pinged to receive state information about the device such as the device's battery levels and network connectivity levels. The states depicted in state processing network 300 include: a started state 302, 48 hours still bad 306, no events in long time state 310, create or update a case state 314, waiting for response state 318 and success state 328. Further, state processing network 300 includes two types of transition triggers: event triggers 301, 309, and 320 and time triggers 303, 307, 311 and 313; col. 40, lines 28-30: data download). Before the effective filing date of the invention, one of ordinary skill in the art would have been motivated to incorporate time-based state machine control of Wing to improve synchronization. Regarding claim 6, Speasl teaches the edge computing device as claimed in claim 1, wherein the processing unit communicates with the cloud computing system through the IoT control unit (figure 1: IoT 110 communicates with cloud/internet 140 through controller 120). Regarding claim 7, Speasl teaches the edge computing device as claimed in claim 1, wherein the IoT control unit communicates with the cloud computing system using a MQTT protocol ([0004] message queuing telemetry transport (MQTT) protoco). Claim 9 is similar to claim 1, but in method form, and is therefore rejected under the same rationale . 07-21-aia AIA Claim (s) 4, 5, 8, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Speasl et al., (US 20210377137, hereinafter referred to as “Speasl.” NOTE: this reference is cited in the IDS filed 12/27/2024) in view of Wing et al. (US 10324773, hereinafter referred to as “Wing”) in further view of Cella et al. (US 12585255, hereinafter referred to as “Cella”) . Regarding claim 4, neither Speasl nor Wing explicitly teaches the edge computing device as claimed in claim 1, wherein the first time base signal and the second time base signal are periodic square wave signals. In an analogous art, Cella teaches wherein the first time base signal and the second time base signal are periodic square wave signals (col. 8, lines 24-39: digital waveforms). Before the effective filing date of the invention, one of ordinary skill in the art would have been motivated to employ periodic square wave signals because square waves are standard form of clock/timing signals used in digital systems to control state machines, thus ensuring that operation is synchronized. Regarding claim 5, neither Speasl nor Wing explicitly teaches the edge computing device as claimed in claim 1, wherein the cycles of the first time base signal and the second time base signal are determined in updating frequency and data volume requirements of the instructions and the data. In an analogous art, Cella teaches wherein the cycles of the first time base signal and the second time base signal are determined in updating frequency and data volume requirements of the instructions and the data (col. 11, lines 34-55: Methods and systems described herein for industrial machine sensor data streaming, collection, processing, and storage may be configured to operate and integrate with existing data collection, processing and storage systems and may include a method for capturing a plurality of streams of sensed data from sensors deployed to monitor aspects of an industrial machine associated with at least one moving part of the machine; at least one of the streams contains a plurality of frequencies of data. The method may include identifying a subset of data in at least one of the plurality of streams that corresponds to data representing at least one predefined frequency. The at least one predefined frequency is represented by a set of data collected from alternate sensors deployed to monitor aspects of the industrial machine associated with the at least one moving part of the machine. The method may further include processing the identified data with a data processing facility that processes the identified data with an algorithm configured to be applied to the set of data collected from alternate sensors. Lastly, the method may include storing the at least one of the streams of data, the identified subset of data, and a result of processing the identified data in an electronic data set.). Before the effective filing date of the invention, one of ordinary skill in the art would have been motivated to enable the determine the cycles of the base signals based on updating frequency and data volume requirements because such parameters directly affect system performance, including latency and bandwidth utilization. Regarding claim 8, neither Speasl nor Wing explicitly teaches the edge computing device as claimed in claim 1, wherein the first memory and the second memory comprise dual-port block memories. In an analogous art, Cella teaches wherein the first memory and the second memory comprise dual-port block memories (col. 29, lines 44-52: In embodiments, intense signal processing activities including resampling, weighting, filtering, and spectrum processing may be performed by dedicated processors such as field-programmable gate array (“FPGAs”), digital signal processor (“DSP”), microprocessors, micro-controllers, or a combination thereof. In embodiments, this subsystem may communicate via a specialized hardware bus with the communication processing section. It will be facilitated with dual-port memory, semaphore logic, and so on.). before the effective filing date of the invention, one of ordinary skill in the art would have been motivated to employ dual-port block memories because they are well-known and conventional solution for enabling simultaneous read and write operations in systems that require concurrent data processing. Claims 12-13 are similar to claims 4-5, respectively, therefore are rejected under the same rationale . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 2, 3, 10, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2, the prior art of record does not teach the edge computing device as claimed in claim 1, wherein: starting from each falling edge of the first time base signal, the processing unit begins writing instructions from the cloud computing system into the first memory, the write operation ends at a moment during a low level of the current cycle of the first time base signal, and during this process, the first state machine of the instruction distribution module is in an idle state; at the next rising edge of the first time base signal, the instruction distribution module begins reading the instructions from the first memory and buffering them in a first buffer, and the first state machine is in the a read state; next, the instruction distribution module sequentially distributes the buffered instructions from the first buffer to the corresponding field devices, the first state machine is in a push state; after all the instructions have been distributed, the first state machine goes into the idle state and waits to enter the read state for the next cycle. Regarding claim 3, the prior art of record does not teach the edge computing device as claimed in claim 1, wherein: at each rising edge of the second time base signal, the processing unit begins reading data from the second memory from the previous cycle, the read operation ends at a moment during a high level of the current cycle, and the processing unit sends the data to the cloud; during the high-level period, the data collection module collects data from all field devices and stores the data in a second buffer, the second state machine is in the data collection state; starting at the falling edge of the high-level period of the second time base signal, the data collection module writes the buffered data from the second buffer into the second memory, the second state machine is in the data write state, after the write operation ends, the second state machine goes into the idle state and waits to enter the data collection state for the next cycle. Claims 10-11 are similar to claims 2-3, respectively, therefore are objected to for the same reason. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al., US 20180262941 - a wireless telecommunication network to provide notification to external devices (such as application servers) regarding Internet-of-Things (IoT) devices attached to the network. Saylor et al., US 6661340 - a personal security network where an individual's system or systems of security devices may be connected to a central security network. Gotz et al., US 11544206 - a process control unit that is used in particular for control or feedback control of a machine or installation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALINA N BOUTAH whose telephone number is (571)272-3908. The examiner can normally be reached M-F 7:00 AM - 3:00 PM. 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ALINA BOUTAH Primary Examiner Art Unit 2458 /ALINA A BOUTAH/Primary Examiner, Art Unit 2458 Application/Control Number: 18/879,551 Page 2 Art Unit: 2458 Application/Control Number: 18/879,551 Page 3 Art Unit: 2458 Application/Control Number: 18/879,551 Page 4 Art Unit: 2458 Application/Control Number: 18/879,551 Page 5 Art Unit: 2458 Application/Control Number: 18/879,551 Page 6 Art Unit: 2458 Application/Control Number: 18/879,551 Page 7 Art Unit: 2458 Application/Control Number: 18/879,551 Page 8 Art Unit: 2458 Application/Control Number: 18/879,551 Page 9 Art Unit: 2458 Application/Control Number: 18/879,551 Page 10 Art Unit: 2458 Application/Control Number: 18/879,551 Page 11 Art Unit: 2458 Application/Control Number: 18/879,551 Page 12 Art Unit: 2458 Application/Control Number: 18/879,551 Page 13 Art Unit: 2458
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