Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 27 December 2024.
Claim 6-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Breakstone (US PG PUB No. 2018/0322082).
As per claim 1, an access acceleration system for a storage device (see FIG 5: 500), comprising a central processing unit (see e.g., FIG 5: 534), a Peripheral Component Interconnect Express (PCle) device (see FIG 5: 530), a storage device (see FIG 5: 510), a computing chip (see FIG 5: 515), and memories (see e.g., [0030]: “graphics memory”);
[Each module is taken to comprise respective memories.]
wherein the PCle device comprises a root complex device (see FIG 6B: 532 and [0082]), a PCle switch (see FIG 6B: 633 and [0082]), and a PCle endpoint (see FIG 6B: 653 and [0082]);
[Breakstone discloses different PCIe configurations including a compute module with a root complex.]
the central processing unit is in communication connection with an upstream port of the PCle switch through the root complex device (see FIG 10B 1051), the storage device is in communication connection with a downstream port of the PCle switch (see e.g., FIG 10: 1002 and [0109]), the computing chip is in communication connection with a downstream port of the PCle switch through the PCle endpoint (see e.g., FIG 10: 1002), and the storage device and the computing chip are in communication connection with different downstream ports of the PCle switch, respectively (see FIG 5: 503); and
[Breakstone discloses a system with a graphics module and a storage module and further discloses they may be configured as endpoints, with the compute module comprising the root complex (see FIG 6B: 530).]
the central processing unit and the computing chip are electrically connected to different one of the memories (see FIG 5: 530 and 540).
[Each of the Compute Module and Graphics Module is taken to comprise different ones of the memories.]
As per claim 2, the system according to claim 1,
wherein the system further comprises: a network interface card, in communication connection with a downstream port of the PCle switch (see FIG 1: 140 and [0031]), wherein the network interface card, the storage devices, and the computing chip are in communication connection with different downstream ports of the PCle switch, respectively (see [0022]).
As per claim 3, the system according to claim 1,
wherein the system comprises at least one host unit (see FIG 6B: 530) and at least one computing unit (see FIG 6B: 650);
each host unit of the at least one host unit comprises one said central processing unit (see FIG 6B: 531), one said root complex device (see FIG 6B: 532), and one memory of the memories (see e.g., [0081]);
each computing unit of the at least one computing unit comprises at least one said PCle switch (see e.g., FIG 5: 511), a plurality of said storage devices (see FIG 5: 510), at least one said computing chip (see FIG 5: 515), at least one said PCle endpoint (see e.g., FIG 6B: 653), and at least one memory of the memories (see e.g., [0085]);
each root complex device is in communication connection with the PCle switch of the at least one computing unit; and in the each computing unit, each PCle switch that is in communication connection with the root complex device is in communication connection with the plurality of storage devices, each computing chip is in communication connection with the at least one PCle switch through the at least one PCle endpoint, and the at least one computing chip is electrically connected one-to-one to the at least one memory (see FIG 5: 510 and [0085]).
[Breakstone discloses the compute module may be configured to comprise a root complex and the other modules as endpoints.]
As per claim 4, the system according to claim 3,
wherein at least one of the at least one computing unit comprises a plurality of PCle switches and a plurality of computing chips, and in the same computing unit, the PCle switches correspond to the computing chips on a one-to-one basis.
As per claim 5, the system according to claim 4, wherein,
each PCle switch in the same computing unit is in communication connection with the root complex device (see FIG 6B: 532 and [0085]); and
in the same computing unit, a plurality of PCle endpoints that are in communication connection with any one of the computing chips are in communication connection with a plurality of downstream ports of one of the PCle switches on a one-to-one basis (see [0082]).
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 20190347212 : A data transmission method an SoC could obtain a first request where the first request message includes a first address of a storage medium and an operation type, and the first address is an address assigned by a processor to the storage medium in a memory address managed by the processor; determine a second address according to the first address and generating a second request message, where the second address is an address assigned by the SoC to the storage medium in a memory address managed by the SoC; send a first control instruction to a DMA controller of the storage medium according to the second address, where the first control instruction is used to instruct the DMA controller to obtain the second request message.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
Prosecution Insights