DETAILED ACTION
The instant action is in response to application 30 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title is not descriptive enough. Examiner suggests emphasizing the claimed charging of the bootstrap capacitor.
The 1st paragraph has the oldest filing date from the Chineese application, so no changes are technically required. However, it is ordinary and customary to include other copending application’s filing date and publication dates (if available).
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 20 May 2023.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
As to claim 1, applicant claims “; both ends of the bootstrap capacitor are respectively coupled to the first node and a first electrode of the first transistor;”. As near as can be determined though, applicant has one end of the bootstrap connected to the switching node and the other connected to the BTST voltage. For the purposes of examination, it will be assumed applicant meant to claim a single end.
As to claim 15, there is a similar problem to claim 1 above.
Claims 2-14, 16, 17 depend directly or indirectly from a rejected claim and are, therefore, also rejected under 35 USC 112(b) , or 35 U.S.C. 112 (pre-AIA ) second paragraph for the reasons set above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 9, 12 are (as best understood) rejected under 35 U.S.C. 102 (a)(2) as being anticipated by D’Souza (US 20240030812).
As to claim 1, D’Souza discloses A Direct Current (DC)-DC converter (Fig. 3), comprising an upper power transistor (340), a lower power transistor (350), an inductor (225A-1), a bootstrap capacitor (224A-1), a first transistor (Fig. 5, 530), a charging control circuit (325), a drive control circuit (310), and a driver circuit (317), wherein wherein-the driver circuit is configured to generate an upper transistor on signal and a lower transistor on signal according to a drive control signal output by the drive control circuit (312, 313), wherein when the drive control signal is at a first level, the upper transistor on signal is at an active level and the lower transistor on signal is at an inactive level, and when the drive control signal is at a second level, the upper transistor on signal is at the inactive level and the lower transistor on signal is at the active level (the two switch complimentary in a buck converter); a control electrode of the upper power transistor is provided with the upper transistor on signal, a control electrode of the lower power transistor is provided with the lower transistor on signal (Fig. 3, 312/313 are gate signals to 340/350), and a first electrode (drain) of the upper power transistor is coupled to a second electrode (source) of the lower power transistor and a first end of the inductor through a first node; both ends of the bootstrap capacitor are respectively coupled to the first node and a first electrode of the first transistor (the bootstrap capacitor is coupled to the switching node and a separate power supply, similar to applicants); the charging control circuit is configured to generate a charging control voltage according to a Pulse Width Modulation (PWM) signal (PWMA-1), wherein when the PWM signal is at the first level, the charging control voltage is set to a voltage at the first electrode of the first transistor (¶75 “Thus, as depicted in FIG. 6, voltage (V-gate, 650) at the gate terminal of switch 530 toggles between values V-2 (636) and V-4 (631), while voltage (V-boot, 215) at the boot node toggles between values Vboot-3 (641) and Vboot-1 (646), corresponding to transitions in PWM signal.”), and when the PWM signal is at the second level, the charging control voltage is set to a voltage at the first node (See Fig. 6); a control electrode of the first transistor is provided with the charging control voltage, and a second electrode of the first transistor is coupled to a charging voltage end (Vboot); and the drive control circuit is configured to determine an on-off state of the first transistor according to the charging control voltage, and cause the drive control signal to be at the first level in a case where the PWM signal is at the first level and the first transistor is completely turned off, otherwise cause the drive control signal to be at the second level (See Fig. 6. When PWM is high, gate 650 is low and Vice versa).
As to claim 7, Dsouza discloses wherein both the upper power transistor and the lower power transistor are N-channel Metal Oxide Semiconductor (NMOS) transistors.
As to claim 9, D’Souza discloses wherein a second electrode of the upper power transistor is coupled to one of an input voltage end and an output voltage end, and a second end of the inductor is coupled to the other of theinput voltage end and the output voltage end (he teaches buck topology).
As to claim 12, D’Souza teaches wherein the charging control circuit is coupled to the first node, the first electrode of the first transistor, and the control electrode of the first transistor (all of those points appear to be connected via 317).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over D’Souza (US 20240030812) in view of Yamazaki (US 20050201186).
As to claim 6, D’Souza does not disclose wherein the charging control circuit comprises a second level conversion circuit,and-a second transistor, a third transistor, a fourth transistor and te-a fifth transistor, wherein the second level conversion circuit is configured to convert the first level of the PWM signal to a fifth level, and convert the second level of the PWM signal to a sixth level; a control electrode of the second transistor is coupled to a control electrode of the third transistor and an output end of the second level conversion circuit, a first electrode of the second transistor is coupled to the first electrode of the first transistor and a first electrode of the fourth transistor, and a second electrode of the second transistor is coupled to a second electrode of the third transistor, a control electrode of the fourth transistor, and a control electrode of the fifth transistor; a first electrode of the third transistor is coupled to the first node and a first electrode of the fifth transistor; and a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor and the control electrode of the first transistor.
Yamanaki teaches (Fig. 3) wherein the charging control circuit comprises a second level conversion circuit,and-a second transistor, a third transistor, a fourth transistor and te-a fifth transistor, wherein the second level conversion circuit is configured to convert the first level of the PWM signal to a fifth level, and convert the second level of the PWM signal to a sixth level; a control electrode of the second transistor is coupled to a control electrode of the third transistor and an output end of the second level conversion circuit, a first electrode of the second transistor is coupled to the first electrode of the first transistor and a first electrode of the fourth transistor, and a second electrode of the second transistor is coupled to a second electrode of the third transistor, a control electrode of the fourth transistor, and a control electrode of the fifth transistor; a first electrode of the third transistor is coupled to the first node and a first electrode of the fifth transistor; and a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor and the control electrode of the first transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use level shifting circuit as disclosed in Yamazaki to provide a method of boosting the signal without an additional capacitor.
Claims 8, 11, 13 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over D’Souza (US 20240030812).
As to calm 8, D’Souza teaches wherein the first transistor is l Metal Oxide Semiconductor transistor. He does not explicitly teach PFETs. However, this is old and well known and therefore not patentable. Per §MPEP 2144.03, merely changing types of switches from n-type to p-type is within the capability of one of ordinary skill. See US Patent 4,970,415 Col. 6 lines 66 – Col. 7 line 9. See also US Patent Application Publication 2012/0146599, ¶0049.
As to claim 11, D’Souza teaches having the driver control circuit with multiple transistors, but does not describe all of the specifics in the claim. However, rearrangement of parts (MPEP 2144.04 VI) and making integral/seperate (MPEP 2144.04 V) are generally regarded as obvious.
As to claim 13, D’Souza teaches a dirver and driver control circuit, though not in the exact order specified. However, this is regarded as obvious per the same reasons as claim 11 above.
Claims 10 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over D’Souza (US 20240030812) in view of Lee (US 20090103341).
As to claim 10, D’Souza teaches wherein, when the second electrode of the upper power transistor is coupled to the input voltage end and the second end of the inductor is coupled to the output voltage end, the DC-DC converter is a buck converter;
D’Souza does not teach and when the second electrode of the upper power transistor is coupled to the output voltage end and the second end of the inductor is coupled to the input voltage end, the DC-DC converter is a boost converter.
Lee teaches wherein, when the second electrode of the upper power transistor is coupled to the input voltage end and the second end of the inductor is coupled to the output voltage end, the DC-DC converter is a buck converter; and when the second electrode of the upper power transistor is coupled to the output voltage end and the second end of the inductor is coupled to the input voltage end, the DC-DC converter is a boost converter (abstract describes bidirectional buck/boost flow).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use bidirectional buck/boost converters as disclosed in Lee to provide a path for regenerative power.
Allowable Subject Matter
Claims 15-17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
Claims 2-5, 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the prior art fails to disclose: “wherein the drive control circuit comprises a turn-off determination circuit and a control signal output circuit, wherein the turn-off determination circuit is configured to output a turn-off indication signal at the active level when the charging control voltage is greater than or equal to a reference voltage, otherwise output the turn-off indication signal at the inactive level, wherein the active level of the turn-off indication signal indicates that the first transistor is completely turned off, and the reference voltage is set according to a threshold voltage of the first transistor; and the control signal output circuit is configured to output the drive control signal at the first level when the PWM signal is at the first level and the turn-off indication signal is at the active level, otherwise output the drive control signal at the second level.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 15, the prior art fails to disclose: “wherein the Schmitt trigger is configured to generate a trigger signal according to a charging control voltage at the control electrode of the first transistor, wherein the trigger signal is inverted to a third level when the charging control voltage rises to an upper threshold, and is inverted to a fourth level when the charging control voltage drops to a lower threshold, and the lower threshold is lower than the upper threshold; the first level conversion circuit is configured to generate a turn-off indication signal according to the trigger signal, wherein the third level of the trigger signal is converted to the active level of the turn-off indication signal, and the fourth level of the trigger signal is converted to the inactive level of the turn-off indication signal; and a first input end of the AND gate is provided with the turn-off indication signal, and a second input end of the AND gate is provided with the PWM signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER M NOVAK/ Primary Examiner, Art Unit 2839
Prosecution Insights