DETAILED ACTION
This office action is in response to the application filed on 01/02/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/02/2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 3, 5, 7, 9 and 13 are objected to because of the following informalities: Claim 1 lines 13 “a conductive state” and “a non-conductive” should be “the conductive state” and “the non-conductive”. Claims 3, 5, 7 and 13 recite “a conductive state” and “a non-conductive” should be “the conductive state” and “the non-conductive”. Claims 3, 5 and 7 lines 9-10 “a second-order” should be “the second-order”. Claim 7 lines 9-10 “a first-order” should be “the first-order”. Claim 9 and 10 line 2 recite “voltage... threshold voltage” should be “a voltage... a threshold voltage”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 7 recite “differential value thereof” it is not clear what part or signal is the applicant referring to when mentioning thereof, is the application referring to a part of the circuit or a part of a signal or waveform. For purposes of examination the limitations are going to be interpreted as the thereof referring to one or both of the reference waveform.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10, 12 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satoh US 2020/0112307.
Regarding Claim 1, Satoh (Figures 1, 5-6 and 11) a semiconductor driving device (111p-112p, 131p-132P and 121p-122p) for driving a multi-gate semiconductor switching element (200p) having a plurality of gate terminals (g1-g2), the semiconductor driving device comprising: a timing generator (111p-112p) which turns on/off gate ON reference signals (output from 111 and 112) respectively for the plurality of gate terminals on the basis of an ON/OFF reference signal (from 90) from outside; a gate reference waveform generator (131-132) which generates a first gate reference waveform (from 131) corresponding to at least one first gate terminal (at G1) and a second gate reference waveform (from 132) corresponding to at least one second gate terminal (at g2), among the plurality of gate terminals, on the basis of on/off of the gate ON reference signals (from 131 and 132), and controls one or both of the first gate reference waveform and the second gate reference waveform in one or both of shifting from a non-conductive state to a conductive state of the multi-gate semiconductor switching element (controlling from off to on state, see par. 77-84) and shifting from a conductive state to a non-conductive state of the multi-gate semiconductor switching element (controlling from on to off state, see par. 77-84); and a signal amplifier (121-122) which receives, as an input waveform, one or both of the first gate reference waveform and the second gate reference waveform (from 131-132), and amplifies the input waveform so that an output waveform follows the input waveform (par. 29). (For Example: Par. 75-84 and 133-137)
Regarding Claim 9, Satoh (Figures 1, 5-6 and 11) wherein a voltage not less than a threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switching element temporally prior to other gate terminals including the second gate terminal (see fig. 11 after t0, when the voltage at the switch is higher than the threshold the switch is to be turned on, with the Sigbt signal high this would generate a high spl1 signal before the spl2 signal). (For Example: Par. 75-84 and 133-137)
Regarding Claim 10, Satoh (Figures 1, 5-6 and 11) wherein voltage less than threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switching element temporally prior to other gate terminals including the second gate terminal. (see fig. 11 before t0, when the voltage at the switch is less than the threshold, the signal sent to the gate is low level and this low level is sent prior to the t0 time). (For Example: Par. 75-84 and 133-137)
Regarding Claim 12, Satoh (Figures 1, 5-6 and 11) wherein at least one of the first gate reference waveform and the second gate reference waveform partially includes a charge voltage shape or a discharge voltage shape formed by a capacitor and a resistor (Fig. 6 at 131-132). (For Example: Par. 75-84 and 88-89)
Regarding Claim 17, Satoh (Figures 1, 5-6 and 11) wherein the multi-gate semiconductor switching element is any of hybrid elements formed by arranging a multi-gate IGBT, an RC-IGBT, an IGBT (200, par. 72), and a MOSFET in parallel.
Regarding Claim 18, Satoh (Figures 1, 5-6 and 11) a power conversion device (Fig. 1) comprising: a device (200) which has a multi-gate semiconductor switching element as a semiconductor switching element and which is one of an inverter device which converts DC power to AC power (see fig. 1), a boost converter device which steps up voltage of DC power, a buck converter device which steps down voltage of DC power, an AC-DC converter device which converts AC power to DC power, a boost inverter device which includes the boost converter device and the inverter device, and a buck inverter device which includes the buck converter device and the inverter device; and the semiconductor driving device according to claim 1 (see rejection to claim 1), which drives the multi-gate semiconductor switching element. (For Example: Par. 75-84 and 133-137)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Takeuchi US 2020/0395471.
Regarding Claim 11, Satoh (Figures 1, 5-6 and 11) the device.
Satoh does not teach wherein the first gate reference waveform and the second gate reference waveform are identical waveforms with a predetermined time difference therebetween.
Takeuchi teaches (Figures 2 and 5) wherein the first gate reference waveform and the second gate reference waveform (Signal A and signal E) are identical waveforms with a predetermined time difference therebetween (see fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Satoh to include wherein the first gate reference waveform and the second gate reference waveform are identical waveforms with a predetermined time difference therebetween, as taught by Takeuchi to avoid a continuous ON state and an ON state twice for one on-pulse signal.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Takeuchi US 2020/0395471.
Regarding Claim 13, Satoh (Figures 1, 5-6 and 11) the device according to claim 1.
Satoh does not teach wherein the gate reference waveform generator performs control so that at least one of the first gate reference waveform and the second gate reference waveform in shifting from a non-conductive state to a conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value of the gate reference waveform discontinuously decreases, and at least one of the first gate reference waveform and the second gate reference waveform in shifting from a conductive state to a non-conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value of the gate reference waveform discontinuously increases.
Takeuchi teaches (Figures 10-12) wherein the gate reference waveform generator performs control (at fig. 10) so that at least one of the first gate reference waveform and the second gate reference waveform in shifting from a non-conductive state to a conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value (dv/dt) of the gate reference waveform discontinuously decreases (see fig. 11 with Vg# discontinuously decreases), and at least one of the first gate reference waveform and the second gate reference waveform in shifting from a conductive state to a non-conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value (dv/dt) of the gate reference waveform discontinuously increases (see fig. 11 with Vg# discontinuously increases). (For Example: Par.111-117)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Satoh to include wherein the gate reference waveform generator performs control so that at least one of the first gate reference waveform and the second gate reference waveform in shifting from a non-conductive state to a conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value of the gate reference waveform discontinuously decreases, and at least one of the first gate reference waveform and the second gate reference waveform in shifting from a conductive state to a non-conductive state of the multi-gate semiconductor switching element partially includes such a shape that a first-order differential value of the gate reference waveform discontinuously increases, as taught by Takeuchi to reduce power loss in the power transistor.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Jansen US 2010/0164601.
Regarding Claim 15, Satoh (Figures 1, 5-6 and 11) wherein the signal amplifier (121-122).
Satoh does not teach w wherein the signal amplifier includes one or both of a complementary emitter follower circuit and a complementary source follower circuit.
Takeuchi teaches (Figure 14) wherein the signal amplifier includes one or both of a complementary emitter follower circuit (par. 93, at 120) and a complementary source follower circuit.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Satoh to include wherein the signal amplifier includes one or both of a complementary emitter follower circuit and a complementary source follower circuit, as taught by Jansen to reduce power losses in the system.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Fujii US 11515700.
Regarding Claim 16, Satoh (Figures 1, 5-6 and 11) the device.
Satoh does not teach wherein the gate reference waveform generator includes at least one operational amplifier.
Fujii teaches (Figure 1) wherein the gate reference waveform generator (23-28) includes at least one operational amplifier (23). (Col. 3 lines 50-67)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Satoh to include wherein the gate reference waveform generator includes at least one operational amplifier, as taught by Fujii to reduce higher surge voltage in the system.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 3; prior art of record fails to disclose either by itself or in combination: “…the gate reference waveform generator performs control so that one or both of a second-order differential value of the first gate reference waveform and a second-order differential value of the second gate reference waveform become not greater than zero, and in shifting from a conductive state to a non-conductive state of the multi-gate semiconductor switching element, the gate reference waveform generator performs control so that one or both of a second-order differential value of the first gate reference waveform and a second-order differential value of the second gate reference waveform become not less than zero”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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