DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of documents required by 37 CFR 1.55.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 01/02/2025 is in compliance with the provisions of 37 CFR 1.97 and was considered by the examiner.
Claim Objections
4. Claim 10 is objected to because of the following informalities: The term "MIS" is an acronym, which can mean different things and/or change in meaning over time; hence, it would be desirable to write out the actual words to which the acronym refers. Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1, 4-5, 9-12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murase et al. (PCT/JP2020/043269 published on 05/27/2021 as WO 2021/100826 A1, having a corresponding US-PGPUB 2022/0397651, and hereby used as an English translation).
Regarding claim 1, Murase discloses a photodetection device (Light receiving element 10; see fig. 71) comprising:
a photogate electrode provided above a photodiode (Photo gates PG and Photodiode PD; see fig. 71 and paragraphs 0287-0290); and
one or more transfer transistors that transfer charge obtained as a result of photoelectric conversion performed by the photodiode to a charge storage unit (Transfer gate TG; see fig. 71 and paragraphs 0287-0291. The charges EC are accumulated in the floating diffusion FD (FDA, FDB) via the transfer electrode VG in a state where the transfer gates TG are opened (ON state); see paragraphs 0267-0269),
wherein the transfer transistors are vertical transistors each including a buried gate electrode portion in which a gate electrode is buried in a semiconductor substrate (Transfer electrodes VG (Vertical Gate); see fig. 71. The transfer electrode VG connects the transfer gate TG and the photodiode PD; see paragraphs 0287-0291, 0296. The transfer electrode VG is formed by using a vertical type transistor to have a configuration in which a gate electrode (polysilicon) is extended inside a silicon substrate, and connects the transfer gate TG and the photodiode PD. Further, the transfer electrode VG is an electrode created by embedding polysilicon in an excavated portion of a silicon substrate. That is, the transfer electrode VG forms an embedded type gate; see paragraphs 0267-0270).
Regarding claim 4, Murase discloses everything claimed as applied above (see claim 1). In addition, Murase discloses the photogate electrode is a vertical gate electrode including a buried gate electrode portion buried in the semiconductor substrate (In FIGS. 79 and 80, the configuration of the light receiving element 10 can be one having a vertical photo gate VPG. The vertical photo gate VPG is formed in a shape extending vertically from the first semiconductor layer 10A and embedded in the photodiode PD; see paragraphs 0303-0305).
Regarding claim 5, Murase discloses everything claimed as applied above (see claim 4). In addition, Murase discloses the buried gate electrode portion of the photogate electrode is formed in such a way as to be shorter than the buried gate electrode portion of each transfer transistor with respect to depth in a substrate thickness direction (The first semiconductor layer 10A can have a configuration having plural (four) photo gates PG and plural (four) transfer electrodes VG; see figs. 71, 79 and paragraphs 0288-0291, 0303-0305).
Regarding claim 9, Murase discloses everything claimed as applied above (see claim 1). In addition, Murase discloses wherein two or four of the transfer transistors are provided for one pixel (Figures 71, 79 illustrate one transfer gate connected to FDA and another transfer gate connected to FDB; see paragraphs 0288, 0305).
Regarding claim 10, Murase discloses everything claimed as applied above (see claim 1). In addition, Murase discloses wherein the charge storage unit includes a floating diffusion region or a MIS capacitor (Floating diffusions FDA, FDB and capacitor MIM; see figs. 71, 79 and paragraphs 0288, 0297).
Regarding claim 11, Murase discloses a photodetection device (Light receiving element 10; see fig. 79) comprising:
a photogate electrode provided above a photodiode (Photo gates VPG and Photodiode PD; see fig. 79 and paragraphs 0303-0304); and
one or more transfer transistors that transfer charge obtained as a result of photoelectric conversion performed by the photodiode to a charge storage unit (Transfer gate TG; see figs. 79, 71 and paragraphs 0305, 0287-0291. The charges EC are accumulated in the floating diffusion FD (FDA, FDB) via the transfer electrode VG in a state where the transfer gates TG are opened (ON state); see paragraphs 0267-0269),
wherein the photogate electrode is a vertical gate electrode including a buried gate electrode portion buried in a semiconductor substrate (In FIGS. 79 and 80, the configuration of the light receiving element 10 can be one having a vertical photo gate VPG. The vertical photo gate VPG is formed in a shape extending vertically from the first semiconductor layer 10A and embedded in the photodiode PD; see paragraphs 0303-0305).
Regarding claim 12, Murase discloses everything claimed as applied above (see claim 11). In addition, Murase discloses the transfer transistors are vertical transistors each including a buried gate electrode portion in which a gate electrode is buried in the semiconductor substrate (Transfer electrodes VG (Vertical Gate); see figs. 79, 71. The transfer electrode VG connects the transfer gate TG and the photodiode PD; see paragraphs 0287-0291, 0296. The transfer electrode VG can be formed by using a vertical type transistor to have a configuration in which a gate electrode (polysilicon) is extended inside a silicon substrate, and connects the transfer gate TG and the photodiode PD. Further, the transfer electrode VG is an electrode created by embedding polysilicon in an excavated portion of a silicon substrate. That is, the transfer electrode VG forms an embedded type gate; see paragraphs 0267-0270).
Regarding claim 15, Murase discloses everything claimed as applied above (see claim 12). In addition, Murase discloses the buried gate electrode portion of the photogate electrode is formed in such a way as to be shorter than the buried gate electrode portion of each transfer transistor with respect to depth in a substrate thickness direction (The first semiconductor layer 10A can have a configuration having plural (four) photo gates PG and plural (four) transfer electrodes VG; see figs. 71, 79 and paragraphs 0288-0291, 0303-0305).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 2-3 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Murase in view of Cohen et al. (US-PGPUB 2010/0039546).
Regarding claim 2, Murase discloses everything claimed as applied above (see claim 1). However, Murase does not expressly disclose in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction.
On the other hand, Cohen discloses in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction (In FIG. 6A, transfer gates 84a and 84b are of substantially the same length as photogate 86. In FIG. 6B, photogate 86' is shorter than transfer gates 84a' and 84b'; see paragraph 0014).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Cohen to provide in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction for the purpose of providing a pixel architecture that can deal with high illumination levels (see paragraphs 0013-0014).
Regarding claim 3, Murase discloses everything claimed as applied above (see claim 1). In addition, Murase discloses the transfer transistors each include two buried gate electrode portions (Transfer electrodes VG (Vertical Gate); see fig. 71. The transfer electrode VG connects the transfer gate TG and the photodiode PD; see paragraphs 0287-0291, 0296. The transfer electrode VG is formed by using a vertical type transistor to have a configuration in which a gate electrode (polysilicon) is extended inside a silicon substrate, and connects the transfer gate TG and the photodiode PD. Further, the transfer electrode VG is an electrode created by embedding polysilicon in an excavated portion of a silicon substrate. That is, the transfer electrode VG forms an embedded type gate; see paragraphs 0267-0270).
However, Murase does not expressly disclose in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two buried gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction.
Nevertheless, Cohen discloses in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction (In FIG. 6B, photogate 86' is shorter than transfer gates 84a' and 84b'; see paragraph 0014).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Cohen to provide in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two buried gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction for the purpose of providing a pixel architecture that can deal with high illumination levels (see paragraphs 0013-0014).
Regarding claim 13, Murase discloses everything claimed as applied above (see claim 12). However, Murase does not expressly disclose in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction.
On the other hand, Cohen discloses in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction (In FIG. 6A, transfer gates 84a and 84b are of substantially the same length as photogate 86. In FIG. 6B, photogate 86' is shorter than transfer gates 84a' and 84b'; see paragraph 0014).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Cohen to provide in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be equal to or smaller than width of the transfer transistors in a second direction perpendicular to the first direction for the purpose of providing a pixel architecture that can deal with high illumination levels (see paragraphs 0013-0014).
Regarding claim 14, Murase discloses everything claimed as applied above (see claim 12). In addition, Murase discloses the transfer transistors each include two buried gate electrode portions (Transfer electrodes VG (Vertical Gate); see fig. 71. The transfer electrode VG connects the transfer gate TG and the photodiode PD; see paragraphs 0287-0291, 0296. The transfer electrode VG is formed by using a vertical type transistor to have a configuration in which a gate electrode (polysilicon) is extended inside a silicon substrate, and connects the transfer gate TG and the photodiode PD. Further, the transfer electrode VG is an electrode created by embedding polysilicon in an excavated portion of a silicon substrate. That is, the transfer electrode VG forms an embedded type gate; see paragraphs 0267-0270).
However, Murase does not expressly disclose in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two buried gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction.
Nevertheless, Cohen discloses in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction (In FIG. 6B, photogate 86' is shorter than transfer gates 84a' and 84b'; see paragraph 0014).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Cohen to provide in a case where an arrangement direction of the photogate electrode and the transfer transistors is defined as a first direction, width of the photogate electrode is formed in such a way as to be smaller than width of the two buried gate electrode portions of each transfer transistor in a second direction perpendicular to the first direction for the purpose of providing a pixel architecture that can deal with high illumination levels (see paragraphs 0013-0014).
11. Claims 6-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Murase in view of Jin et al. (US-PGPUB 2022/0021831).
Regarding claim 6, Murase discloses everything claimed as applied above (see claim 1). However, Murase does not expressly disclose a first voltage, or a second voltage is applied to the photogate electrode.
On the other hand, Jin discloses a first voltage, or a second voltage is applied to the photogate electrode (A second DC voltage level VDC′ of the photogate voltage VPG during the reset period TRST and the readout period TRD may be different from the first DC voltage level VDC during the integration period TINT. The first DC voltage level VDC during the integration period TINT may be a voltage level between the high voltage level VH and the low voltage level VL of the demodulation signals STGA and STGB. During the reset period TRST and the readout period TRD, the overflow gates OG1 and OG2 are in the turned-on state, and the second DC voltage level VDC′ may be determined based on the potential distribution of the channels formed in the semiconductor substrate; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide a first voltage or a second voltage is applied to the photogate electrode for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Regarding claim 7, Murase and Jin disclose everything claimed as applied above (see claim 6). However, Murase does not disclose the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors.
Nevertheless, Jin discloses the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors (The first DC voltage level VDC of the photogate voltage VPG can be provided during the reset period TRST and it can be a voltage level between a high voltage level VH of the demodulation signals STGA and STGB and a low voltage level VL of the demodulation signals STGA and STGB; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Regarding claim 8, Murase and Jin disclose everything claimed as applied above (see claim 6). However, Murase does not disclose the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors.
Nevertheless, Jin discloses the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors (The second DC voltage level VDC′ of the photogate voltage VPG can be provided during the readout period TRD. The second DC voltage level VDC′ can be lower than the first DC voltage level VDC depending on the potential distribution of the channels; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Regarding claim 16, Murase discloses everything claimed as applied above (see claim 11). However, Murase does not expressly disclose a first voltage or a second voltage is applied to the photogate electrode.
On the other hand, Jin discloses a first voltage or a second voltage is applied to the photogate electrode (A second DC voltage level VDC′ of the photogate voltage VPG during the reset period TRST and the readout period TRD may be different from the first DC voltage level VDC during the integration period TINT. The first DC voltage level VDC during the integration period TINT may be a voltage level between the high voltage level VH and the low voltage level VL of the demodulation signals STGA and STGB. During the reset period TRST and the readout period TRD, the overflow gates OG1 and OG2 are in the turned-on state, and the second DC voltage level VDC′ may be determined based on the potential distribution of the channels formed in the semiconductor substrate; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide a first voltage or a second voltage is applied to the photogate electrode for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Regarding claim 17, Murase and Jin disclose everything claimed as applied above (see claim 16). However, Murase does not disclose the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors.
Nevertheless, Jin discloses the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors (The first DC voltage level VDC of the photogate voltage VPG can be provided during the reset period TRST and it can be a voltage level between a high voltage level VH of the demodulation signals STGA and STGB and a low voltage level VL of the demodulation signals STGA and STGB; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide the first voltage is applied to the photogate electrode during an off period, in which all of the one or more transfer transistors are turned off, and the first voltage is a voltage higher than an off voltage for turning off the transfer transistors for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Regarding claim 18, Murase discloses everything claimed as applied above (see claim 16). However, Murase does not disclose the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors.
Nevertheless, Jin discloses the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors (The second DC voltage level VDC′ of the photogate voltage VPG can be provided during the readout period TRD. The second DC voltage level VDC′ can be lower than the first DC voltage level VDC depending on the potential distribution of the channels; see fig. 7 and paragraphs 0076, 0123).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murase and Jin to provide the second voltage is applied to the photogate electrode during a driving period, in which two or more of the transfer transistors are alternately turned on, and the second voltage is a voltage lower than or equal to an on voltage for turning on the transfer transistors for the purpose of effectively implementing the global shutter function by adequately draining the charge during the periods other than the integration periods.
Citation of Pertinent Art
12. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Mase et al. (US-PGPUB 2023/0048727) discloses the charge distribution region 23 is formed so as to overlap the photogate electrode 41 when viewed from the Z direction and so as not to overlap a plurality of transfer gate electrodes 42, 43, 44, and 45 when viewed from the Z direction.
Contact Information
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA CALDERON whose telephone number is (571)270-3580. The examiner can normally be reached M-F 9:00 AM-5:00 PM.
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/CYNTHIA CALDERON/Primary Examiner, Art Unit 2639 09/02/2026
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