DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The claims recite “high frequency wiring board”. The application teaches what is meant by that term. See:
[0024] In an optical receiver according to an embodiment of the present disclosure, as shown in Figs. 2 to 8, a high frequency wiring board is used instead of a metal wire for all or any number of connections between elements constituting the optical receiver. The above-described conventional optical receiver has a problem in that, in a case where a distance between the elements constituting the optical receiver is away from an optimum value, the length of the metal wire changes and the band of the optical receiver deteriorates. In contrast, in the configuration of the optical receiver according to the embodiment of the present disclosure, the deterioration of the band of the optical receiver can be reduced by using the high frequency wiring board, that is a line in which an impedance line and a high impedance line are combined, for electrical connection between the elements.
The term “high frequency wiring board” will be interpreted consistent with this teaching. See also the high frequency wiring board 222 in FIGS. 2-8.
Claim Rejections - 35 USC § 112 - Indefinite
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, last paragraph recites:
at least one high frequency wiring board that creates at least one of connection between an upper surface of the PD and an upper surface of the bias circuit and connection between the upper surface of the PD and an upper surface of the TIA.
It is not clear which surfaces of the PD and bias circuit are the “upper” surfaces. The Examiner also notes that some of the dependent claims recite a “lower” surface, which is also not clear for the same reason as the “upper” surface. In particular, circuit boards can be oriented in different directions (e.g., turned sideways, turned over, etc.), and it is not clear what surface is the “upper” surface (or the “lower” surface) of these elements. It may be that Applicant intends the “upper” surface to be the surface opposite the substrate on which the component is mounted, and the “lower” surface is the surface adjacent to or closest to the substrate on which the component is mounted. However, this is not clear from the claim language.
Claim 1 recites “at least one high frequency wiring board”, which is interpreted as set forth above under “Claim Interpretation”. However, in the interests of compact prosecution, if this term is not interpreted as set forth above (e.g., if Applicant challenges this interpretation), then it is not clear what particular structure is within the scope of this term. The same is true for the high frequency wiring boards introduced in the dependent claims (e.g., the first and second high frequency wiring boards in claim 3).
Claim 2 recites “lower surface” and “upper surface”. These terms are rejected for the reasons discussed in claim 1.
Claim 3 recites “lower surfaces” “upper surface”. These terms are rejected for the reasons discussed in claim 1.
Claim 6 recites “upper surface” with reference to first and second subcarriers. These terms are rejected for the reasons discussed in claim 1.
Claim 13 recites “upper surface” with reference to the first and second subcarrier. These terms are rejected for the reasons discussed in claim 1.
Claim 14 recites “upper surface” with reference to the first and second subcarrier. These terms are rejected for the reasons discussed in claim 1.
Claim 18 recites “the high frequency wiring board”. It is not clear if this is a reference to the first high frequency wiring board (claim 3), the second high frequency wiring board (claim 3), or the at least one high frequency wiring board (claim 1).
Claims 2-18 are rejected because they depend from one or more of the claims rejected above and they fail to further limit the scope in a manner to overcome the rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0069220 (Yagisawa) at FIG. 2 illustrates an optical receiver including PDs 131, a TIA 132, and a bias circuit applying “bias potential” and ground to TIA 132 and PD 131.
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Regarding the bias circuit in FIG. 2, see also:
[0030] An anode terminal of each of the photo detectors 131 is electrically connected to a signal input terminal of a corresponding TIA 132 by, for example, a wiring pattern. In addition, a cathode terminal of each of the photo detectors 131 is electrically connected to a bias terminal of a corresponding TIA 132 by, for example, a wiring pattern. Here, as a bias potential is applied to the bias terminal of the TIA 132, a bias potential is also applied to the cathode terminal of the photo detector 131. Therefore, when an optical signal is input to the photo detector 131, a current signal representing an intensity of the optical signal is guided to the signal input terminal of the corresponding TIA 132. The TIA 132 converts the current signal generated by the photo detector 131 into a voltage signal, and outputs the voltage signal.
The bias circuit and its connections can also be seen in FIG. 6A:
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See also:
[0051] In FIGS. 6A and 6B, PD represents a photo detector included in the photo detector circuit 11 or the photo detector circuit 21. TIA represents a TIA included in the amplifier circuit 12 or the amplifier circuit 22. The TIA has an input impedance Z.sub.0. C1 represents a capacitive element provided between a bias potential and a ground near the photo detector PD. Although not illustrated, a capacitive element may also be provided near the TIA. A bias line electrically connects a cathode of the photo detector PD and a bias terminal of the TIA. A signal line electrically connects an anode of the photo detector PD and a signal input terminal of the TIA. When the crosstalk is simulated, a distance between two photo detectors PD is 0.25 mm, as illustrated in FIG. 6B.
FIGS. 8A and 8B illustrate that the PD 21, TIA 22, and bias circuit 24, 31, 32, 33 can be mounted on the same carrier (i.e., circuit board 20).
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See also FIG. 8C. See also:
[0066] However, in the optical receiver module 3 according to the third embodiment, on the other surface (i.e., a reverse surface) of the circuit board 20, a bias electrode 31 is formed so as to include a region in which a plurality of cathode wiring patterns 24c are formed. The bias electrode 31 is represented with a broken line in FIG. 8A. On the reverse surface of the circuit board 20, a ground electrode 32 is formed so as to surround the bias electrode 31. The bias electrode 31 and the ground electrode 32 are electrically coupled by one or a plurality of capacitive elements. In this example, as illustrated in FIG. 8B, a capacitive element C1 is provided near the photo detector PD, and a capacitive element C2 is provided near the TIA.
[0067] Each of the cathode wiring patterns 24c is electrically connected to the bias electrode 31. In this example, each of the cathode wiring patterns 24c is electrically connected to the bias electrode 31 by a via 33. Herein, a "via" includes a through-hole.
This also illustrates the circuit board 20 making a connection between a surface of the PD 21 and a surface of the TIA 22 via connector 24c and via 33.
However, Yagisawa does not appear to teach the high frequency wiring board as recited in the claim.
JP 2003-197952 (Mitsubishi; cited by Applicant) at FIG. 1 illustrates an optical receiver including a PD 1 and an amplifier 2, all mounted on substrates.
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See also:
[0034] FIG. 1 is a diagram showing a configuration of an optical signal receiving module according to a first embodiment of the present invention, The optical signal receiving module exemplified here is used on the receiving side of an optical communication system and has a function of efficiently converting an input optical signal into an electric signal, as in the conventional one shown in FIG. 11.
[0035] In FIG. 1, reference numeral 1 denotes a surface-incident type PD (PhotoDiode) device: 11, a light-receiving portion of the PD device 1; 12, a P-electrode of the PD device 1; Reference numeral 13 denotes N-electrodes as bias voltage input terminals of the PD device 1; 2, a Integrated Circuits chip; 21, signal input electrodes of the IC chip 2; and 2223, ground electrodes provided on the upper surface of the IC chip 2. The N-electrode 13 of the PD element 1 is provided on the entire back surface of the PD element 1. Reference numeral 3 denotes a chip capacitor, and 41, 42, 43, 44, 45 denotes a wire. Reference numeral 5 denotes an insulating substrate, specifically, a ceramic substrate, on the upper surface of which a wiring pattern 51 is formed.
Paragraph [0035] also teaches wire connections between elements and the use of bias signals. The conductors carrying the bias signals are part of a bias circuit, although the particular structure of the bias circuit is not illustrated in FIG. 1.
FIG. 1 also illustrates a wire connection 45 between the capacitor 3 and the PD 1, and wire connections 41-43 between the PD 1 and the amp 2. These are discussed in more detail in paragraph [0037]:
[0037] 0ne end of a wire 45 and one end of a wire 44 are connected to the upper electrode of the chip capacitor 3. The other end of the wire 45 is connected to the wiring pattern 51 of the ceramic substrate 5, and electrically connects the upper electrode of the chip capacitor 3 and the wiring pattern 51 of the ceramic substrate 5. The other end of the wire 44 is connected to a PD bias circuit (not shown) SO that a bias voltage applied from the PD bias circuit can be applied to the N electrode 13 of the PD element 1 through the wiring pattern 51 of the ceramic substrate 5.
However, this does not appear to teach the particular high frequency wiring board recited in the claims.
JP 2019-192696 (Panasonic; cited by Applicant) at FIG. 1 illustrates the general structure of a receiver including a PD 103 and an amplifier 104, both mounted on a substrate 102.
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However, it does not appear to teach a bias circuit as recited in the claims, and it does not appear to teach a high frequency wiring board as recited in the claims.
US 2018/0006728 (Yuda) at FIG. 3 illustrates an optical receiver 152 including a PD, a TIA 81, and a bias circuit including control unit 83.
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See also:
[0074] Referring to FIG. 3, the optical transceiver 101 includes a burst transmitting unit 151, a receiving unit 152, and an integrator circuit (computing unit) 84. The burst transmitting unit 151 includes a pre-amplifier 86, an output buffer circuit (modulation current supply circuit) 87, a bias current supply circuit 88, and a light emitting circuit 89. The light emitting circuit 89 includes a light emitting element LD and inductors L1 and L2. The receiving unit 152 includes a light receiving element PD, a TIA (transimpedance amplifier) 81, an LIA (limiting amplifier) 82, a bias control unit (adjusting unit) 83, and an output buffer 85.
See also FIG. 4.
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This illustrates the bias control unit 83 in more detail.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARREN WOLF whose telephone number is (571)270-3378. The examiner can normally be reached Monday through Friday, 7:00 AM to 3:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KENNETH N. VANDERPUYE can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARREN E WOLF/Primary Examiner, Art Unit 2634
Prosecution Insights