Prosecution Insights
Last updated: October 01, 2026
Application No. 18/881,021

FLEXIBLE CIRCUIT BOARD, DISPLAY MODULE AND DISPLAY DEVICE

Non-Final OA §102§103§112
Filed
Jan 03, 2025
Priority
Jun 13, 2023 — CN 202310700882.1 +1 more
Examiner
SREEVATSA, SREEYA
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
254 granted / 295 resolved
+26.1% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
315
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
34.3%
-5.7% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 295 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending in this application. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 06/25/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Flexible circuit board of claims 1-20, Application processor of claim 1, Display driver integrated circuit of claim 1, Display panel of claim 5, End position of claim 5, Display module of claim 9, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. Claim Objections Claims 1 and 9 are objected to because of the following informalities: Claim 1 line 9, “the ground” should be –a ground--. Claim 9 line 2, “according to any one of claims 1” should be --according to claim 1--. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 7-8 and 16-17 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 recites “a first binding area that is located at an end position on one side of the flexible circuit board”. Claim 7, which depends on claim 5, recites a broader limitation “the first binding area is located at the end portion of the flexible circuit board”. This is improper. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements. Claims 8, 16 and 17 are rejected for the same reason as stated above for claim 7. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 9-12 and 18-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Xiao (US 20200349877 A1). Regarding claim 1, Xiao teaches a flexible circuit board ([0001], a field of display technologies), comprising an electrostatic discharge protection circuit (e.g. voltage delay unit 366, fig.3), an electrostatic discharge detection circuit (e.g. third transistor 363 and fourth transistor 364, fig.3) and a switch circuit (e.g. first transistor 361, second transistor 362, fifth transistor 365, fig.3); an input end of the electrostatic discharge detection circuit is coupled to an output end of the electrostatic discharge protection circuit (e.g. gate of 363 and 364 is connected to output of 366, fig.3), and an output end of the electrostatic discharge detection circuit is coupled to a control end of the switch circuit (e.g. output of 363 and 364 is connected to gate of 365, fig.3); a first end of the switch circuit, a reset signal output end of an application processor, and a reset signal input end of a Display Driver Integrated Circuit (DDIC) are coupled to a first node (e.g. gate and source of 361, output of external signal input terminal 34 and input of display circuit 33 are all connected at a point on line 331, fig.3), and a second end of the switch circuit is coupled to the ground (e.g. one end of 365 is connected to VSS, fig.3). Regarding claim 2, Xiao teaches the flexible circuit board according to claim 1, wherein the switch circuit comprises a first switch transistor (e.g. fifth transistor 365, fig.3), a control electrode of the first switch transistor is coupled to the output end of the electrostatic discharge detection circuit (e.g. gate of 365 is coupled to output of 363 and 364, fig.3), a first electrode of the first switch transistor is coupled to the first node (e.g. drain of 365 is coupled to node at output of 34 via 361, fig.3), and a second electrode of the first switch transistor is coupled to the ground (e.g. source of 365 is coupled to VSS, fig.3). Regarding claim 3, Xiao teaches the flexible circuit board according to claim 2, wherein the first switch transistor is an N-type transistor ([0083], the fifth transistor 365 is an N-type transistor). Regarding claim 9, Xiao teaches a display module (abstract, present invention discloses an electrostatic protection device and a display panel), comprising a display panel and the flexible circuit board according to claim 1 (abstract, present invention discloses an electrostatic protection device and a display panel). Regarding claim 10, Xiao teaches a display device, comprising the display module according to claim 9 ([0001], a field of display technologies). Regarding claim 11, it is rejected for the same reasons as stated above for claim 2. Regarding claim 12, it is rejected for the same reasons as stated above for claim 3. Regarding claim 18, it is rejected for the same reasons as stated above for claim 2. Regarding claim 19, it is rejected for the same reasons as stated above for claim 3. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 20200349877 A1). Regarding claim 4, Xiao teaches the flexible circuit board according to claim 1. Xiao does not teach, wherein the flexible circuit board further comprises a first resistor and a first capacitor, the first resistor is coupled between the reset signal output end of the application processor and the first node, a first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the ground. It would have been an obvious matter of design choice to a first resistor and a first capacitor, the first resistor is coupled between the reset signal output end of the application processor and the first node, a first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the ground, since the applicant has not disclosed that a first resistor and a first capacitor solves any problem or is for a particular reason. It appears that the claimed invention would perform equally well with a first resistor and a first capacitor, the first resistor is coupled between the reset signal output end of the application processor and the first node, a first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the ground, as it provides the advantage of limiting current and voltages according to safety parameters. Regarding claim 13, it is rejected for the same reasons as stated above for claim 4. Regarding claim 20, it is rejected for the same reasons as stated above for claim 4. Claims 5-8 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 20200349877 A1), and further in view of Ueda (US 5838412 A). Regarding claim 5, Xiao teaches the flexible circuit board according to claim 1. Xiao does not teach, wherein the flexible circuit board comprises a first binding area that is located at an end position on one side of the flexible circuit board and used for binding with a display panel, and at least a portion of the flexible circuit board adjacent to the first binding area comprises a first ground layer, a wiring layer, and a second ground layer that are laminated sequentially in that order. Ueda teaches in a similar field of endeavor of display device and flexible circuit, a first binding area that is located at an end position on one side of the flexible circuit board and used for binding with a display panel (column 11 lines 33-47, eight conductor layers L1 to L8 parallel to the liquid crystal display element PNL and mounting the wiring of peripheral circuits and electronic components on this portion), and at least a portion of the flexible circuit board adjacent to the first binding area comprises a first ground layer (column 11 lines 33-47, conductor layer L1 is used for a component pad and grounding, L2 is used for a gray-scale reference voltage Vref), a wiring layer (column 11 lines 33-47, L5 is used for lead-out wiring which is the second wiring group), and a second ground layer that are laminated sequentially in that order (column 11 lines 33-47, L6 is used for a gray-scale reference voltage Vref). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the flexible circuit board comprises a first binding area that is located at an end position on one side of the flexible circuit board and used for binding with a display panel, and at least a portion of the flexible circuit board adjacent to the first binding area comprises a first ground layer, a wiring layer, and a second ground layer that are laminated sequentially in that order in Xiao, as taught by Ueda, as it provides the advantage of reducing connection resistance and enabling flexible wiring. Regarding claim 6, Xiao and Ueda teach the flexible circuit board according to claim 5, wherein the first ground layer and the second ground layer are electrically connected through a via hole in the wiring layer (Ueda, e.g. VIA fig.21B). Regarding claim 7, it is rejected for the same reason as stated above for claim 5. Regarding claim 8, Xiao and Ueda teach the flexible circuit board according to claim 7, wherein a portion of an area of the flexible circuit board that is adjacent to the first binding area (Ueda, column 11 lines 33-47, eight conductor layers L1 to L8 parallel to the liquid crystal display element PNL and mounting the wiring of peripheral circuits and electronic components on this portion) comprises the first ground layer (Ueda, column 11 lines 33-47, conductor layer L1 is used for a component pad and grounding, L2 is used for a gray-scale reference voltage Vref), the wiring layer (Ueda, column 11 lines 33-47, L5 is used for lead-out wiring which is the second wiring group) and the second ground layer that are laminated sequentially in that order (Ueda, column 11 lines 33-47, L6 is used for a gray-scale reference voltage Vref). Regarding claim 14, it is rejected for the same reasons as stated above for claim 5. Regarding claim 15, it is rejected for the same reasons as stated above for claim 6. Regarding claim 16, it is rejected for the same reasons as stated above for claim 7. Regarding claim 17, it is rejected for the same reasons as stated above for claim 8. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 08/14/2026
Read full office action

Prosecution Timeline

Jan 03, 2025
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
90%
With Interview (+3.8%)
2y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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