Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 6, 2026 has been entered.
Status of Claims
- Applicant' s Amendment filed March 6, 2026 is acknowledged.
- Claim(s) 1, 12 is/are amended
- Claim(s) 2, 13 is/are canceled
- Claim(s) 1, 3-12, 14-15 is/are pending in the application.
Examiner respectfully reminds Applicant that 37 CFR 1.121 (c)(1) indicates “All of the claims presented in a claim listing shall be presented in ascending numerical order. Consecutive claims having the same status of "canceled" or "not entered" may be aggregated into one statement (e.g., Claims 1–5 (canceled)). The claim listing shall commence on a separate sheet of the amendment document and the sheet(s) that contain the text of any part of the claims shall not contain any other part of the amendment.” In Applicant’s response dated March 6, 2026, the claims were not on separate sheets as indicated on page one of Applicants response:
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Future submissions should comply with 37CFR 1.121 (c)(1).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
The application is a U.S. National Phase Application of PCT International Application No. PCT/CN2024/095280 filed on May 24, 2024.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
Applicant’s amendment of the claims in the response dated December 18, 2025, to avoid interpretation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is acknowledged. As best understood by Examiner, applicant has: amended the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function), based the last paragraph of page 7 of Applicant’s original specification where “a driver chip DIC” is disclosed. Examiner notes that Applicant’s original written description describes the various “unit”/”module” (s) with respect to their function without having provided any drawings of specific circuits nor specific written description of circuit components which accomplish the disclosed functions.
However, in view of MPEP guidance that states “The following are examples of structural terms that have been found not to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, paragraph 6: "circuit," "detent mechanism," "digital detector," "reciprocating member," "connector assembly," "perforation," "sealingly connected joints," and "eyeglass hanger member." See Mass. Inst. of Tech., 462 F.3d at 1355-1356, 80 USPQ2d at 1332 (the court found the recitation of "aesthetic correction circuitry" sufficient to avoid pre-AIA 35 U.S.C. 112, paragraph 6, treatment because the term circuit, combined with a description of the function of the circuit, connoted sufficient structure to one of ordinary skill in the art.)” Examiner withdraws the interpretation under 35 USC 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3, 6, 9, 11-12, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al, Chinese Patent Publication No. CN201910576366 in view of Choi et al, U.S. Patent Publication No. 20220327999, Kwa et al, U.S. Patent Publication No. 20210118393 and Watsuda, U.S. Patent Publication No. 20160093260.
Consider claim 1, Qian teaches a display (see Qian paragraph 0023 where organic light emitting display is disclosed), comprising a driver chip (see Qian paragraph 0023 where driving chip120) and a display panel (see Qian paragraph 0019 where display panel comprising: a plurality of pixel circuits 110, a plurality of data lines (D11, D12, D21, D22, D31, D32, D41, D42, ...) and a plurality of scanning lines (S1, S2, S3, S4, S5, S6, ...)),
wherein the driver chip comprises a data signal output circuit (see Qian paragraph 0028 and figure 8, element 120, 121), and
the display panel comprises N rows of sub-pixels (see Qian figure 8, element 113, 114 where pixel 113 corresponds to nth row and 114 corresponds to n=1th row), and
a scanning stage of each row of sub-pixels comprises a data writing period (see Qian figure 9, element t13 and paragraph 0051) and a reserved period immediately after the data writing period (see Qian figure 9, element t14 and paragraph 0052),
t
wherein the reserved period comprises a light-emitting period immediately after the data writing period (see Qian figure 9, element t14 and paragraph 0052 where fourth transistor T4 of the first pixel circuit driving the organic light emitting diode D1 to emit light) and an idle period immediately after the light-emitting period (Admitted Prior art because Applicant failed to properly traverse the officially noticed items/features as required by MPEP 2144.03 D. Examiner took Official Notice in Office Action dated January 16, 2026, that it is well known in the display art to have a horizontal blanking period before and after each row so as to comply with display data standards as evidenced by Kwa paragraph 0047. One of ordinary skill would have been motivated to have an idle period immediately after a light-emitting period so as to comply with display data standards);
Specifically, the scanning signal input terminal Scan 1 of the first pixel circuit 113 inputs a second low-level scanning pulse signal, and the data signal input terminal Vdata 1 of the first pixel circuit 113 inputs the data voltage. In the fourth phase t14, the first pixel circuit 113 enters a light emitting phase (equivalent to a reserved period after the data writing period). It can be seen from FIG. 9 that after the Scan 1 is in the ON state in the third stage t 13, before the Scan 2 is in the ON state (this stage is also equivalent to the reserved time period after the data writing period), the data signal input terminal Vdata 2 of the second pixel circuit 114 starts to input the data voltage V 2 (equivalent to setting the data signal output circuit in the on state in the reserved time period of the n
row of sub-pixels). In the fourth phase t 14, the second pixel circuit 114 enters and completes the data writing phase. Specifically, the scan signal input terminal Scan 2 of the second pixel circuit 114 inputs a second low level scanning pulse signal, and the second pixel circuit 114 is a data voltage signal input terminal for inputting a data voltage.
Qian is silent regarding the data signal output circuit is configured to be in an OFF state during the data writing period of an nth row of sub-pixels and to be switched from the OFF state to an ON state during the reserved period of the nth row of sub-pixels, the data signal output circuit is further configured to be in the OFF state during the light-emitting period of the nth row of sub-pixels and to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels.
It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0.
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In a related field of endeavor, Choi teaches turning off pixels in display areas so as to reduce an amount of power consumed (see Choi paragraph 0050, 0055).
Choi is silent regarding data signal output circuit is configured to be in an OFF. In a related field of endeavor, Kwa teaches turning off column drivers so as to save power (see Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5).
One of ordinary skill would have been motivated to have modified Qian with the teachings of Choi and Kwa to have turned off a column driver for a row that was not being updated so as to reduce an amount of power consumed using known techniques with predictable results. Further, turning off Qian during a period after Scan 1 is in the ON state in the third stage t 13, before the Scan 2 is in the ON state (this stage is also equivalent to the reserved time period after the data writing period) would correspond to completing scan of row 1 and before start of scan of row 2. Combining the teachings of Choi and Kwa with Qian would result in having the data signal output circuit is further configured to be in the OFF state during the light-emitting period of the nth row of sub-pixels and to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels (see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052). Specifically one of ordinary skill would recognize that turning off and turning on scan/data driver(s) would necessarily occur at appropriate times for pixels which are to display data as taught by Choi and Kwa.
Qian is silent regarding wherein the n+1th row of sub-pixels is configured for displaying in white.
In a related field of endeavor, Watsuda teaches rows of subpixels may display in black, white or gray-level so as to provide monochrome display (see Watsuda paragraph 0060). One of ordinary skill would have been motivated to have modified Qian to have rows of subpixels display in black, white or gray-level so as to provide monochrome display using known techniques with predictable results.
Consider claim 3, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1 and further teaches wherein the scanning stage further comprises a preparation period immediately before the data writing period (see Qian figure 9, element t12 and paragraph 0050);
the data signal output circuit is further configured to be switched from the OFF state to the ON state during the reserved period of the nth row of sub-pixels, to output the stable first data signal during the preparation period of the n+1th row of sub-pixels and to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels (see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052).
Consider claim 5, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1 and further teaches wherein a moment at which the data signal output circuit is switched from the OFF state to the ON state during the reserved period of the nth row of sub-pixels is located between a last one-fifth period and a last one-tenth period of the reserved period (It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0 and Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5).
Consider claim 6, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1 and further teaches wherein the first data signal is a data signal corresponding to a maximum display brightness of the display panel (see Watsuda paragraph 0060 where for example white may correspond to maximum display brightness).
Consider claim 9, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1 and further teaches wherein the display further comprises a selection circuit (see Qian figure 8, element 123);
the selection circuit is configured to be in the OFF state during the reserved period of the nth row of sub-pixels and in the ON state during the data writing period of the nth row of sub-pixels, to enable the data signal output circuit to provide the stable first data signal to the n+1th row of sub-pixels (see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052).
Consider claim 11, Qian as modified by Choi, Kwa and Watsuda teaches a display device, comprising the display according to claim 1 (see Qian paragraph 0023 where organic light emitting display is disclosed and rejection of claim 1 above).
Consider claim 12, Qian teaches a control method for a display (see Qian paragraph 0023 where organic light emitting display is disclosed), the display comprising a driver chip (see Qian paragraph 0023 where driving chip120) and a display panel (see Qian paragraph 0019 where display panel comprising: a plurality of pixel circuits 110, a plurality of data lines (D11, D12, D21, D22, D31, D32, D41, D42, ...) and a plurality of scanning lines (S1, S2, S3, S4, S5, S6, ...)),
wherein the driver chip comprises a data signal output circuit (see Qian paragraph 0028 and figure 8, element 120, 121) and
the display panel comprises N rows of sub-pixels (see Qian figure 8, element 113, 114 where pixel 113 corresponds to nth row and 114 corresponds to n=1th row), and
a scanning stage of each row of sub-pixels comprises a data writing period (see Qian figure 9, element t13 and paragraph 0051) and a reserved period immediately after the data writing period (see Qian figure 9, element t14 and paragraph 0052);
the method comprises
to provide a stable first data signal to an n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels, 0 < n <N (see Qian figure 9 and paragraph 0052),
wherein the n+1th row of sub-pixels is configured for displaying in white,
wherein the reserved period comprises a light-emitting period immediately after the data writing period (see Qian figure 9, element t14 and paragraph 0052 where fourth transistor T4 of the first pixel circuit driving the organic light emitting diode D1 to emit light) and an idle period immediately after the light-emitting period (Admitted Prior art because Applicant failed to properly traverse the officially noticed items/features as required by MPEP 2144.03 D. Examiner took Official Notice in Office Action dated January 16, 2026, that it is well known in the display art to have a horizontal blanking period before and after each row so as to comply with display data standards as evidenced by Kwa paragraph 0047. One of ordinary skill would have been motivated to have an idle period immediately after a light-emitting period so as to comply with display data standards);
Specifically, the scanning signal input terminal Scan 1 of the first pixel circuit 113 inputs a second low-level scanning pulse signal, and the data signal input terminal Vdata 1 of the first pixel circuit 113 inputs the data voltage. In the fourth phase t14, the first pixel circuit 113 enters a light emitting phase (equivalent to a reserved period after the data writing period). It can be seen from FIG. 9 that after the Scan 1 is in the ON state in the third stage t 13, before the Scan 2 is in the ON state (this stage is also equivalent to the reserved time period after the data writing period), the data signal input terminal Vdata 2 of the second pixel circuit 114 starts to input the data voltage V 2 (equivalent to setting the data signal output circuit in the on state in the reserved time period of the n
row of sub-pixels). In the fourth phase t 14, the second pixel circuit 114 enters and completes the data writing phase. Specifically, the scan signal input terminal Scan 2 of the second pixel circuit 114 inputs a second low level scanning pulse signal, and the second pixel circuit 114 is a data voltage signal input terminal for inputting a data voltage.
Qian is silent regarding controlling the data signal output circuit to be in an OFF state during the data writing period of an nth row of sub-pixels; and controlling the data signal output circuit to be switched from the OFF state to an ON state during the reserved period of the nth row of sub-pixels, controlling the data signal output circuit to be switched from the OFF state to the ON state during the reserved period of the nth row of sub-pixels, comprises: controlling the data signal output circuit to be in the OFF state during the light-emitting period of the nth row of sub-pixels; and controlling the data signal output circuit to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels.
It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0.
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In a related field of endeavor, Choi teaches turning off pixels in display areas so as to reduce an amount of power consumed (see Choi paragraph 0050, 0055).
Choi is silent regarding data signal output circuit is configured to be in an OFF. In a related field of endeavor, Kwa teaches turning off column drivers so as to save power (see Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5).
One of ordinary skill would have been motivated to have modified Qian with the teachings of Choi and Kwa to have turned off a column driver for a row that was not being updated so as to reduce an amount of power consumed using known techniques with predictable results. Further, turning off Qian during a period after Scan 1 is in the ON state in the third stage t 13, before the Scan 2 is in the ON state (this stage is also equivalent to the reserved time period after the data writing period) would correspond to completing scan of row 1 and before start of scan of row 2. Combining the teachings of Choi and Kwa with Qian would result in having the data signal output circuit is further configured to be in the OFF state during the light-emitting period of the nth row of sub-pixels and to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels (see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052). Specifically one of ordinary skill would recognize that turning off and turning on scan/data driver(s) would necessarily occur at appropriate times for pixels which are to display data as taught by Choi and Kwa.
Qian is silent regarding wherein the n+1th row of sub-pixels is configured for displaying in white.
In a related field of endeavor, Watsuda teaches rows of subpixels may display in black, white or gray-level so as to provide monochrome display (see Watsuda paragraph 0060). One of ordinary skill would have been motivated to have modified Qian to have rows of subpixels display in black, white or gray-level so as to provide monochrome display using known techniques with predictable results.
Consider claim 14, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 12 and further teaches wherein a moment at which the data signal output circuit is switched from the OFF state to the ON state during the reserved period of the nth row of sub-pixels is located between a last one-fifth period and a last one-tenth period of the reserved period (It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0 and Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5).
Consider claim 15, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 12 and further teaches wherein the first data signal is a data signal corresponding to a maximum display brightness of the display panel (see Watsuda paragraph 0060 where white may correspond to maximum display brightness).
Claim(s) 4, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al, Chinese Patent Publication No. CN201910576366, Choi et al, U.S. Patent Publication No. 20220327999, Kwa et al, U.S. Patent Publication No. 20210118393 and Watsuda, U.S. Patent Publication No. 20160093260 in view of Qu et al, U.S. Patent Publication No. 20140168187.
Consider claim 4, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1 and further teaches wherein the driver chip further comprises an enabling signal circuit (see Kwa figure 2A, element 112a, figure 6, element 608 and paragraphs 0025, 0027, 0031, 0043, 0069 where some of the column drivers may be off or not active and power can be saved);
the data signal output circuit is further configured to be in the OFF state during the data writing period of the nth row of sub-pixels based on control of the first potential enabling signal; to be switched from the OFF state to the ON state during the reserved period of the nth row of sub-pixels based on control of the second potential enabling signal, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels (see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052).
Qian/Choi/Kwa/Watsuda is silent regarding the enabling signal circuit is configured to provide a first potential enabling signal to the data signal output circuit during the data writing period of the nth row of sub-pixels; and provide a second potential enabling signal to the data signal output circuit during the reserved period of the nth row of sub-pixels.
In a related field of endeavor, Qu teaches a column driver enable signal having two different potential levels that is transmitted from a TCON so as to instruct a column driver whether it should currently drive a display panel (see Qu figure 4, CD enable 406 and paragraph 0025).
One of ordinary skill would have been motivated to have modified Qian/Choi/Kwa with the teachings of Qu to have a column driver enable signal having two different potential levels that is transmitted from a TCON so as to instruct a column driver whether it should currently drive a display panel using known techniques with predictable results.
Consider claim 10, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 9 and further teaches wherein the driver chip further comprises a selection signal output circuit (implicit see Qian paragraph 0030 where a first gating switch 123 off, and first gating switch 123 is turned on,);
the selection circuit is further configured to be in the OFF state during the reserved period of the nth row of sub-pixels based on control of the first potential selection signal; and in the ON state during the data writing period of the nth row of sub-pixels based on control of the second potential selection signal, to enable the data signal output circuit to provide the stable first data signal to the n+1th row of sub-pixels(see Choi paragraph 0050, 0055 and Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Qian figure 9 and paragraph 0052).
Qian is silent regarding the selection signal output circuit is configured to provide a first potential selection signal to the selection circuit during the reserved period of the nth row of sub-pixels; and provide a second potential selection signal to the selection circuit during the data writing period of the n+1th row of sub-pixels.
In a related field of endeavor, Qu teaches an enable signal having two different potential levels so as to instruct a device whether it should turn on or off (see Qu figure 4, CD enable 406 and paragraph 0025).
One of ordinary skill would have been motivated to have modified Qian to have an enable signal having two different potential levels so as to instruct a switch whether it should turn on or off using known techniques with predictable results.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al, Chinese Patent Publication No. CN201910576366, Choi et al, U.S. Patent Publication No. 20220327999, Kwa et al, U.S. Patent Publication No. 20210118393 and U.S. Patent Publication No. 20160093260 in view of Takahara, U.S. Patent Publication No. 20070080905.
Consider claim 7, Qian as modified by Choi, Kwa and Watsuda teaches all the limitations of claim 1. Qian is silent regarding wherein the display further comprises a voltage circuit; the voltage circuit is configured to provide a second data signal to the nth row of sub-pixels during the data writing period of the nth row of sub-pixels.
In a related field of endeavor, Takahara teaches a voltage circuit; the voltage circuit is configured to provide a second data signal to the nth row of sub-pixels during the data writing period of the nth row of sub-pixels so as to achieve black display (see Takahara figure 375(a), element 3752, 3751, 19 and paragraphs 1296-1299).
One of ordinary skill would have been motivated to have modified Qian to have a voltage circuit; the voltage circuit is configured to provide a second data signal to the nth row of sub-pixels during the data writing period of the nth row of sub-pixels so as to achieve black display using known techniques with predictable results.
Consider claim 8, Qian as modified by Choi, Kwa, Watsuda and Takahara teaches all the limitations of claim 7 and further teaches wherein the second data signal is a data signal corresponding to a minimum display brightness of the display panel (see Choi paragraph 0050, 0055, Kwa paragraphs 0027 0031, figure 2B, element 118a, 116a, figure 5 and Takahara figure 375(a), element 3752, 3751, 19 and paragraphs 1296-1299).
Response to Arguments
Applicant's arguments filed March 6, 2026 have been fully considered but they are not persuasive.
Examiner respectfully notes that Applicant’s remarks dated March 6, 2026, are not considered persuasive in-part because as noted the in the office action dated January 16, 2026, spanning pages 7-8 and page 13, the Officially Noticed items/features are considered to be admitted prior art because Applicant failed to properly traverse the officially noticed items/features as required by MPEP 2144.03 D where “To adequately traverse such a finding, an applicant must specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art. See 37 CFR 1.111(b).”.
Regarding Applicant’s assertion that “Qian, Choi and Kwa all do not disclose the feature “the n+1th row of sub-pixels(which is provided with the stable first data signal during its data writing period) are configured for displaying in white””, Examiner respectfully notes that Watsuda has been cited as fairly teaching or suggesting this feature.
Regarding Applicant’s assertion that “Qian does not disclose the feature "the reserved period of each row of sub- pixels comprises a light-emitting period immediately after the data writing period and an idle period immediately after the light-emitting period, the data signal output circuit is further configured to be in the OFF state during the light-emitting period of the nth row of sub- pixels, and to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels", since the Examiner has acknowledged that Qian does not disclose the feature "the data signal output circuit is configured to be in an OFF state during the data writing period of an nth row of sub-pixels and to be switched from the OFF state to an ON state during the reserved period of the nth row of sub-pixels".”, Examiner respectfully notes that the above articulated rejection has rejected these features as obvious in view of the teachings of Choi and Kwa.
Regarding Applicant’s assertion that “Choi and Kwa do not disclose the above features either. Choi and Kwa all throughout fail to give any literal description at all. Choi just teaches addressing pixel rows 315 in only some of the display areas so as to reduce an amount of power consumed (see paragraphs [0050] and [0055] mentioned by the Examiner), and Kwa discloses that timing controller TCON 112a can be configured to update display panel 108a by sending control signals to plurality of row drivers 116a and plurality of column drivers 118a in a column-wise manner rather than a row-wise manner. This allows some of the column drivers to be off or not active and power can be saved. That is, only one or two columns might need to update the RGB information and the rest of the columns do not need to update the RGB information so they can be off or not active during the update and power can be saved. This can provide primarily battery life improvement (see paragraph [0031] mentioned by the Examiner). Thus, Choi and Kwa do not disclose or teach that the reserved period of each row of sub-pixels after a data writing period includes a light-emitting period immediately and an idle period immediately after the light-emitting period, the data signal output circuit is further configured to be in the OFF state during the light-emitting period of the nth row of sub- pixels, and to be switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels, to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels. More specifically, Choi and Kwa both fail to disclose an operation state of a data signal output circuit after the data writing period in a scanning stage of each row of sub-pixels, i.e. it is in the OFF state during the light-emitting period of the nth row of sub-pixels, and is switched from the OFF state to the ON state during the idle period of the nth row of sub-pixels. Especially, Choi and Kwa BOTH do NOT explicitly mention a data signal output circuit at all. “, Examiner respectfully reminds Applicant that the claim has been rejected as obvious in view of the combined teachings of the cited prior arts.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Specifically, Examiner has combined the teachings of Choi, Kwa and Watsuda with Qian as articulated in the rejection above. Applicant’s assertion that “it is impossible for a person skilled in the art, without inventive effort, to achieve the technical solution of claim 1 of the present application based on Qian alone, or in any proper combination with Choi and Kwa”, is unpersuasive.
Specifically as indicated above with respect to Qian, It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0.
It can be seen from the teachings of Qian that the input of the data voltage V2 in the second row of pixels is independent of whether the first row of pixels is input to the data voltage V1, regardless of whether the first row of pixels display an image, i.e. black or data voltage V1 is 0.
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Further, Examiner notes that one of ordinary skill would recognize that turning off and turning on scan and/or data driver(s) would necessarily occur at appropriate times for pixels which are to display data as disclosed by Choi and Kwa.
One of ordinary skill would easily recognize that the period of Qian after Scan 1 is in the ON state in the third stage t 13, before the Scan 2 is in the ON state (this stage is also equivalent to the reserved time period after the data writing period) would correspond to completing scan of row 1 and before start of scan of row 2.
Further, one of ordinary skill would readily recognize that turning on would necessarily occur prior to scanning a subsequent row. As articulated above an idle period immediately after the light-emitting period (which is Admitted Prior art because Applicant failed to properly traverse the officially noticed items/features as required by MPEP 2144.03 D.) would have been an obvious time to turn on a driver so as to provide signals at a next row.
It is respectfully submitted that given the level of skill of the ordinary workman in the art of image display, as evidenced by the references cited in the instant application, one of ordinary skill could clearly provide the recited features without inventive inspiration. To argue otherwise, is to assume an unsupportably low evaluation of the skill of the ordinary workman.
Applicant appears to insist that absent a verbatim recitation of every structure and function found in the claim, Examiner’s cited prior art cannot ground an obviousness rejection. To the contrary, not even anticipatory rejections require an identical and exactly corresponding recitation of the structures and functions (35 USC § 102; MPEP § 2131, citing In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990)), and the correspondence requirements between the structures and functions claimed and those disclosed in the cited prior art are even less rigorous in the instant application, given that the controverted rejections are grounded in 35 USC § 103.
Contrary to Applicants' assertion, there is no bright line rule defining a prima facie case of obviousness under 35 USC § 103 (MPEP § 2144, 1st paragraph). Further, establishment of obviousness sufficient to shift the burden of production to the Applicants can be by reliance on legal precedent, implicit disclosure, common knowledge, or scientific theory as well as by disclosures in cited prior art references (MPEP § 2144.01-2144.04). Further, inferences that one of ordinary skill in art might reasonably draw from the cited prior art references can be relied upon as part of the prima facie showing of the instant invention's obviousness (MPEP § 2144.01).
To the degree that Applicant’s arguments require an express statement of the claimed features within the cited prior art, Applicant appears to be applying a standard beyond that of the 35 USC § 102 anticipation standard to refute a 35 USC § 103 obviousness rejection (MPEP § 2131, finding anticipation does not require verbatim recitation of the material features in the cited references).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Miyazawa, U.S. Patent Publication No. 20070128583 (electro-optical device), Hong et al, U.S. Patent Publication No. 20140160182 (display device), Kim et al, U.S. Patent Publication No. 20180061320 (organic light emitting diode display), Kim et al, U.S. Patent Publication No. 20180342217 (figure 10, figure 15), Bae, U.S. Patent Publication No. 20200098080 (display)
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/Dorothy Harris/Primary Examiner, Art Unit 2625