Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 24, 2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In line 2 of claim 7, “a third transistor” is indefinite because there is no “first” or “second” transistor set forth prior the “third transistor”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (US 2023/010665 or CN 114566110 A)
As per claim 1 Chen et al discloses: A drive control circuit of a light-emitting drive circuit, comprising:
at least two groups of first drive circuits 10 & 20, connected to at least two groups of input control terminals INPUT 1 to INPUT N, at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O; Figure 2 & 5-6; [0074] Each level conversion sub-circuit 10 may further be connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals.}, and an output terminal OUTPUT 1 to OUTPUT N configured to connect to the light-emitting drive circuit {[0074] Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Note: GOA (i.e. Gate driver On Array) connects to a display panel (see [0068]) which has a light-emitting drive circuit.};
wherein levels of drive power signals provided by the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O} are different {[0075] In addition, the first power supply signals provided by the first power supply terminals connected to the respective level conversion sub-circuits 10 may be at different levels, and the second power supply signals provided by the second power supply terminals connected to the respective level conversion sub-circuits 10 may be at different levels.}, the at least two groups of input control terminals INPUT 1 to INPUT N are in one-to-one correspondence with the at least two groups of first drive circuits 10 & 20 {figures 2 & 5}, the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O} are in one-to-one correspondence with the at least two groups of first drive circuits 10 & 20 {figures 2 & 5-6}, and the at least two groups of input control terminals INPUT 1 to INPUT N are in one-to-one correspondence with the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O};
wherein each group of the at least two groups of first drive circuits 10 & 20 is configured to control, in response to an input control signal provided by a corresponding group of input control terminals, an on-off of a corresponding group of drive power terminals and the output terminal OUTPUT 1 to OUTPUT N { [0074] Each level conversion sub-circuit 10 may further be connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals. Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Each level conversion sub-circuit 10 may be configured to, in response to the received input control signal, transmit a first power supply signal provided by one of the first power supply terminals or a second power supply signal provided by one of the second power supply terminals to each of the connected output signal terminals. & [0101] The first power supply signal provided by either of the two first power supply terminals VGH1_O and VGH3_O may be transmitted to the output signal terminal via the first transistor Q1. When the received input control signal is at the low level, the first transistor Q1 in the first level conversion sub-circuit 10 may be turned off, and the second transistor Q2 in the first level conversion sub-circuit 10 may be turned on. }
As per claim 2 Chen et al discloses: The drive control circuit according to claim 1, wherein each group of the at least two groups of input control terminals INPUT 1 to INPUT N comprises a first input control terminal INPUT 1 and a second input control terminal INPUT 2 {figures 2 & 5-6}; and
each group of the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O} comprises a first drive power terminal VGH3_O corresponding to the first input control terminal INPUT 1, and a second drive power terminal VGH1_O corresponding to the second input control terminal INPUT 2 {figures 2 & 5-6};
wherein a level of a drive power signal provided by the first drive power terminal VGH3_O is greater than a level of the drive power signal provided by the second drive power terminal VGH1_O { [0118] Correspondingly, the level of the first power supply terminal VGH3_O connected to the first level conversion sub-circuit 10 may be higher than the level of the first power supply terminal VGH1_O.}; and
each group of the at least two groups of first drive circuits 10 & 20 is configured to control, in response to an input control signal provided by the first input control terminal INPUT 1, an on-off of the first drive power terminal VGH3_O and the output terminal OUTPUT 1 to OUTPUT N, and control, in response to an input control signal provided by the second input control terminal INPUT 2, an on-off of the second drive power terminal VGH1_O and the output terminal OUTPUT 1 to OUTPUT N {figure 6 & [0101] The first power supply signal provided by either of the two first power supply terminals VGH1_O and VGH3_O may be transmitted to the output signal terminal via the first transistor Q1. When the received input control signal is at the low level, the first transistor Q1 in the first level conversion sub-circuit 10 may be turned off, and the second transistor Q2 in the first level conversion sub-circuit 10 may be turned on. }.
As per claim 3 Chen et al discloses: The drive control circuit according to claim 2, wherein the each group of the at least two groups of the first drive circuits 10 comprises a first transistor Q1 and a second transistor Q2 {figure 6};
wherein a gate of the first transistor Q1 is connected to the first input control terminal INPUT 1, a first electrode of the first transistor Q1 is connected to the first drive power terminal VGH3_O , and a second electrode of the first transistor Q1 is connected to the output terminal OUTPUT 1 to OUTPUT N {figure 6};
and a gate of the second transistor Q2 is connected to the second input control terminal INPUT 2, a first electrode of the second transistor Q2 is connected to the second drive power terminal VGH1_O, and a second electrode of the second transistor Q2 is connected to the output terminal OUTPUT 1 to OUTPUT N {figure 6}.
As per claim 4 Chen et al discloses: The drive control circuit according to claim 3, wherein one of the first transistor Q1 and the second transistor Q2 is a P-type transistor, and another of the first transistor Q1 and the second transistor Q2 is an N-type transistor {[0100] It is to be noted that the first transistor Q1 and the second transistor Q2 in each level conversion sub-circuit 10 may be of different types. For example, one of the transistors may be an N-type transistor, and the other may be a P-type transistor. For the N-type transistor, the effective level may be the high level; and for the P-type transistor, the effective level may be the low level. As such, it may be determined that the operating principle of the level conversion sub-circuit 10 is as follows.}.
As per claim 5 Chen et al discloses: The drive control circuit according to claim1 further comprising: a first signal control circuit, connected to the at least two groups of input control terminals INPUT 1 to INPUT N, and configured to transmit an input control signal to each group of the at least two groups of input control terminals INPUT 1 to INPUT N { [0072] For example, referring to FIG. 2, the illustrated level conversion circuit totally includes two level conversion sub-circuits 10 and two first switch sub-circuits 20 and each first switch sub-circuit 20 is connected to a plurality of input control terminals INPUT_1 to INPUT_N and one level conversion sub-circuit 10. Here, N is a positive integer greater than 1. When receiving the first switch control signal at an effective level, each first switch sub-circuit 20 may provide the input control signal provided by each of the connected input control terminals to the connected level conversion sub-circuit 10.}.
As per claim 6 Chen et al discloses: The drive control circuit according to claim 1, further comprising: a second drive circuit, connected to an enable control terminal, a pull-down power terminal, and the output terminal OUTPUT 1 to OUTPUT N, and configured to control, in response to an enable control signal provided by the enable control terminal, an on-off of the pull-down power terminal and the output terminal OUTPUT 1 to OUTPUT N { [0074] Each level conversion sub-circuit 10 may further be connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals. Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Each level conversion sub-circuit 10 may be configured to, in response to the received input control signal, transmit a first power supply signal provided by one of the first power supply terminals or a second power supply signal provided by one of the second power supply terminals to each of the connected output signal terminals. & [0101] The first power supply signal provided by either of the two first power supply terminals VGH1_O and VGH3_O may be transmitted to the output signal terminal via the first transistor Q1. When the received input control signal is at the low level, the first transistor Q1 in the first level conversion sub-circuit 10 may be turned off, and the second transistor Q2 in the first level conversion sub-circuit 10 may be turned on. }.
As per claim 7 Chen et al, insofar as the claims are definite and understood, discloses: The drive control circuit according to claim 6, wherein the second drive circuit 10 comprises a third transistor Q1/Q2; wherein a gate of the third transistor Q1/Q2 is connected to the enable control terminal, a first electrode of the third transistor Q1/Q2 is connected to the pull-down power terminal, and a second electrode of the third transistor Q1/Q2 is connected to the output terminal OUTPUT 1 to OUTPUT N {figure 6}.
As per claim 8 Chen et al discloses: The drive control circuit according to claim 6, further comprising: a second signal control circuit, connected to the enable control terminal, and configured to transmit an enable control signal to the enable control terminal { [0071] Each first switch sub-circuit 20 may be connected to at least one of a plurality of input control terminals and at least one level conversion sub-circuit 10. Each first switch sub-circuit 20 may be configured to provide an input control signal provided by each of the connected input control terminals to the connected level conversion sub-circuit 10 in response to a first switch control signal.}.
As per claim 9 Chen et al discloses: The drive control circuit according to claim 1 further comprising: a power supply circuit VGH1, connected to the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O}, and configured to transmit drive power signals with different levels to the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O & figure 6}.
As per claim 17 Chen et al discloses: The drive control circuit according to claim 1, further comprising: at least two groups of amplifiers 60 {figure 9}, connected to the at least two groups of input control terminals INPUT 1 to INPUT N and the at least two groups of first drive circuits 10 & 20 in one-to-one correspondence {figure 9: VGH1_O, VGH2_O, VGH3_O, VGH4_O }, and configured to amplify an input control signal provided by each group of the at least two groups of input control terminals INPUT 1 to INPUT N and transmit the input control signal as amplified to a corresponding group of the first drive circuits { [0118] For example, referring to FIG. 9 which shows two amplification sub-circuits 60, the input terminal of one of the amplification sub-circuits 60 is connected to the first initial power supply terminal VGH1, and the output terminal thereof is connected to the first initial power supply terminal VGH3. The amplification sub-circuit 60 may amplify the first power supply signal provided by the first initial power supply terminal VGH1, and transmit the amplified first power supply signal to the first initial power supply terminal VGH3}.
As per claim 18 Chen et al discloses: A display drive circuit, applied in a display panel, and comprising a light-emitting drive circuit, and a drive control circuit wherein the drive control circuit is connected to the light-emitting drive circuit, and the light-emitting drive circuit is configured to connect to a pixel in the display panel; the drive control circuit is configured to control the light-emitting drive circuit to drive the pixel to emit light {[0074] Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Note: GOA (i.e. Gate driver On Array) connects to a display panel (see [0068]) which is seen to have a light-emitting drive circuit and pixels.}; and
the drive control circuit comprises: at least two groups of first drive circuits 10 & 20, connected to at least two groups of input control terminals INPUT 1 to INPUT N, at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O}, and an output terminal OUTPUT 1 to OUTPUT N configured to connect to the light-emitting drive circuit;
wherein levels of drive power signals provided by the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O} are different {[0075] In addition, the first power supply signals provided by the first power supply terminals connected to the respective level conversion sub-circuits 10 may be at different levels, and the second power supply signals provided by the second power supply terminals connected to the respective level conversion sub-circuits 10 may be at different levels.}, the at least two groups of input control terminals INPUT 1 to INPUT N are in one-to-one correspondence with the at least two groups of first drive circuits 10 & 20 {figures 2 & 5}, the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O} are in one-to- one correspondence with the at least two groups of first drive circuits 10 & 20, and the at least two groups of input control terminals INPUT 1 to INPUT N are in one-to-one correspondence with the at least two groups of drive power terminals {Group 1: VGH1_O; VGH3_O & Group 2: VGH2_O; VGH4_O};
wherein each group of the at least two groups of first drive circuits 10 & 20 is configured to control, in response to an input control signal provided by a corresponding group of input control terminals, an on-off of a corresponding group of drive power terminals and the output terminal OUTPUT 1 to OUTPUT N { [0074] Each level conversion sub-circuit 10 may further be connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals. Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Each level conversion sub-circuit 10 may be configured to, in response to the received input control signal, transmit a first power supply signal provided by one of the first power supply terminals or a second power supply signal provided by one of the second power supply terminals to each of the connected output signal terminals. & [0101] The first power supply signal provided by either of the two first power supply terminals VGH1_O and VGH3_O may be transmitted to the output signal terminal via the first transistor Q1. When the received input control signal is at the low level, the first transistor Q1 in the first level conversion sub-circuit 10 may be turned off, and the second transistor Q2 in the first level conversion sub-circuit 10 may be turned on. }.
As per claim 19 Chen et al discloses: The display drive circuit according to claim 18, wherein the light-emitting drive circuit comprises a gate drive circuit; wherein the drive control circuit is configured to control the gate drive circuit to transmit a gate drive signal to the pixel to drive the pixel to emit light {[0074] Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Note: GOA (i.e. Gate driver On Array) connects to a display panel (see [0068]) which is seen to have a light-emitting drive circuit and pixels.}.
As per claim 20 Chen et al discloses: A display device, comprising a display panel, and the display drive circuit as defined in claim 18; wherein the display panel comprises a plurality of pixels; the display drive circuit is connected to the plurality of pixels, and the display drive circuit is configured to drive the plurality of pixels to emit light {[0074] Each output signal terminal may further be connected to a gate driving circuit (i.e., the GOA circuit). Note: GOA (i.e. Gate driver On Array) connects to a display panel (see [0068]) which is seen to have a light-emitting drive circuit and pixels.}.
Allowable Subject Matter
Claims 10- 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID D DAVIS whose telephone number is (571)272-7572. The examiner can normally be reached Monday - Friday, 8 a.m. - 4 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID D DAVIS/Primary Examiner, Art Unit 2627
DDD
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