Detailed Action
Response to Amendment
The amendment filed on 1/26/2026 has been entered and considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1, 2, 4, 5, 8-16 are objected to because of the following informalities:
The last limitation in claim 1 recites the limitation, “which the third transistor is turned have no overlap” should be changed to “turned on have” for the underlined portion.
Claims 2, 4, 5, 8-16 are objected as being dependent on objected base claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 8-10, 12, 13, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al (PGPUB 2024/0257757 A1) in view of Lee et al (PGPUB 2024/0355279 A1).
As to claim 1, Heo (Figs. 11, 12) teaches, a pixel circuit (pixel circuit, Fig. 11), comprising:
a light-emitting device (light-emitting element EL, ¶ 54);
a driving transistor (driving element DT) configured to generate, based on a data voltage signal (data voltage Vdata), a driving current (current, Fig. 8A) for driving the light-emitting device to emit light (¶ 97, 98);
a driving control circuit (switch elements M1 and M4), coupled to the driving transistor (i.e. via node DTG)(Fig. 8A) and configured to:
provide the data voltage signal to a gate of the driving transistor (Fig. 11: i.e. via DTG); and
in response to a signal (second EM signal EM2) from a light emission control signal terminal (gate line GL6) being at an active level (Fig. 12: i.e. EM2 at VGH), cause the driving transistor to generate the driving current (¶ 120, 131);
a conduction control circuit (switch element M5), wherein the driving transistor is coupled to the light-emitting device via the conduction control circuit (Fig. 11), and the conduction control circuit is configured to provide the driving current from the driving transistor to the light-emitting device in response to a signal (first EM signal EM1) from a first control signal terminal (gate line GL5) being at an active level (VGH)(Fig. 12, ¶ 131);
wherein, a duration of the active level of the signal from the first control signal terminal is shorter than a duration of the active level of the signal from the light emission control signal terminal (Fig. 12: i.e. EM1 has long duration of VGL than EM2. In other words, EM1 is turned on during shorter time periods by 2H than EM2, which has only 1H at VGL as shown in Fig. 12),
wherein the driving control circuit comprises:
a reset circuit (third switch M3), coupled to a second terminal (i.e. lower terminal as shown in Fig. 11) of the driving transistor, and configured to provide a signal (initialization voltage Vinit) from a first reference voltage signal terminal (fourth constant voltage node PL4) to the second terminal of the driving transistor in response to a signal (third scan signal SC3) from a second control signal terminal (third gate line GL3)(Fig. 11);
a light emission control circuit (switch element M6), coupled to a first terminal (i.e. upper terminal of Fig. 11) of the driving transistor, and configured to provide a signal (ELVDD) from a first power supply terminal to (first constant voltage node PL1) the first terminal of the driving transistor in response to the signal from the light emission control signal terminal (¶ 127);
a first control circuit (first capacitor C1 and second capacitor C1), coupled to the gate and the second terminal of the driving transistor (Fig. 11), and configured to keep a voltage difference between the second terminal and the gate of the driving transistor stable (¶ 86, 94, 98, 129, 131: i.e. threshold voltage is stored in the capacitors),
in a display frame (Fig. 3, ¶ 50: i.e. frame period):
the second transistor (first switch element M1) is configured, in response to a signal from a third control signal terminal (gate signal SC1), to be turned on and provide the data voltage signal (data voltage Vdata) from the data signal terminal to the gate of the driving transistor (¶ 81);
the third transistor (fourth switch element M4) is configured, in response to a signal from a fourth control signal terminal (gate signal SC4), to be turned on and provide the reference voltage signal (reference voltage Vref) from the data signal terminal to the gate of the driving transistor (¶ 84); and
the second transistor and the third transistor are configured in such a way that a duration in which the second transistor is turned on and a duration in which the third transistor is turned have no overlap (Fig. 4: i.e. SC4 is turned on during initialization period INI and sensing period SEN, while SC1 is turned on writing period WR)(¶ 86).
Heo does not specifically teach a data voltage signal as the reference voltage signal.
Lee (Fig. 2) teaches, a data writing circuit (second transistor T2 and third transistor T3), coupled to the gate of the driving transistor (third transistor T3), and configured to provide a reference voltage signal (data signal DATA) from a data signal terminal (i.e. left terminal of T2 and DL via T2) and the data voltage signal from the data signal terminal to the gate of the driving transistor (i.e. bottom terminal of T3 via T3)(¶ 69), respectively;
a second control circuit (first capacitor C1), coupled to the first power supply terminal (ELVDD) and the second terminal (i.e. upper terminal as shown in Fig. 2) of the driving transistor (T1), and configured to keep a voltage difference between the second terminal of the driving transistor and the first power supply terminal stable (¶ 86: i.e. store threshold voltage of first transistor T1 and compensate it).
wherein the data writing circuit comprises a second transistor (T3) and a third transistor (T2)(Fig. 2);
a gate (i.e. gate of T3) of the second transistor (T3) is coupled to the third control signal terminal (GW2), a first terminal (i.e. bottom terminal as shown in Fig. 2) of the second transistor is coupled to the data signal terminal, and a second terminal (i.e. upper terminal as shown in Fig. 2) of the second transistor is coupled to the gate of the driving transistor (Fig. 2); and
a gate of the third transistor (i.e. gate of T2) is coupled to the fourth control signal terminal (GW1), a first terminal (i.e. left terminal as shown in Fig. 2) of the third transistor is coupled to the data signal terminal, and a second terminal (i.e. right terminal as shown in Fig. 2) of the third transistor is coupled to the gate of the driving transistor (Fig. 2).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s pixel circuit structure into Heo’s pixel circuit, so as to avoid transmission loss of the data voltage and enable low power driving of the display device (¶ 20, 21).
As to claim 2, Heo (Figs. 11, 12) teaches, wherein, the driving control circuit is configured to:
in a light emission phase (light emission period EMIS), in response to the signal from the light emission control signal terminal being at the active level, cause the driving transistor to generate the driving current (¶ 131: i.e. M6 turns on to pass current to DT);
the conduction control circuit is configured to:
in the light emission phase, in response to the signal from the first control signal terminal being at the active level, provide the driving current from the driving transistor to the light-emitting device (¶ 131: i.e. M5 turns on to pass current through);
wherein in the light emission phase, a start moment of the signal from the first control signal terminal being at the active level is later than a start moment of the signal from the light emission control signal terminal being at the active level; or a start moment of the signal from the first control signal terminal being at the active level is same as a start moment of the signal from the light emission control signal terminal being at the active level (Fig. 12: i.e. VGH simultaneously applied at the beginning of EMIS).
As to claim 4, Heo (Figs. 3, 4) teaches in response to a signal (gate signal SC4) from a third control signal terminal (gate line GL4), first provide the reference voltage signal (i.e. SC4 is applied via GL4 and applied at timing INI as shown in Fig. 4) and then provide the data voltage signal from the data signal terminal to the gate of the driving transistor (i.e. provide Vdata to DTG via M1 in response to SC1. As shown in Fig. 4, SC1 is applied after SC4 during data writing period WR).
Heo does not specifically teach the reference voltage signal is from the data signal terminal.
Lee (Fig. 2) teaches, wherein the data writing circuit is further configured to:
in response to a signal (first write gate signal GW1) from a third control signal terminal (i.e. gate of T2), (i.e. GW1 is applied to transmit data voltage from DL to N1 and gate of T1) and (i.e. GW2 is applied to T3 to transmit data voltage from DL to N! and gate of T1) .
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s pixel circuit structure into Heo’s pixel circuit, so as to avoid transmission loss of the data voltage and enable low power driving of the display device (¶ 20, 21).
As to claim 5, Heo teaches the pixel circuit of claim 4, but does not specifically teach the data writing circuit of claim 4.
Lee (Figs. 2) teaches, wherein the data writing circuit comprises a first transistor (second transistor T2)(¶ 68);
wherein a gate of the first transistor is coupled to the third control signal terminal (i.e. gate of T2 receiving GW1), a first terminal (i.e. left terminal as shown in fig. 2) of the first transistor is coupled to the data signal terminal, and a second terminal (i.e. right terminal as shown in Fig. 2) of the first transistor is coupled to the gate of the driving transistor (Fig. 2: i.e. connects to gate of T1 via N1).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s pixel circuit structure into Heo’s pixel circuit, so as to avoid transmission loss of the data voltage and enable low power driving of the display device (¶ 20, 21).
As to claim 8, Heo (Fig. 11) teaches, wherein the reset circuit comprises a fourth transistor (third switch transistor M3)(¶ 83);
wherein a gate of the fourth transistor (i.e. gate of M3) is coupled to the second control signal terminal (third gate line GL3), a first terminal (i.e. upper terminal as shown in Fig. 3) of the fourth transistor is coupled to the second terminal of the driving transistor (i.e. connects to DTS and lower terminal of DT), and a second terminal (i.e. lower terminal) of the fourth transistor is coupled to the first reference voltage signal terminal (Fig. 3).
As to claim 9, Heo (Fig. 11) teaches, wherein the light emission control circuit comprises a fifth transistor (switch element M6)(Fig. 11);
wherein a gate (i.e. gate of M6) of the fifth transistor is coupled to the light emission control signal terminal (EM2), a first terminal (i.e. upper terminal of M6 as shown in Fig. 11) of the fifth transistor is coupled to the first power supply terminal, and a second terminal (i.e. lower terminal) of the fifth transistor is coupled to the first terminal of the driving transistor (Fig. 11).
As to claim 10, Heo (Fig. 11) teaches, wherein the first control circuit comprises a first capacitor (capacitors C1 and C2)(¶ 80);
wherein a first electrode (i.e. upper terminal of C1) of the first capacitor is coupled to the gate of the driving transistor (i.e. connected to gate of DT and DTG), and a second electrode (i.e. lower terminal of C2) of the first capacitor is coupled to the second terminal of the driving transistor (i.e. connects to lower terminal of DT and DTS).
As to claim 12, Heo (Fig. 11) teaches, wherein the conduction control circuit comprises a sixth transistor (switch element M5)(Fig. 11);
wherein a gate of the sixth transistor (i.e. gate of M5) is coupled to the first control signal terminal (i.e. M5 connects to GL5), a first terminal (i.e. upper terminal of M5 as shown in Fig. 11) of the sixth transistor is coupled to a second terminal (i.e. lower terminal of DT) of the driving transistor, and a second terminal (i.e. lower terminal of M5) of the sixth transistor is coupled to the light-emitting device (i.e. connects to EL)(Fig. 11).
As to claim 13, Heo (Fig. 11) teaches, wherein the driving transistor is a single-gate transistor (Fig. 11: i.e. single gate connected to DTG).
As to claim 15, Heo (Fig. 1) teaches, a display apparatus (display device)(Fig. 1), comprising the pixel circuit according to claim 1.
As to claim 16, Heo (Figs. 11, 12) teaches, a driving method for the pixel circuit according to claims 1, comprises:
in a data writing phase (data writing period WR): providing, by the driving control circuit, the data voltage signal to the gate of the driving transistor (i.e. SC1 is applied to transmit Vdata to the gate of the driving transistor); and
in a light emission phase (light emission period EMIS): in response to the signal from the light emission control signal terminal being at the active level (i.e. EM2 on), causing, by the driving control circuit, the driving transistor to generate the driving current (i.e. EM1 and EM2 is applied to turn on transistor M6 to generate current through M6/DT/M5/EL)(¶ 131); and
in response to the signal from the first control signal terminal being at the active level (i.e. EM1 on), providing, by the conduction control circuit, the driving current from the driving transistor to the light-emitting device (i.e. EM1 and EM2 is applied to turn on transistor M6 to generate current through M6/DT/M5/EL)(¶ 131).
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo and Lee as applied to claim 1 above, and further in view of Zhang (USPAT 10,916,197 B1).
As to claim 11, Heo and Lee teach the pixel circuit of claim 3, but do not specifically teach the second capacitor.
Zhang (Fig. 7) teaches, wherein the second control circuit comprises a second capacitor (capacitor C1)(Fig. 7);
wherein a first electrode (i.e. upper terminal of C1 as shown in Fig. 7) of the second capacitor is coupled to the first power supply terminal (VDD), and a second electrode (i.e. lower terminal) of the second capacitor is coupled to the second terminal (i.e. lower terminal of T1) of the driving transistor (T1)(Fig. 7).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s pixel structure into Heo’s pixel circuit as modified with the teaching of Lee’s pixel structure, so as to improve the uniformity of image display (abstract).
As to claim 14, Heo and Lee teach the pixel circuit of claim 3, but do not specifically teach a dual-gate transistor.
Zhang (Fig. 7) teaches, wherein the driving transistor is a dual-gate transistor (driving transistor T1), and the driving transistor comprises a top gate (top gate TG) and a bottom gate (bottom gate BG)(Fig. 7, col. 5 lines 10-15);
wherein the top gate of the driving transistor is coupled to the data writing circuit, and the bottom gate of the driving transistor is coupled to the second terminal of the driving transistor (Fig. 7: i.e. top gate connects to node P3 via transistor T4).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s pixel structure into Heo’s pixel circuit as modified with the teaching of Lee’s pixel structure, so as to improve the uniformity of image display (abstract).
Response to Arguments
Applicant's arguments filed 1/26/2026 have been fully considered but they are not persuasive.
Applicant has amended claim 1 to recite the limitations from previous claims 3, 6, 7 and the new limitation, “in a display frame, … the second transistor and the third transistors are configured in such a way that a duration in which the second transistor is turned on and a duration in which the third transistor is turned have no overlap”. Applicant argues that Heo and Lee prior art in combination do not specifically teach this limitation. Examiner respectfully disagrees. As discussed in detail above, Heo prior art teaches first switch element M1 and fourth switch element M4 that apply data voltage Vdata and reference voltage Vref in response to first scan signal SC1 and fourth scan signal SC4 respectively. On Fig. 4, the turn-on timing of scan signal SC4 is during initialization period INI and sensing period SEN. The turn-on timing of scan signal SC1 is only during writing period WR. Therefore, there is no overlap between the turn-on duration of SC4 and SC1. As indicated in the previous office action and above, Heo does not specifically teach the reference voltage Vref being the data voltage Vdata, or the fourth switch element M4 coupled to data line as required by the claim. Therefore, Heo and Lee combination still teaches the amended claims 1. The rejection is maintained final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623