DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/25/2026 has been entered.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
Claim 1, line 34: “to cause to” should be changed to –to cause--.
Claim 10, line 3: “a scanning line” should be changed to –the scanning line--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 8-14 and 16-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by He et al. (US PGPub 2024/0087518).
Regarding claim 1, He discloses a pixel circuit (fig. 6, pixel circuit 12), comprising a driving transistor (fig. 6, transistor T3) and a control circuit (fig. 6, transistor T8 and transistor T4 as based on the details structure of the control circuit in claim 1, lines 11-14), wherein:
the control circuit is electrically connected to a gate electrode of the driving transistor (fig. 6, node labeled N1), and the control circuit is further electrically connected to an electrode of the driving transistor (fig. 6, node labeled N3);
the control circuit is configured to control, in a first phase of a refreshing frame, an absolute value of a difference between a potential of the gate electrode of the driving transistor and a potential of the electrode of the driving transistor to be less than a voltage difference threshold, wherein the first phase is arranged before a data writing phase ([0100], “More specifically, in the embodiments of the present disclosure, in the first bias stage, the bias transistor may be turned on to provide a bias voltage to the second terminal of the driving transistor T3 to address the threshold shift of the driving transistor T3, and improve the stability of writing the data signal Vdata to the gate of the driving transistor T3 in the subsequent data writing stage. Based on the stable data signal Vdata and the biased driving transistor T3, the required driving current can be obtained, that is, the precision of driving current generated by the driving transistor T3 can be improved”);
the electrode comprises a first electrode of the driving transistor and/or a second electrode of the driving transistor (fig. 6, node N3);
the control circuit comprises a reference voltage writing circuit (fig. 6, transistor T8) and an on-off control circuit (fig. 6, transistor T4);
the reference voltage writing circuit comprises a first transistor (fig. 6, transistor T8), and the on-off control circuit comprises a third transistor (fig. 6, transistor T4);
a gate electrode of the first transistor is directly connected to a scanning line (fig. 6, SC_P(n-1)), a first electrode of the first transistor is directly connected to a reference voltage end (fig. 6, Vref1), and a second electrode of the first transistor is directly connected to the second electrode of the driving transistor (fig. 6, node N3);
a gate electrode of the third transistor is directly connected to a first gate line (fig. 6, SC_N(n)), a first electrode of the third transistor is directly connected to the gate electrode of the driving transistor (fig. 6, node N1), and a second electrode of the third transistor is directly connected to the second electrode of the driving transistor (fig. 6, node N3);
the pixel circuit further comprises a first initialization circuit (fig. 6, transistor T5), and the first initialization circuit comprises a seventh transistor (fig. 6, transistor T5); a control electrode of the seventh transistor is electrically connected to a reset line (fig. 6, SC_P1), a first electrode of the seventh transistor is electrically connected to a first initial voltage end (fig. 6, DVH), and a second electrode of the seventh transistor is electrically connected to a control node (fig. 6, node N3);
the second electrode of the first transistor and the second electrode of the third transistor are directly connected to each other at a same node (fig. 6, node N3), and the same node is a node of the second electrode of the driving transistor (fig. 6, node N3); and
the control circuit is configured to, in the first phase, write a reference voltage to the second electrode of the driving transistor through the first transistor and simultaneously electrically connect the gate electrode of the driving transistor to the second electrode of the driving transistor through the third transistor, to cause the driving transistor to be in a diode connection state ([0067], “A valid pulse of the fifth control signal may control the threshold compensation transistor T4 to be in an on state to detect and self-compensate for the deviation of the threshold value voltage of the driving transistor T3”).
Regarding claim 2, He further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (He: [0101], “At the same time, the threshold compensation transistor T4 may also be in the on stage for detecting and self-compensating the deviation of the threshold voltage of the driving transistor T3, which can also improve the performance of the driving transistor T3 to improve the precision of driving current generated by the driving transistor T3, thereby improving the display effect of the display panel” where the voltage and the gate and second electrode of the driving transistor would be substantially the same and thus the ratio would be 1).
Regarding claim 4, He further discloses wherein the reference voltage writing circuit is electrically connected to each of the scanning line (He: fig. 6, SC_P(n-1)), the reference voltage end (He: fig. 6, Vref1) and the second electrode of the driving transistor (He: fig. 6, node N3), and is configured to write the reference voltage provided by the reference voltage end into the second electrode of the driving transistor under the control of a scanning signal provided by the scanning line (He: [0070, “When the first reset transistor T8 resets the gate of the driving transistor T3, the first reset transistor T8 and the threshold compensation transistor T4 may both be in the on state”);
the on-off control circuit is electrically connected to each of the first gate line (He: fig. 6, SC_N(n)), the gate electrode of the driving transistor (He: fig. 6, node N1) and the second electrode of the driving transistor (He: fig. 6, node N3), and is configured to control the gate electrode of the driving transistor to be electrically connected to the second electrode of the driving transistor under the control of a first gate electrode driving signal provided by the first gate line (He: [0067], “A valid pulse of the fifth control signal may control the threshold compensation transistor T4 to be in an on state to detect and self-compensate for the deviation of the threshold value voltage of the driving transistor T3”).
Regarding claim 8, He further discloses further comprising a light-emitting element (He: fig. 6, light-emitting element Q), a first light-emitting control circuit (He: fig. 6, transistor T1), a second light-emitting control circuit (He: fig. 6, transistor T6), and a data writing circuit (He: fig. 6, transistor T2);
the first light-emitting control circuit is electrically connected to each of a light-emitting control line (He: fig. 6, EM), a first voltage end (He: fig. 6, PVDD), and the first electrode of the driving transistor (He: fig. 6, node N2), and is configured to control the first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal on the light-emitting control line (He: [0068], “The light-emitting control signal terminal EM may be used for outputting a light-emitting control signal for controlling the first light-emitting control transistor T1 and the second light-emitting control transistor T6. The light-emitting control signal may be a pulse signal. A valid pulse of the light-emitting control signal may control the first light-emitting control transistor T1 and the second light-emitting control transistor T6. At this time, the driving current may flow through the light-emitting element Q, and the light-emitting element Q may emit light in response to the driving current”);
the second light-emitting control circuit is electrically connected to each of the light- emitting control line (He: fig. 6, EM), the second electrode of the driving transistor (He: fig. 6, node N3) and a first electrode of the light-emitting element (He: fig. 6, node N4), and is configured to control the second electrode of the driving transistor to be electrically connected to the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line (He: [0068], “The light-emitting control signal terminal EM may be used for outputting a light-emitting control signal for controlling the first light-emitting control transistor T1 and the second light-emitting control transistor T6. The light-emitting control signal may be a pulse signal. A valid pulse of the light-emitting control signal may control the first light-emitting control transistor T1 and the second light-emitting control transistor T6. At this time, the driving current may flow through the light-emitting element Q, and the light-emitting element Q may emit light in response to the driving current”); a second electrode of the light-emitting element is electrically connected to a second voltage end (He: fig. 6, PVEE);
the data writing circuit is electrically connected to each of a second gate line (He: fig. 6, SC_P(n)), a data line (He: fig. 6, Vdata), and the first electrode of the driving transistor (He: fig. 6, node N2), and is configured to write a data voltage provided by the data line into the first electrode of the driving transistor under the control of a second gate electrode driving signal provided by the second gate line (He: [0069], “It should be noted that the data writing transistor T2 may write the data signal Vdata to the gate of the driving transistor T3”);
the first initialization circuit is configured to write a first initial voltage provided by the first initial voltage end into the control node under the control of a reset signal provided by the reset line (He: [0065], “The bias voltage terminal DVH may be used for outputting a bias signal for biasing the second terminal of the driving transistor T3. The third scan signal terminal SC_P1 may be used for outputting a third control signal for controlling the bias transistor T5”).
Regarding claim 9, He further discloses further comprising an energy storage circuit (He: fig. 6, capacitor C1);
the energy storage circuit is electrically connected to the gate electrode of the driving transistor (He: fig. 6, node N1), and is configured to maintain the potential of the gate electrode of the driving transistor (He: [0071], “The first plate of the capacitor C1 may be electrically connected to the first power supply voltage terminal PVDD, and the second plate of the capacitor C1 may be electrically connected to the first node N1”).
Regarding claim 10, He further discloses further comprising a second initialization circuit (He: fig. 6, transistor T7);
the second initialization circuit is electrically connected to each of the scanning line (He: fig. 6, SC_P(n-1)), a second initial voltage end and the first electrode of the light-emitting element (He: fig. 6, node N4), and is configured to write a second initial voltage provided by the second initial voltage end into the first electrode of the light-emitting element under the control of a scanning signal provided by the scanning line (He: [0073], “the second reset transistor T7 may be used reset the anode of the light-emitting element Q”).
Regarding claim 11, He further discloses wherein the data writing circuit comprises a fourth transistor (He: fig. 6, transistor T2), the first light-emitting control circuit comprises a fifth transistor (He: fig. 6, transistor T1), and the second light-emitting control circuit comprises a sixth transistor (He: fig. 6, transistor T6),
a gate electrode of the fourth transistor is electrically connected to the second gate line (He: fig. 6, SC_P(n)), a first electrode of the fourth transistor is electrically connected to the data line (He: fig. 6, Vdata), and a second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor (He: fig. 6, node N2);
a gate electrode of the fifth transistor is electrically connected to the light-emitting control line (He: fig. 6, EM), a first electrode of the fifth transistor is electrically connected to the first voltage end (He: fig. 6, PVD), and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor (He: fig. 6, node N2);
a gate electrode of the sixth transistor is electrically connected to the light-emitting control line (He: fig. 6, EM), a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor (He: fig. 6, node N3), and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element (He: fig. 6, node N4).
Regarding claim 12, He further discloses wherein the energy storage circuit comprises a storage capacitor (He: fig. 6, capacitor C1), and the second initialization circuit comprises an eighth transistor (He: fig. 6, transistor T7);
a first end of the storage capacitor is electrically connected to the gate electrode of the driving transistor (He: fig. 6, node N1), and a second end of the storage capacitor is electrically connected to the first voltage end (He: fig. 6, C1 connected to PVD at node that is not labeled);
a gate electrode of the eighth transistor is electrically connected to the scanning line (He: fig. 6, SC_P(n-1)), a first electrode of the eighth transistor is electrically connected to the second initial voltage end (He: fig. 6, Vref2), and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element (He: fig. 6, node N4).
Regarding claim 13, He further discloses a driving method, applied to the pixel circuit according to claim 1, wherein a display period comprises the refreshing frame (He: fig. 8, reset stage); the refreshing frame comprises the first phase arranged before the data writing phase (He: fig. 8, reset stage before data writing stage); the driving method comprises:
in the first phase of the refreshing frame, controlling, by the control circuit, the absolute value of the difference between the potential of the gate electrode of the driving transistor and the potential of the electrode of the driving transistor to be less than the voltage difference threshold (He: [0008], “turning on the first reset transistor and the threshold compensation transistor to provide a first reference voltage to a gate of the driving transistor in the reset stage”); the electrode comprises the first electrode of the driving transistor and/or the second electrode of the driving transistor (He: second electrode of transistor T3).
Regarding claim 14, He further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (He: [0101], “At the same time, the threshold compensation transistor T4 may also be in the on stage for detecting and self-compensating the deviation of the threshold voltage of the driving transistor T3, which can also improve the performance of the driving transistor T3 to improve the precision of driving current generated by the driving transistor T3, thereby improving the display effect of the display panel”).
Regarding claim 16, He further discloses wherein the refreshing frame further comprises a reset phase and the data writing phase arranged sequentially in that order after the first phase (He: fig. 8, reset stage before data writing stage); the driving method comprises:
in at least part of the first phase, the reset phase and at least part of the data writing phase, writing, by the reference voltage writing circuit, the reference voltage to the second electrode of the driving transistor under the control of a scanning signal (He: [0081], “A stage (e.g., a first stage or a current stage) of the shift register may provide the control signals for the data writing transistor T2 of the pixel circuit 12 in the current and provide the control signals for the first reset transistor T8 of the pixel circuit 12 in the next row”); controlling, by the on-off control circuit, the gate electrode of the driving transistor to be electrically connected to the second electrode of the driving transistor under the control of a first gate electrode driving signal, to cause the driving transistor to be in a diode connection state (He: [0067], “A valid pulse of the fifth control signal may control the threshold compensation transistor T4 to be in an on state to detect and self-compensate for the deviation of the threshold value voltage of the driving transistor T3”).
Regarding claim 17, He further discloses wherein the refreshing frame further comprises a first bias phase (He: fig. 8, first bias stage) and a first light-emitting phase arranged after the data writing phase (He: fig. 8, light-emitting stage after data writing stage); the pixel circuit further comprises a light-emitting element (He: fig. 8, light-emitting element Q), the data writing phase (He: fig. 8, data writing stage), a first light-emitting control circuit (He: fig. 6, transistor T1) and a second light-emitting control circuit (He: fig. 6, transistor T6);
in at least part of the data writing phase, writing, by a data writing circuit, a data voltage on a data line into the first electrode of the driving transistor under the control of a second gate electrode driving signal (He: [0101], “In the data writing stage, the data signal Vdata may be written to the gate of the driving transistor T3 through the data writing transistor T2, and the driving transistor T3 may generate a corresponding driving current based on the data signal Vdata. At the same time, the threshold compensation transistor T4 may also be in the on stage for detecting and self-compensating the deviation of the threshold voltage of the driving transistor T3, which can also improve the performance of the driving transistor T3 to improve the precision of driving current generated by the driving transistor T3, thereby improving the display effect of the display panel);
in at least part of the reset phase, writing, by the first initialization circuit, a first initial voltage into the control node under the control of a reset signal (He: [0095], “S102, first reset transistor T8 and the threshold compensation transistor T4 are turned on to provide a first reference voltage to the gate of the driving transistor T3 in the reset stage”);
in at least part of the first bias phase, writing, by the reference voltage writing circuit, the reference voltage into the first electrode of the driving transistor or the second electrode of the driving transistor under the control of the scanning signal (He: [0100], “in the first bias stage, the bias transistor may be turned on to provide a bias voltage to the second terminal of the driving transistor T3 to address the threshold shift of the driving transistor T3, and improve the stability of writing the data signal Vdata to the gate of the driving transistor T3 in the subsequent data writing stage. Based on the stable data signal Vdata and the biased driving transistor T3, the required driving current can be obtained, that is, the precision of driving current generated by the driving transistor T3 can be improved”);
in the first light-emitting phase, controlling, by the first light-emitting control circuit, a first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal provided by a light-emitting control line, and controlling, by the second light-emitting control circuit, the second electrode of the driving transistor to be electrically connected to a first electrode of the light-emitting element under the control of the light-emitting control signal, and driving, by the driving transistor, the light-emitting element (He: [0102], “In the light-emitting stage, the light-emitting control module 13 may be turned on, the driving current generated by the driving transistor T3 may flow through the light-emitting element Q, and the light-emitting element Q may emit light in response to the driving current. Based on the high-precision driving current, the brightness required by the target can be achieved, thereby improving the display effect of the display panel”).
Regarding claim 18, He further discloses wherein the display period further comprises a maintenance frame (He: fig. 12, steps S105 and S104); the maintenance frame comprises a second bias phase and a second light-emitting phase arranged sequentially in that order (He: fig. 12, steps S105 and S104); the driving method comprises:
in at least part of the second bias phase, writing, by the reference voltage writing circuit, the reference voltage into the first electrode of the driving transistor or the second electrode of the driving transistor under the control of the scanning signal (He: [0104], “S105, the working process of the pixel circuit 12 further includes a second biasing stage after the data writing stage and before the light-emitting stage, the bias transistor T5 is turned on to provide a biasing voltage to the second terminal of the driving transistor T3 in the second bias stage.”);
in the second light-emitting phase, controlling, by a first light-emitting control circuit, a first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal provided by a light-emitting control line, and controlling, by a second light-emitting control circuit, the second electrode of the driving transistor to be electrically connected to a first electrode of a light-emitting element under the control of the light-emitting control signal, and driving, by the driving transistor, the light-emitting element (He: [0102], “In the light-emitting stage, the light-emitting control module 13 may be turned on, the driving current generated by the driving transistor T3 may flow through the light-emitting element Q, and the light-emitting element Q may emit light in response to the driving current. Based on the high-precision driving current, the brightness required by the target can be achieved, thereby improving the display effect of the display panel.”).
Regarding claim 19, He further discloses a display device (He: fig. 13, display device 100), comprising the pixel circuit according to claim 1.
Regarding claim 20, He further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (He: [0101], “At the same time, the threshold compensation transistor T4 may also be in the on stage for detecting and self-compensating the deviation of the threshold voltage of the driving transistor T3, which can also improve the performance of the driving transistor T3 to improve the precision of driving current generated by the driving transistor T3, thereby improving the display effect of the display panel”).
Claims 21-25 are within the scope of claims 8-12 respectively and are therefore interpreted and rejected based on similar reasoning.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
