DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2, 4, 8-14 and 16-25 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US PGPub 2023/0140604) in view of Zhou et al. (US PGPub 2024/0038174) and Zhang et al. (US PGPub 2024/0078972).
Regarding claim 1, Jeong discloses a pixel circuit (fig. 8, pixel PX_1), comprising a driving transistor (fig. 8, transistor T1) and a control circuit (other transistors in figure 8, where Applicants fig. 8 and dependent claims, for example claims 3-5 and others, define the circuitry within the control circuit), wherein:
the control circuit is electrically connected to a gate electrode of the driving transistor (fig. 8, node N3 connected to gate of transistor T1), and the control circuit is further electrically connected to an electrode of the driving transistor (fig. 8, nodes N1 and N2 which are each connected to a first and a second electrode of transistor T1); the control circuit is configured to control, in a first phase of a refreshing frame, ([0152], “the voltage of the third node N3 may be changed to a difference between the first power voltage VDD and a threshold voltage Vth of the first transistor T1 (for example, VDD-Vth)”) and a potential of the electrode of the driving transistor ([0125], “Here, as the fifth power voltage Vbias is periodically supplied to the first node N1, the bias state of the first transistor T1 may be periodically changed, and a threshold voltage characteristic of the first transistor T1 may be changed. Therefore, a characteristic of the first transistor T1 may be fixed to a specific state, and the first transistor T1 may be prevented from being deteriorated in the low-frequency driving.”) ([0070]-[0071], “[0070] In order to improve image quality, one frame period may include a plurality of non-emission periods and emission periods according to the frame frequency. For example, initial non-emission period and emission period of one frame may be defined as a first driving period, and subsequent non-emission period and emission period may be defined as a second driving period. For example, a data signal for displaying an image may be substantially written to the pixel PX in the first driving period, and an on-bias may be applied to the driving transistor of the pixel PX in the second driving period”)
the electrode comprises a first electrode of the driving transistor and/or a second electrode of the driving transistor (fig. 8, nodes N1 and N2 which are each connected to a first and a second electrode of transistor T1);
wherein the control circuit comprises a reference voltage writing circuit (Jeong: fig. 8, transistor T9) and an on-off control circuit (Jeong: fig. 8, transistor T10);
the reference voltage writing circuit comprises a first transistor (Jeong: fig. 8, transistor T9), and the on-off control circuit comprises a third transistor (Jeong: fig. 8, transistor T10).
While at least one function of the control circuitry of Jeong is to control the potential at the gate electrode and the potential at the source/drain electrodes of the driving transistor, Jeong does not specify that the difference between the potentials is less than a voltage threshold difference which is an arbitrary value not further defined in the claim. It has been known in the art to use control circuitry to control an absolute value of a difference between the gate electrode potential and the potential of the drain/source electrodes of a driving transistor. In a similar field of endeavor of display devices, Zhou discloses the control circuit is configured to control an absolute value of a difference between a potential of the gate electrode of the driving transistor and a potential of the electrode of the driving transistor to be less than a voltage difference threshold ([0042], “In the data-writing phase, at the moment of starting to charge the energy-storage capacitor C1, a gate voltage Vg of the drive transistor M satisfies Vg=Vint, and the source voltage Vs of the drive transistor M satisfies Vs=Vdata+VDD, and at this moment, the gate-source voltage Vgs of the drive transistor M satisfies the expression: Vgs=Vg−Vs=Vint−Vdata<Vth, and thus the drive transistor M is turned on. Vth represents the threshold voltage of the drive transistor M, the drive transistor M is turned on when Vgs<Vth, and the drive transistor M is cut off when Vgs>Vth”).
In view of the teachings of Jeong and Zhou, it would have been obvious to one of ordinary skill in the art to control the difference between a potential of the gate electrode and a potential of the drain/source electrode of the driving transistor, as taught by Zhou, within the pixel circuitry of Jeong, for the purpose of improving a refresh frequency of a display panel by shortening a duration of the data-writing phase and a duration of the one-frame display period (Zhou: [0042]).
While Joeng and Zhou discloses the second electrode of the third transistor is indirectly connected to the second electrode of the driving transistor (Jeong: fig. 8, T10 connected to T1 at node N2 through transistor T3), it has been known to have the third transistor directly connected to the driving transistor. In a similar field of endeavor of display devices, Zhang discloses a gate electrode of the first transistor is directly connected to a scanning line (fig. 5, S1), a first electrode of the first transistor is directly connected to a reference voltage end (fig. 5, bias adjustment signal DVH), and a second electrode of the first transistor is directly connected to the second electrode of the driving transistor (fig. 5, node N3);
a gate electrode of the third transistor is directly connected to a first gate line (fig. 5, S2), a first electrode of the third transistor is directly connected to the gate electrode of the driving transistor (fig. 5, node N1), and a second electrode of the third transistor is directly connected to the second electrode of the driving transistor (fig. 5, node N3);
the second electrode of the first transistor is directly connected to the second electrode of the third transistor (fig. 5, node N3).
In view of the teachings of Joeng, Zhou and Zhang, it would have been obvious to one of ordinary skill in the art to include the connections of Zhang within the circuitry of Jeong and Zhou, where the threshold compensation module provides the known function of the threshold compensating module 15 compensates the threshold voltage of the driving transistor T2, so that the driving transistor T2 can provide the corresponding drive current according to the data signal Vdata (Zhang: [0104]).
Regarding claim 2, the combination of Jeong and Zhou further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (Zhou: [0042], “Vg=Vdata +VDD+Vth, Vgs=(Vdata+VDD+Vth)−(Vdata+VDD)=Vth” where Vgs is the difference between the potential at the gate electrode and the potential at the source electrode and therefore if Vgs=Vth then the ratio of Vgs/Vth=1).
Regarding claim 4, the combination of Jeong and Zhou further discloses wherein
the reference voltage writing circuit is electrically connected to each of the scanning line (Jeong: fig. 8, S3i line), the reference voltage end (Jeong: fig. 8, Vbias) and the second electrode of the driving transistor (Jeong: fig. 8, node N1), and is configured to write a reference voltage provided by the reference voltage end into the second electrode of the driving transistor under the control of a scanning signal provided by the scanning line (Jeong: [0124], “a predetermined high voltage may be applied to the first electrode (for example, a source electrode) of the first transistor T1 by the turn-on of the ninth transistor T9”);
the on-off control circuit is electrically connected to each of the first gate line (Jeong: fig. 8, S5i line), the gate electrode of the driving transistor (Jeong: fig. 8, node N3) and the second electrode of the driving transistor (Jeong: fig. 8, transistor T10 connected to node N2 through the transistor t3), and is configured to control the gate electrode of the driving transistor to be electrically connected to the second electrode of the driving transistor under the control of a first gate electrode driving signal provided by the first gate line (Jeong: [0190], “The tenth transistor T10 may be turned on when the fifth scan signal is supplied to the fifth scan line S5i to connect the first transistor T1 in a diode form together with the turned-on third transistor T3 or supply the third power voltage Vint1 from the third power line PL3 to the third node N3 (or the gate electrode of the first transistor T1) together with the turned-on fourth transistor T4”).
Regarding claim 8, the combination of Jeong and Zhou further discloses further comprising a light-emitting element (Jeong: fig. 8, a light emitting element LD), a first light-emitting control circuit (Jeong: fig. 8, transistor T6), a second light-emitting control circuit (Jeong: fig. 8, transistor T7), a data writing circuit (Jeong: fig. 8, transistor T2) and a first initialization circuit (Jeong: fig. 8, transistor T4);
the first light-emitting control circuit is electrically connected to each of a light-emitting control line (Jeong: fig. 8, E1i), a first voltage end (Jeong: fig. 8, VDD), and the first electrode of the driving transistor (Jeong: fig. 8, node N1), and is configured to control the first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal on the light-emitting control line (Jeong: [0112], “When the sixth transistor T6 is turned on, the first node N1 may be electrically connected to the first power line PL1”);
the second light-emitting control circuit is electrically connected to each of the light-emitting control line (Jeong: fig. 8, E2i), the second electrode of the driving transistor (Jeong: fig. 8, node N2) and a first electrode of the light-emitting element (Jeong: fig. 8, node N5), and is configured to control the second electrode of the driving transistor to be electrically connected to the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line (Jeong: [0113]-[0114], “The seventh transistor T7 may be connected between the second node N2 and the fifth node N5 (or the first electrode of the light emitting element LD)…When the seventh transistor T7 is turned on, the second node N2 and the fifth node N5 may be electrically connected”); a second electrode of the light-emitting element is electrically connected to a second voltage end (Jeong: fig. 8, VSS);
the data writing circuit is electrically connected to each of a second gate line (Jeong: fig. 8, S4i line), a data line (Jeong: fig. 8, Dj line), and the first electrode of the driving transistor (Jeong: fig. 8, node N1), and is configured to write a data voltage provided by the data line into the first electrode of the driving transistor under the control of a second gate electrode driving signal provided by the second gate line (Jeong: [0101], “The second transistor T2 may be connected between the j-th data line Dj (hereinafter, referred to as a data line) and the first node N1. A gate electrode of the second transistor T2 may be connected to an i-th fourth scan line S4i (hereinafter, referred to as a fourth scan line). The second transistor T2 may be turned on when the fourth scan signal is supplied to the fourth scan line S4i to electrically connect the data line Dj and the first node N1”);
the first initialization circuit is electrically connected to each of a reset line (Jeong: fig. 8, S1i line), a first initial voltage end (Jeong: fig. 8, Vint1) and a control node (Jeong: fig. 8, node between transistors T3, T4 and T10), and is configured to write a first initial voltage provided by the first initial voltage end into the control node under the control of a reset signal provided by the reset line (Jeong: [0192], “In the first period P1 of the compensation period CP, as the first scan signal is supplied to the first scan line S1i, the fourth transistor T4 is turned on, and the third power voltage Vint1 may be supplied to the third node N3 through the transistor T4 and the tenth transistor T10. Therefore, the voltage of the third node N3 (that is, the voltage of the gate electrode of the first transistor T1) may be initialized to the third power voltage Vint1”).
Regarding claim 9, the combination of Jeong and Zhou further discloses further comprising an energy storage circuit (Jeong: fig. 8, capacitor C1);
the energy storage circuit is electrically connected to the gate electrode of the driving transistor (Jeong: fig. 8, capacitor C1 connected to gate of transistor T1 at node N3), and is configured to maintain the potential of the gate electrode of the driving transistor (Jeong: [0126], “The first capacitor C1 may store a voltage difference between the third node N3 and the fourth node N4”).
Regarding claim 10, the combination of Jeong and Zhou further discloses further comprising a second initialization circuit (Jeong: fig. 8, transistor T8);
the second initialization circuit is electrically connected to each of a scanning line (Jeong: fig. 8, S3i line), a second initial voltage end (Jeong: fig. 8, Vint2) and the first electrode of the light-emitting element (Jeong: fig. 8, node N5), and is configured to write a second initial voltage provided by the second initial voltage end into the first electrode of the light-emitting element under the control of a scanning signal provided by the scanning line (Jeong: [0116], “The eighth transistor T8 may be turned on when the third scan signal is supplied to the third scan line S3i to supply the fourth power voltage Vint2 to the fifth node N5”).
Regarding claim 11, the combination of Jeong and Zhou further discloses wherein the data writing circuit comprises a fourth transistor (Jeong: fig. 8, transistor T2), the first light-emitting control circuit comprises a fifth transistor (Jeong: fig. 8, transistor T6), the second light-emitting control circuit comprises a sixth transistor (Jeong: fig. 8, transistor T7), and the first initialization circuit comprises a seventh transistor (Jeong: fig. 8, transistor T4);
a gate electrode of the fourth transistor is electrically connected to the second gate line (Jeong: fig. 8, S4i line), a first electrode of the fourth transistor is electrically connected to the data line (Jeong: fig. 8, Dj line), and a second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor (Jeong: fig. 8, node N);
a gate electrode of the fifth transistor is electrically connected to the light-emitting control line (Jeong: fig. 8, E1i), a first electrode of the fifth transistor is electrically connected to the first voltage end (Jeong: fig. 8, VDD), and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor (Jeong: fig. 8, node N1);
a gate electrode of the sixth transistor is electrically connected to the light-emitting control line (Jeong: fig. 8, E2i), a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor (Jeong: fig. 8, node N2), and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element (Jeong: fig. 8, node N5);
a control electrode of the seventh transistor is electrically connected to the reset line (Jeong: fig. 8, S1i), a first electrode of the seventh transistor is electrically connected to the first initial voltage end (Jeong: fig. 8, Vint1), and a second electrode of the seventh transistor is electrically connected to the control node (Jeong: fig. 8, node between transistors T3, T4 and T10).
Regarding claim 12, the combination of Jeong and Zhou further discloses wherein the energy storage circuit comprises a storage capacitor (Jeong: fig. 8, capacitor C1), and the second initialization circuit comprises an eighth transistor (Jeong: fig. 8, transistor T8);
a first end of the storage capacitor is electrically connected to the gate electrode of the driving transistor (Jeong: fig. 8, node N3), and a second end of the storage capacitor is electrically connected to the first voltage end (Jeong: fig. 8, capacitor C1 connected to VDD through capacitor C2);
a gate electrode of the eighth transistor is electrically connected to the scanning line (Jeong: fig. 8, S3i line), a first electrode of the eighth transistor is electrically connected to the second initial voltage end (Jeong: fig. 8, Vint2), and a second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element (Jeong: fig. 8, node N5).
Regarding claim 13, the combination of Jeong and Zhou further discloses a driving method, applied to the pixel circuit according to claim 1, wherein a display period comprises the refreshing frame; the refreshing frame comprises the first phase arranged before the data writing phase (Jeong: [0070]-[0071], “In order to improve image quality, one frame period may include a plurality of non-emission periods and emission periods according to the frame frequency. For example, initial non-emission period and emission period of one frame may be defined as a first driving period, and subsequent non-emission period and emission period may be defined as a second driving period. For example, a data signal for displaying an image may be substantially written to the pixel PX in the first driving period, and an on-bias may be applied to the driving transistor of the pixel PX in the second driving period”); the driving method comprises:
in the first phase of the refreshing frame, controlling, by the control circuit, the absolute value of the difference between the potential of the gate electrode of the driving transistor (Jeong: [0152], “the voltage of the third node N3 may be changed to a difference between the first power voltage VDD and a threshold voltage Vth of the first transistor T1 (for example, VDD-Vth)”) and the potential of the electrode of the driving transistor (Jeong: [0125], “Here, as the fifth power voltage Vbias is periodically supplied to the first node N1, the bias state of the first transistor T1 may be periodically changed, and a threshold voltage characteristic of the first transistor T1 may be changed. Therefore, a characteristic of the first transistor T1 may be fixed to a specific state, and the first transistor T1 may be prevented from being deteriorated in the low-frequency driving.”) to be less than the voltage difference threshold (Zhou: [0042], “In the data-writing phase, at the moment of starting to charge the energy-storage capacitor C1, a gate voltage Vg of the drive transistor M satisfies Vg=Vint, and the source voltage Vs of the drive transistor M satisfies Vs=Vdata+VDD, and at this moment, the gate-source voltage Vgs of the drive transistor M satisfies the expression: Vgs=Vg−Vs=Vint−Vdata<Vth, and thus the drive transistor M is turned on. Vth represents the threshold voltage of the drive transistor M, the drive transistor M is turned on when Vgs<Vth, and the drive transistor M is cut off when Vgs>Vth”); the electrode comprises the first electrode of the driving transistor and/or the second electrode of the driving transistor (Jeong: fig. 8, nodes N1 and N2 which are each connected to a first and a second electrode of transistor T1).
Regarding claim 14, the combination of Jeong and Zhou further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (Zhou: [0042], “Vg=Vdata +VDD+Vth, Vgs=(Vdata+VDD+Vth)−(Vdata+VDD)=Vth” where Vgs is the difference between the potential at the gate electrode and the potential at the source electrode and therefore if Vgs=Vth then the ratio of Vgs/Vth=1).
Regarding claim 16, the combination of Jeong and Zhou further discloses wherein the refreshing frame further comprises a reset phase and the data writing phase arranged sequentially in that order after the first phase; the driving method comprises:
in at least part of the first phase, the reset phase and at least part of the data writing phase, writing, by the reference voltage writing circuit, the reference voltage to the second electrode of the driving transistor under the control of a scanning signal (Jeong: [0123]-[0125], “The ninth transistor T9 may be turned on when the third scan signal is supplied to the third scan line S3i to supply the fifth power voltage Vbias to the first node N1…Here, as the fifth power voltage Vbias is periodically supplied to the first node N1, the bias state of the first transistor T1 may be periodically changed, and a threshold voltage characteristic of the first transistor T1 may be changed. Therefore, a characteristic of the first transistor T1 may be fixed to a specific state, and the first transistor T1 may be prevented from being deteriorated in the low-frequency driving”); controlling, by the on-off control circuit, the gate electrode of the driving transistor to be electrically connected to the second electrode of the driving transistor under the control of a first gate electrode driving signal, to cause the driving transistor to be in a diode connection state (Jeong: [0190], “The tenth transistor T10 may be turned on when the fifth scan signal is supplied to the fifth scan line S5i to connect the first transistor T1 in a diode form together with the turned-on third transistor T3 or supply the third power voltage Vint1 from the third power line PL3 to the third node N3 (or the gate electrode of the first transistor T1) together with the turned-on fourth transistor T4”).
Regarding claim 17, the combination of Jeong and Zhou further discloses wherein the refreshing frame further comprises a first bias phase and a first light-emitting phase arranged after the data writing phase; the pixel circuit further comprises a light-emitting element (Jeong: fig. 8, light emitting element LD), a first initialization circuit (Jeong: fig. 8, transistor T4), the data writing phase, a first light-emitting control circuit (Jeong: fig. 8, transistor T6) and a second light-emitting control circuit (Jeong: fig. 8, transistor T7);
in at least part of the data writing phase, writing, by a data writing circuit, a data voltage on a data line into the first electrode of the driving transistor under the control of a second gate electrode driving signal (Jeong: [0101], “The second transistor T2 may be connected between the j-th data line Dj (hereinafter, referred to as a data line) and the first node N1. A gate electrode of the second transistor T2 may be connected to an i-th fourth scan line S4i (hereinafter, referred to as a fourth scan line). The second transistor T2 may be turned on when the fourth scan signal is supplied to the fourth scan line S4i to electrically connect the data line Dj and the first node N1.”);
in at least part of the reset phase, writing, by the first initialization circuit, a first initial voltage into the control node under the control of a reset signal (Jeong: [0106], “The fourth transistor T4 may be turned on by supply of the first scan signal to initialize the third node N3 (or the gate electrode of the first transistor T1) to the third power voltage Vint1.”);
in at least part of the first bias phase, writing, by the reference voltage writing circuit, the reference voltage into the first electrode of the driving transistor or the second electrode of the driving transistor under the control of the scanning signal (Jeong: [0123], “The ninth transistor T9 may be turned on when the third scan signal is supplied to the third scan line S3i to supply the fifth power voltage Vbias to the first node N1. In an embodiment, the fifth power voltage Vbias may have a level similar to a voltage level of a data signal of a black grayscale. For example, the fifth power voltage Vbias may have a voltage level of about 5 to 7V”);
in the first light-emitting phase, controlling, by the first light-emitting control circuit, a first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal provided by a light-emitting control line, and controlling, by the second light-emitting control circuit, the second electrode of the driving transistor to be electrically connected to a first electrode of the light-emitting element under the control of the light-emitting control signal, and driving, by the driving transistor, the light-emitting element (Jeong: [0111]-[0114], “The sixth transistor T6 may be connected between the first power line PL1 and the first node N1. A gate electrode of the sixth transistor T6 may be connected to an i-th first emission control line E1i (hereinafter, referred to as a first emission control line). The sixth transistor T6 may be turned off when the first emission control signal is supplied to the first emission control line E1i, and may be turned on in other cases. When the sixth transistor T6 is turned on, the first node N1 may be electrically connected to the first power line PL1. The seventh transistor T7 may be connected between the second node N2 and the fifth node N5 (or the first electrode of the light emitting element LD). A gate electrode of the seventh transistor T7 may be connected to an i-th second emission control line E2i (hereinafter, referred to as a second emission control line). The seventh transistor T7 may be turned off when the second emission control signal is supplied to the second emission control line E2i, and may be turned on in other cases. When the seventh transistor T7 is turned on, the second node N2 and the fifth node N5 may be electrically connected.).
Regarding claim 18, the combination of Jeong and Zhou further discloses wherein the display period further comprises a maintenance frame; the maintenance frame comprises a second bias phase and a second light-emitting phase arranged sequentially in that order; the driving method comprises:
in at least part of the second bias phase, writing, by the reference voltage writing circuit, the reference voltage into the first electrode of the driving transistor or the second electrode of the driving transistor under the control of the scanning signal (Jeong: [0123], “The ninth transistor T9 may be turned on when the third scan signal is supplied to the third scan line S3i to supply the fifth power voltage Vbias to the first node N1. In an embodiment, the fifth power voltage Vbias may have a level similar to a voltage level of a data signal of a black grayscale. For example, the fifth power voltage Vbias may have a voltage level of about 5 to 7V”);
in the second light-emitting phase, controlling, by a first light-emitting control circuit, a first voltage end to be electrically connected to the first electrode of the driving transistor under the control of a light-emitting control signal provided by a light-emitting control line (Jeong: [0112], “The sixth transistor T6 may be turned off when the first emission control signal is supplied to the first emission control line E1i, and may be turned on in other cases. When the sixth transistor T6 is turned on, the first node N1 may be electrically connected to the first power line PL1.”), and controlling, by a second light-emitting control circuit, the second electrode of the driving transistor to be electrically connected to a first electrode of a light-emitting element under the control of the light-emitting control signal (Jeong: [0114], “The seventh transistor T7 may be turned off when the second emission control signal is supplied to the second emission control line E2i, and may be turned on in other cases. When the seventh transistor T7 is turned on, the second node N2 and the fifth node N5 may be electrically connected.”), and driving, by the driving transistor, the light-emitting element (Jeong: [0100], “The first transistor T1 may control a driving current flowing from a first power line PL1 providing the first power voltage VDD to a second power line PL2 providing the second power voltage VSS via the light emitting element LD in response to a voltage of the third node N3”).
Regarding claim 19, the combination of Jeong and Zhou further discloses a display device (Jeong: fig. 1, display device 1000), comprising the pixel circuit according to claim 1.
Regarding claim 20, the combination of Jeong and Zhou further discloses wherein a ratio of the voltage difference threshold to an absolute value of a threshold voltage of the driving transistor is greater than or equal to 0.8 and less than or equal to 1.2 (Zhou: [0042], “Vg=Vdata +VDD+Vth, Vgs=(Vdata+VDD+Vth)−(Vdata+VDD)=Vth” where Vgs is the difference between the potential at the gate electrode and the potential at the source electrode and therefore if Vgs=Vth then the ratio of Vgs/Vth=1).
Claims 21-25 are within the scope of claims 8-12 respectively and are therefore interpreted and rejected based on similar reasoning.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. (US PGPub 2023/0112488) discloses a circuit diagram illustrating an example of a pixel (fig. 4).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629