DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 202310812831.8, filed on 30th, June 2023.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“…the control line is electrically coupled to the at least two data drivers through at least three access points…” (Claim 13)
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1, 7-8, and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (US Patent/PGPub. No. 20190147786).
Regarding Claim 1, (Original)
KIM et al. teach
a multiplexer circuit ([0065], FIG. 2 & 4, i.e. MUX driver 140-1), electrically coupled to M data voltage providing ends ([0066], FIG. 2 & 4, i.e. first output channel Ch1 … second output channel Ch2) and a plurality of data lines ([0066], FIG. 2 & 4, i.e. first to third data lines DL1, DL2, and DL3… fourth to sixth data lines DL4, DL5, and DL6), the multiplexer circuit comprising N multiplexing control lines ([0066], FIG. 2 & 4, i.e. first and second control signals S1 and S2) and N multiplexing circuits ([0049], FIG. 2 & 4, i.e. circuits corresponding to S1 and S2), an nth multiplexing circuit comprising M multiplexing sub-circuits ([0049], FIG. 2 & 4, i.e. S1 (group TM1, TM2, and TM3) or S2 (group TM4, TM5, and TM6) 3 circuits each), and an nth multiplexing control line ([0066], FIG. 2 & 4, i.e. each of S1 and S2) comprising M control lines ([0063], FIG. 2 & 4, i.e. MCS 1-1, MCS 2-1, and MCS 3-1 corresponding to S1 and MCS 1-2, MCS 2-2, and MCS 3-2 corresponding to S2),
wherein an mth multiplexing sub-circuit ([0049], FIG. 2 & 4, i.e. each of MUX switches) comprised in the nth multiplexing circuit (i.e. please see above citation(s)) is electrically coupled to an mth control line ([0063], FIG. 2 & 4, i.e. each of MCS 1-1, MCS 2-1, MCS 3-1, MCS 1-2, MCS 2-2, or MCS 3-2) in the nth multiplexing control line (i.e. please see above citation(s)), an mth data voltage providing end ([0066], FIG. 2 & 4, i.e. one of Ch1 or Ch2) and a corresponding data line ([0050], FIG. 2 & 4, i.e. one of DL1 to DL6), and configured to write a data voltage ([0050], FIG. 2 & 4, i.e. one of data voltages to DL1-DL6) provided by the mth data voltage providing end into the corresponding data line ([0050], FIG. 2 & 4, i.e. first output channel Ch1 and the second output channel Ch2 may supply … to the first to sixth data lines DL1 to DL6) under the control of a control signal ([0051], FIG. 2 & 4, i.e. one of MCS 1-1, MCS 2-1, MCS 3-1, MCS 1-2, MCS 2-2, or MCS 3-2) provided by the mth control line (i.e. please see above citation(s)), where N and M are both integers greater than 1 ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) N = M = 2 > 1), n is a positive integer smaller than or equal to N ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) n = N = 2), and m is a positive integer smaller than or equal to M ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) m = N = 6).
Regarding Claim 7, (Currently Amended)
KIM et al. teach
a multiplexing module ([0065], FIG. 2 & 4, i.e. MUX driver 140-1), comprising a plurality of multiplexer circuits ([0049], FIG. 2 & 4, i.e. Ch1 (group of TM1, TM2, and TM3) and Ch2 (group of TM4, TM5, and TM6)), wherein the multiplexer circuit is electrically coupled to M data voltage providing ends ([0066], FIG. 2 & 4, i.e. first output channel Ch1 … second output channel Ch2) and a plurality of data lines ([0066], FIG. 2 & 4, i.e. first to third data lines DL1, DL2, and DL3… fourth to sixth data lines DL4, DL5, and DL6), the multiplexer circuit comprises N multiplexing control lines ([0066], FIG. 2 & 4, i.e. first and second control signals S1 and S2) and N multiplexing circuits ([0049], FIG. 2 & 4, i.e. circuits corresponding to S1 and S2), an nth multiplexing circuit comprises M multiplexing sub-circuits ([0049], FIG. 2 & 4, i.e. S1 (group TM1, TM2, and TM3) or S2 (group TM4, TM5, and TM6) 3 circuits each), and an nth multiplexing control line ([0066], FIG. 2 & 4, i.e. each of S1 and S2) comprises M control lines ([0063], FIG. 2 & 4, i.e. MCS 1-1, MCS 2-1, and MCS 3-1 corresponding to S1 and MCS 1-2, MCS 2-2, and MCS 3-2 corresponding to S2),
wherein an mth multiplexing sub-circuit ([0049], FIG. 2 & 4, i.e. each of MUX switches) comprised in the nth multiplexing circuit (i.e. please see above citation(s)) is electrically coupled to an mth control line ([0063], FIG. 2 & 4, i.e. MCS 1-1, MCS 2-1, MCS 3-1, MCS 1-2, MCS 2-2, or MCS 3-2) in the nth multiplexing control line (i.e. please see above citation(s)), an mth data voltage providing end ([0066], FIG. 2 & 4, i.e. one of Ch1 or Ch2) and a corresponding data line ([0050], FIG. 2 & 4, i.e. one of DL1 to DL6), and configured to write a data voltage ([0050], FIG. 2 & 4, i.e. one of data voltages to DL1-DL6) provided by the mth data voltage providing end into the corresponding data line ([0050], FIG. 2 & 4, i.e. first output channel Ch1 and the second output channel Ch2 may supply … to the first to sixth data lines DL1 to DL6) under the control of a control signal ([0051], FIG. 2 & 4, i.e. one of MCS 1-1, MCS 2-1, MCS 3-1, MCS 1-2, MCS 2-2, or MCS 3-2) provided by the mth control line (i.e. please see above citation(s)), where N and M are both integers greater than 1 ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) N = M = 2 > 1), n is a positive integer smaller than or equal to N ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) n = N = 2), and m is a positive integer smaller than or equal to M ([0063], FIG. 2 & 4, i.e. as shown by the figure(s) m = N = 6).
Regarding Claim 8, (Original)
KIM et al. teach
a display device ([0033], FIG. 1, i.e. display device 100), comprising a data driver ([0033], FIG. 1, i.e. data driver 130), a plurality of data lines ([0035], FIG. 1, i.e. data lines DL1 to DLm), and the multiplexing module according to claim 7, wherein the data driver (i.e. please see above citation(s)) is configured to provide a data voltage ([0043], FIG. 1, i.e. a data voltage) to the multiplexing module through a data voltage providing end ([0050], FIG. 2 & 4, i.e. first output channel Ch1 and the second output channel Ch2), and each of the data lines ([0050], FIG. 2 & 4, i.e. first to third data lines DL1, DL2, and DL3 which are electrically connected to a first output channel Ch1 of the data driver 130 and fourth to sixth data lines DL4, DL5, and DL6) is configured to receive a data voltage ([0050], FIG. 2 & 4, i.e. may supply red data, green data, and blue data to the first to sixth data lines DL1 to DL6) provided by the multiplexing module (i.e. please see above citation(s)).
Regarding Claim 15, (Currently Amended)
KIM et al. teach
the display device according to claim 8, further comprising a plurality of gate lines ([0035], FIG. 1, i.e. gate lines GL1 to GLn) and a plurality of pixel circuits ([0034], FIG. 1, i.e. plurality of pixels P) arranged in rows and columns (FIG. 1, i.e. as shown by the GLx rows and DLy columns), wherein each of the pixel circuits is electrically coupled to ([0035], FIG. 1, i.e. plurality of pixels P is electrically connected to the n gate lines GL1 to GLn and the m data lines DL1 to DLm) a corresponding gate line ([0035], FIG. 1, i.e. gate lines GL1 to GLn) and a corresponding data line ([0035], FIG. 1, i.e. data lines DL1 to DLm), and configured to receive a data voltage ([0035], FIG. 1, i.e. driving signal or a driving voltage) provided by the corresponding data line under the control of a gate driving signal ([0037], FIG. 1, i.e. gate signals to the gate lines GL1 to GLn in accordance with a gate driving control signal GCS) provided by the corresponding gate line (i.e. please see above citation(s)).
Regarding Claim 16, (Currently Amended)
KIM et al. teach
a driving method ([0011], FIG. 1, i.e. MUX driving), for a display device ([0033], FIG. 1, i.e. display device 100) according to claim 8 (i.e. please see above citation(s)), comprising:
providing, by a data driver ([0033], FIG. 1, i.e. data driver 130), a data voltage ([0043], FIG. 1, i.e. a data voltage) for a multiplexing module ([0065], FIG. 2 & 4, i.e. MUX driver 140-1) through a data voltage providing end ([0066], FIG. 2 & 4, i.e. first output channel Ch1 … second output channel Ch2); and
receiving, by a data line ([0066], FIG. 2 & 4, i.e. first to third data lines DL1, DL2, and DL3… fourth to sixth data lines DL4, DL5, and DL6), a data voltage ([0050], FIG. 2 & 4, i.e. first output channel Ch1 and the second output channel Ch2 may supply red data, green data, and blue data to the first to sixth data lines DL1 to DL6) provided by the multiplexing module (i.e. please see above citation(s)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 2-6 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US Patent/PGPub. No. 20190147786) in view of ZHANG et al. (US Patent/PGPub. No. 20230066643).
Regarding Claim 2, (Original)
KIM et al. teach
the multiplexer circuit according to claim 1.
However, KIM et al. do not explicitly teach
the multiplexer circuit comprises a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit;
the first multiplexing control line comprises a first control line and a second control line, and the second multiplexing control line comprises a third control line and a fourth control line;
the first multiplexing circuit comprises a first multiplexing sub-circuit and a second multiplexing sub-circuit, and the second multiplexing circuit comprises a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;
the first multiplexing sub-circuit is electrically coupled to the first control line, a first data voltage providing end and a first data line, and configured to write a data voltage provided by the first data voltage providing end into the first data line under the control of a first control signal provided by the first control line;
the second multiplexing sub-circuit is electrically coupled to the second control line, a second data voltage providing end and a second data line, and configured to write a data voltage provided by the second data voltage providing end into the second data line under the control of a second control signal provided by the second control line;
the third multiplexing sub-circuit is electrically coupled to the third control line, the first data voltage providing end and a third data line, and configured to write the data voltage provided by the first data voltage providing end into the third data line under the control of a third control signal provided by the third control line; and
the fourth multiplexing sub-circuit is electrically coupled to the fourth control line, the second data voltage providing end and a fourth data line, and configured to write the data voltage provided by the second data voltage providing end into the fourth data line under the control of a fourth control signal provided by the fourth control line.
In the same field of endeavor, ZHANG et al. teach
the multiplexer circuit ([0026], FIG. 2, i.e. multiplexing circuit 200) comprises a first multiplexing control line ([0039], FIG. 2, i.e. strobe signals M1 and M2), a second multiplexing control line ([0039], FIG. 2, i.e. strobe signals M3 and M4), a first multiplexing circuit ([0040], FIG. 2, i.e. multiplexing module 210 (left side)) and a second multiplexing circuit ([0040], FIG. 2, i.e. multiplexing module 210 (right side));
the first multiplexing control line (i.e. please see above citation(s)) comprises a first control line ([0039], FIG. 2, i.e. M1 line) and a second control line ([0039], FIG. 2, i.e. M2 line), and the second multiplexing control line (i.e. please see above citation(s)) comprises a third control line ([0039], FIG. 2, i.e. M3 line) and a fourth control line ([0039], FIG. 2, i.e. M4 line);
the first multiplexing circuit (i.e. please see above citation(s)) comprises a first multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T1) and a second multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T4), and the second multiplexing circuit (i.e. please see above citation(s)) comprises a third multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T5) and a fourth multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T8);
the first multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T1 connected to M1, S1, and DL that connected to T1) the first control line (i.e. please see above citation(s)), a first data voltage providing end ([0039], FIG. 2, i.e. S1) and a first data line ([0011], FIG. 2, i.e. first data line (DL that connected to T1)), and configured to write a data voltage ([0039], FIG. 2, i.e. pre-charge source driving signals S1) provided by the first data voltage providing end ([0039], FIG. 2, i.e. S1 line) into the first data line under the control of a first control signal ([0039], FIG. 2, i.e. strobe signal M1) provided by the first control line (i.e. please see above citation(s));
the second multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T4 connected to M2, S2, and DL that connected to T4) the second control line, a second data voltage providing end ([0039], FIG. 2, i.e. S2) and a second data line ([0013], FIG. 2, i.e. seventh data line DL (DL that connected to T4)), and configured to write a data voltage ([0039], FIG. 2, i.e. pre-charge source driving signals S1) provided by the second data voltage providing end ([0039], FIG. 2, i.e. S1 line) into the second data line (i.e. please see above citation(s)) under the control of a second control signal ([0039], FIG. 2, i.e. strobe signal M2) provided by the second control line (i.e. please see above citation(s));
the third multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T5 connected to M3, S1, and DL that connected to T5) the third control line, the first data voltage providing end and a third data line ([0011], FIG. 2, i.e. second data line (DL that connected to T5)), and configured to write the data voltage provided by the first data voltage providing end into the third data line (i.e. please see above citation(s)) under the control of a third control signal ([0039], FIG. 2, i.e. strobe signal M3) provided by the third control line (i.e. please see above citation(s)); and
the fourth multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T8 connected to M4, S2, and DL that connected to T8) the fourth control line, the second data voltage providing end (i.e. please see above citation(s)) and a fourth data line ([0013], FIG. 2, i.e. eighth data line DL (DL that connected to T8)), and configured to write the data voltage provided by the second data voltage providing end into the fourth data line (i.e. please see above citation(s)) under the control of a fourth control signal ([0039], FIG. 2, i.e. strobe signal M4) provided by the fourth control line (i.e. please see above citation(s)).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to modify KIM et al. teaching of MUX circuit in FIG. 4 with ZHANG et al. teaching of MUX circuit in FIG. 2 by rearranging MUX sub-circuits and connections to data providing inputs, control signals, and data lines to effectively reduce input lines yet timely enhance data signal transmission by altering connections among input lines, control lines, data lines, and MUX sub-circuits (ZHANG et al. Abstract).
Regarding Claim 3, (Original)
the multiplexer circuit according to claim 2, wherein
ZHANG et al. teach
the first multiplexing sub-circuit (i.e. please see above citation(s)) comprises a first transistor ([0038], FIG. 2, i.e. thin film transistor T1), and the second multiplexing sub-circuit (i.e. please see above citation(s)) comprises a second transistor ([0038], FIG. 2, i.e. thin film transistor T4);
a gate electrode ([0038], FIG. 2, i.e. T1’s gate) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T1 … turned on by control of strobe signals M1) the first control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T1’s bottom electrode) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S1) the first data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T1’s top electrode) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. odd-numbered data lines) the first data line (i.e. please see above citation(s)); and
a gate electrode ([0038], FIG. 2, i.e. T4’s gate) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T4 … turned on by control of … strobe signals M2) the second control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T4’s bottom electrode) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S2) the second data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T4’s top electrode) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. even-numbered data lines) the second data line (i.e. please see above citation(s)).
Regarding Claim 4, (Original)
the multiplexer circuit according to claim 3, wherein
ZHANG et al. teach
the first transistor and the second transistor (i.e. please see above citation(s)) are n-type transistors ([0043], FIG. 2, i.e. N-channel thin film transistor), or the first transistor and the second transistor (i.e. please see above citation(s)) are p-type transistors ([0043], FIG. 2, i.e. P-channel thin film transistor).
Regarding Claim 5, (Original)
the multiplexer circuit according to claim 2, wherein
ZHANG et al. teach
the third multiplexing sub-circuit (i.e. please see above citation(s)) comprises a third transistor ([0038], FIG. 2, i.e. thin film transistor T5), and the fourth multiplexing sub-circuit (i.e. please see above citation(s)) comprises a fourth transistor ([0038], FIG. 2, i.e. thin film transistor T8);
a gate electrode ([0038], FIG. 2, i.e. T5’s gate) of the third transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T5 … turned on by control of strobe signals M3) the third control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T5’s bottom electrode) of the third transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S1) the first data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T5’s top electrode) of the third transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. even-numbered data lines) the third data line (i.e. please see above citation(s)); and
a gate electrode ([0038], FIG. 2, i.e. T8’s gate) of the fourth transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T4 … turned on by control of … strobe signals M4) the fourth control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T8’s bottom electrode) of the fourth transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S2) the second data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T8’s top electrode) of the fourth transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. even-numbered data lines) the fourth data line (i.e. please see above citation(s)).
Regarding Claim 6, (Original)
the multiplexer circuit according to claim 5, wherein
ZHANG et al. teach
the third transistor and the fourth transistor (i.e. please see above citation(s)) are n-type transistors ([0043], FIG. 2, i.e. N-channel thin film transistor); or
the third transistor and the fourth transistor (i.e. please see above citation(s)) are p-type transistors ([0043], FIG. 2, i.e. N-channel thin film transistor).
Regarding Claim 19, (New)
KIM et al. teach
the multiplexing module according to claim 7.
However, KIM et al. do not explicitly teach
the multiplexer circuit comprises a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit;
the first multiplexing control line comprises a first control line and a second control line, and the second multiplexing control line comprises a third control line and a fourth control line;
the first multiplexing circuit comprises a first multiplexing sub-circuit and a second multiplexing sub-circuit, and the second multiplexing circuit comprises a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;
the first multiplexing sub-circuit is electrically coupled to the first control line, a first data voltage providing end and a first data line, and configured to write a data voltage provided by the first data voltage providing end into the first data line under the control of a first control signal provided by the first control line;
the second multiplexing sub-circuit is electrically coupled to the second control line, a second data voltage providing end and a second data line, and configured to write a data voltage provided by the second data voltage providing end into the second data line under the control of a second control signal provided by the second control line;
the third multiplexing sub-circuit is electrically coupled to the third control line, the first data voltage providing end and a third data line, and configured to write the data voltage provided by the first data voltage providing end into the third data line under the control of a third control signal provided by the third control line; and
the fourth multiplexing sub-circuit is electrically coupled to the fourth control line, the second data voltage providing end and a fourth data line, and configured to write the data voltage provided by the second data voltage providing end into the fourth data line under the control of a fourth control signal provided by the fourth control line.
In the same field of endeavor, ZHANG et al. teach
the multiplexer circuit ([0026], FIG. 2, i.e. multiplexing circuit 200) comprises a first multiplexing control line ([0039], FIG. 2, i.e. strobe signals M1 and M2), a second multiplexing control line ([0039], FIG. 2, i.e. strobe signals M3 and M4), a first multiplexing circuit ([0040], FIG. 2, i.e. multiplexing module 210 (left side)) and a second multiplexing circuit ([0040], FIG. 2, i.e. multiplexing module 210 (right side));
the first multiplexing control line (i.e. please see above citation(s)) comprises a first control line ([0039], FIG. 2, i.e. M1 line) and a second control line ([0039], FIG. 2, i.e. M2 line), and the second multiplexing control line (i.e. please see above citation(s)) comprises a third control line ([0039], FIG. 2, i.e. M3 line) and a fourth control line ([0039], FIG. 2, i.e. M4 line);
the first multiplexing circuit (i.e. please see above citation(s)) comprises a first multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T1) and a second multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T4), and the second multiplexing circuit (i.e. please see above citation(s)) comprises a third multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T5) and a fourth multiplexing sub-circuit ([0038], FIG. 2, i.e. thin film transistor T8);
the first multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T1 connected to M1, S1, and DL that connected to T1) the first control line (i.e. please see above citation(s)), a first data voltage providing end ([0039], FIG. 2, i.e. S1) and a first data line ([0011], FIG. 2, i.e. first data line (DL that connected to T1)), and configured to write a data voltage ([0039], FIG. 2, i.e. pre-charge source driving signals S1) provided by the first data voltage providing end ([0039], FIG. 2, i.e. S1 line) into the first data line under the control of a first control signal ([0039], FIG. 2, i.e. strobe signal M1) provided by the first control line (i.e. please see above citation(s));
the second multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T4 connected to M2, S2, and DL that connected to T4) the second control line, a second data voltage providing end ([0039], FIG. 2, i.e. S2) and a second data line ([0013], FIG. 2, i.e. seventh data line DL (DL that connected to T4)), and configured to write a data voltage ([0039], FIG. 2, i.e. pre-charge source driving signals S1) provided by the second data voltage providing end ([0039], FIG. 2, i.e. S1 line) into the second data line (i.e. please see above citation(s)) under the control of a second control signal ([0039], FIG. 2, i.e. strobe signal M2) provided by the second control line (i.e. please see above citation(s));
the third multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T5 connected to M3, S1, and DL that connected to T5) the third control line, the first data voltage providing end and a third data line ([0011], FIG. 2, i.e. second data line (DL that connected to T5)), and configured to write the data voltage provided by the first data voltage providing end into the third data line (i.e. please see above citation(s)) under the control of a third control signal ([0039], FIG. 2, i.e. strobe signal M3) provided by the third control line (i.e. please see above citation(s)); and
the fourth multiplexing sub-circuit (i.e. please see above citation(s)) is electrically coupled to (FIG. 2, i.e. as shown by the figure(s) T8 connected to M4, S2, and DL that connected to T8) the fourth control line, the second data voltage providing end (i.e. please see above citation(s)) and a fourth data line ([0013], FIG. 2, i.e. eighth data line DL (DL that connected to T8)), and configured to write the data voltage provided by the second data voltage providing end into the fourth data line (i.e. please see above citation(s)) under the control of a fourth control signal ([0039], FIG. 2, i.e. strobe signal M4) provided by the fourth control line (i.e. please see above citation(s)).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to modify KIM et al. teaching of MUX circuit in FIG. 4 with ZHANG et al. teaching of MUX circuit in FIG. 2 by rearranging MUX sub-circuits and connections to data providing inputs, control signals, and data lines to effectively reduce input lines yet timely enhance data signal transmission by altering connections among input lines, control lines, data lines, and MUX sub-circuits (ZHANG et al. Abstract).
Regarding Claim 20, (New)
the multiplexing module according to claim 19, wherein
ZHANG et al. teach
the first multiplexing sub-circuit (i.e. please see above citation(s)) comprises a first transistor ([0038], FIG. 2, i.e. thin film transistor T1), and the second multiplexing sub-circuit (i.e. please see above citation(s)) comprises a second transistor ([0038], FIG. 2, i.e. thin film transistor T4);
a gate electrode ([0038], FIG. 2, i.e. T1’s gate) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T1 … turned on by control of strobe signals M1) the first control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T1’s bottom electrode) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S1) the first data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T1’s top electrode) of the first transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. odd-numbered data lines) the first data line (i.e. please see above citation(s)); and
a gate electrode ([0038], FIG. 2, i.e. T4’s gate) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. T4 … turned on by control of … strobe signals M2) the second control line (i.e. please see above citation(s)), a first electrode ([0039], FIG. 2, i.e. T4’s bottom electrode) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. to pre-charge source driving signals S2) the second data voltage providing end (i.e. please see above citation(s)), and a second electrode ([0039], FIG. 2, i.e. T4’s top electrode) of the second transistor (i.e. please see above citation(s)) is electrically coupled to ([0039], FIG. 2, i.e. even-numbered data lines) the second data line (i.e. please see above citation(s)).
6. Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US Patent/PGPub. No. 20190147786) in view of OH et al. (US Patent/PGPub. No. 20240192797).
Regarding Claim 9, (Original)
KIM et al. teach
the display device according to claim 8.
However, KIM et al. do not explicitly teach
the data driver provides a control signal for each control line through at least one corresponding output channel.
In the same field of endeavor, OH et al. teach
the data driver ([0090], FIG. 1-2, i.e. the timing controller 130 … the data driver 110 … may be integrated into one drive IC (D-IC)) provides a control signal ([0094], FIG. 1-2, i.e. timing controller 130 generates … a de-multiplexer control signal for controlling the operation timing of the de-multiplexer array 112) for each control line through at least one corresponding output channel ([0092], [0094], FIG. 1-2, i.e. since timing controller and data driver are integrated, control line would have been provided to de-multiplexer array 112 through output channel, data line as shown by the figure(s)).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to modify KIM et al. teaching of display comprising separate timing controller, data driver, and MUX circuit with OH et al. teaching of display comprising integrated time controller and data driver in addition to MUX circuit to effectively reduce the non-display area by combining time controller and data driver (OH et al.’s FIG. 2).
Regarding Claim 10, (Original)
KIM et al. teach
the display device according to claim 8, wherein the display device (i.e. please see above citation(s)) comprises a display panel ([0033], FIG. 1, i.e. display panel 110), one data driver ([0033], FIG. 1, i.e. data driver 130) and a plurality of control lines ([0066], FIG. 2 & 4, i.e. first and second control signals S1 and S2);
the data driver (i.e. please see above citation(s)) is arranged at a first side (FIG. 1, i.e. top side as shown by the figure) of the display panel, the plurality of control lines (i.e. please see above citation(s)) is arranged between (FIG. 1-2 & 4, i.e. as shown by the figure(s) S1/S2 is between data driver 13 and display area A/A) the data driver and an active display region ([0035], FIG. 1, i.e. In the display area A/A) of the display panel (i.e. please see above citation(s)).
However, KIM et al. do not explicitly teach
the data driver is further configured to provide the control signal to be inputted into the control line.
In the same field of endeavor, OH et al. teach
the data driver ([0090], FIG. 1-2, i.e. the timing controller 130 … the data driver 110 … may be integrated into one drive IC (D-IC)) is further configured to provide the control signal ([0094], FIG. 1-2, i.e. timing controller 130 generates … a de-multiplexer control signal for controlling the operation timing of the de-multiplexer array 112) to be inputted into the control line ([0092], [0094], FIG. 1-2, i.e. since timing controller and data driver are integrated, control line would have been provided to de-multiplexer array 112 through output channel, data line as shown by the figure(s)).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to modify KIM et al. teaching of display comprising separate timing controller, data driver, and MUX circuit with OH et al. teaching of display comprising integrated time controller and data driver in addition to MUX circuit to effectively reduce the non-display area by combining time controller and data driver (OH et al.’s FIG. 2).
7. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US Patent/PGPub. No. 20190147786) in view of OH et al. (US Patent/PGPub. No. 20240192797) and Watanabe et al. (US Patent/PGPub. No. 20240379047).
Regarding Claim 12, (Original)
the display device according to claim 9, wherein
KIM et al. teach
the data driver (i.e. please see above citation(s)) is arranged at a first side (FIG. 1, i.e. top side as shown by the figure) of the display panel, the plurality of control lines (i.e. please see above citation(s)) is arranged between (FIG. 1-2 & 4, i.e. as shown by the figure(s) S1/S2 is between data driver 13 and display area A/A) the data driver and an active display region ([0035], FIG. 1, i.e. In the display area A/A) of the display panel (i.e. please see above citation(s)); and
OH et al. teach
the data driver ([0090], FIG. 1-2, i.e. the timing controller 130 … the data driver 110 … may be integrated into one drive IC (D-IC)) is further configured to provide the control signal ([0094], FIG. 1-2, i.e. timing controller 130 generates … a de-multiplexer control signal for controlling the operation timing of the de-multiplexer array 112) to be inputted into the control line ([0092], [0094], FIG. 1-2, i.e. since timing controller and data driver are integrated, control line would have been provided to de-multiplexer array 112 through output channel, data line as shown by the figure(s)).
However, KIM et al. and OH et al. do not explicitly teach
the display device comprises a display panel, at least two data drivers and a plurality of control lines.
In the same field of endeavor, Watanabe et al. teach
the display device ([0028], FIG. 1, i.e. display device) comprises a display panel ([0030], FIG. 1, i.e. panel of display device), at least two data drivers ([0028], FIG. 1, i.e. plurality of data driver circuits) and a plurality of control lines ([0030], FIG. 1, i.e. and two clock signal lines CL_1 and CL_2).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine KIM et al. and OH et al. teaching of display comprising timing controller, data driver, control signals, and MUX circuit with Watanabe et al. teaching of display comprising timing controller, multiple data drivers, control signals, and MUX circuit to effectively compensate threshold voltage of driving transistor providing correct brightness to pixels (Watanabe et al.’s [0039]).
Allowable Subject Matter
8. Claim(s) 11, 13-14 and 17-18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The following is an examiner’s statement of reasons for allowance:
KIM et al. (US Patent/PGPub. No. 20190147786) teach a display panel which includes a plurality of pixels including a plurality of sub pixels implementing different colors and a plurality of data lines connected to the sub pixels, a data driver including a first output channel and a second output channel for supplying a data signal to a corresponding one of the plurality of data lines; and a MUX driver disposed between the display panel and the data driver, and controls data outputs of the plurality of data lines connected to the first output channel and the second output channel in accordance with a resolution of an image signal input from the outside.
ZHANG et al. (US Patent/PGPub. No. 20230066643) teach a display panel and a display device are provided. In the display panel, at least one odd-numbered thin film transistor is sequentially turned on to charge sub-pixels of a corresponding odd-numbered row before charging sub-pixels of any one of odd-numbered rows is finished, and at least one even-numbered thin film transistor is sequentially turned on to charge sub-pixels of a corresponding even-numbered row before charging sub-pixels of any one of even-numbered rows is finished, thereby saving the number of uses of data traces and thin film transistors, as well as enhancing the timeliness of data signal transmission.
The subject matter of the claim(s) that could neither be found/suggested nor obviously combinable in the prior arts of record. The subject matter was a device/method including
“…the control line comprises a first end and a second end; and
a first output channel of the data driver is electrically coupled to the first end, a second output channel of the data driver is electrically coupled to the second end, and the data driver is configured to provide the control signal to the first end through the first output channel, and provide the control signal to the second end through the second output channel.” (Claim 11),
“…the control line is electrically coupled to the at least two data drivers through at least three access points, and configured to receive the control signal provided by the data driver.” (Claim 13),
“…the display device further comprises a plurality of gate lines and two multiplexing control lines;
in a case that a (2a-1)th gate line is enabled, a first multiplexing control line controls a corresponding multiplexing transistor to be turned on, and then a second multiplexing control line controls a corresponding multiplexing transistor to be turned on; and
in a case that a (2a)th gate line is enabled, the second multiplexing control line controls the corresponding multiplexing transistor to be turned on, and then the first multiplexing control line controls the corresponding multiplexing transistor to be turned on, where a is a positive integer.” (Claim 17),
“…the display device further comprises a plurality of gate lines and two multiplexing control lines;
in a case that a (2a-1)th gate line is enabled, a second multiplexing control line controls a corresponding multiplexing transistor to be turned on, and then a first multiplexing control line controls a corresponding multiplexing transistor to be turned on; and
in a case that a (2a)th gate line is enabled, the first multiplexing control line controls the corresponding multiplexing transistor to be turned on, and then the second multiplexing control line controls the corresponding multiplexing transistor to be turned on, where a is a positive integer.” (Claim 18),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/VINH T LAM/Primary Examiner, Art Unit 2628