DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims, 21, 25-27, 29-31, 35-38, 40 are rejected under 35 U.S.C. 103 as being unpatentable over Parker et al (US 6810480, Parker) in view of Wehbe et al (US 20210200873, Wehbe).
As to claim 21, Parker discloses a method (fig 5), comprising:
obtaining a first value (s50, col 5 lns 53-56 “using a second biometric sample) and a second value (s43 “templates retrieved”) both associated with access to a computer resource (s48 “session associated with ID”);
performing a first comparison of the first value with the second value (s51, col 5 lns 55-60);
based on the first comparison indicating that the first value matches the second value (“if the identify matches”), performing a second comparison of the first value with the second value (col 5 lns 55-60 “a return is made to step 48” which executes step 51 again);
based on the second comparison indicating that the first value matches the second value, generating a signal (s48 to grant access); and
based on the second comparison indicating that the first value differs from the second value, generating another signal (s47).
Parker does not disclose the signal (s48 to grant access) to trigger a first interrupt service routine (ISR) and the another signal to trigger a second interrupt service routine. In the same field of art (status updating), Wehbe discloses a method including requesting an instruction block associated with one or more instructions (par. 4). In one embodiment, Wehbe further discloses a method (fig. 7), comprising: obtaining a first value (fig. 5 s550 “runtime hash) and a second value (s560 “expected hash) both associated with access to a computer resource (Note: Hashes are associated to a computer resource); performing a comparison of the first value with the second value (s570, par. 46); and based on the comparison indicating that the first value matches the second value (par. 48), generating a signal to trigger a first interrupt service routine (ISR) (fi. 6 s630 “send success Interrupt to system processor”) and based on the comparison indicating that the first value differs from the second value (par. 48 “does not match”), generating a signal to trigger a second ISR (s620 “send failure interrupt to system processor”), the second ISR differing from the first ISR (fig. 6). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Parker and Wehbe, by, based on the second comparison indicating that the first value matches the second value, generating a signal to trigger a first ISR, and based on the second comparison indicating that the first value differs from the second value, generating a signal to trigger a second ISR, the second ISR differing from the first ISR. The motivation is to improve the security of the system (par. 3).
As to claim 25, Parker/Wehbe discloses the method of claim 21, further comprising: enabling, by the first ISR (Wehbe, fig. 7 s721 “send interrupt vector to core to start ISR”), a third comparison of the first value with the second value (fig. 5. Note: Multiple comparisons are made at s51).
As to claim 26, Parker/Wehbe discloses the method of claim 25, further comprising: accessing, by the first ISR, a register (Parker, col 4 lns 50-60. Note: It requires a register to store “second biometric sample” for comparison) to determine whether or not to enable the access to the computer resource (fig. 5, s48).
As to claim 27, Parker/Wehbe discloses the method of claim 26, wherein the access of the first ISR to the register is allowed based on the third comparison indicating that the first value matches the second value (Parker, col 4 lns 50-60. Note: A loop is made to step 48 when identity matches).
As to claim 29, Parker/Wehbe discloses the method of claim 21, further comprising: disabling, by the second ISR (Wehbe, fig. 7 s723 “send request for interrupt vector to interrupt controller”), the access to the computer resource (Parker, fig. 5, s47).
As to claim 30, Parker/Wehbe discloses the method of claim 21, wherein the first value includes a digital signature associated with the access to the computer resource, and the second value includes a previously-validated digital signature associated with the access to the computer resource (col 4 ln 10-15 fingerprint, signature…).
As to claim 31, all the same elements of claim 21 are listed, but in a system form (Wehbe, comparison logic 250, par. 29). Therefore, the supporting rationale of the rejection to claim 21 applies equally to claim 31.
As to claim 35, Parker/Wehbe discloses the system of claim 31, further comprising:
a microcontroller (Wehbe, par. 25, hardware controller 210) configured to service the first ISR to enable a third comparison of the first value with the second value (Parker, s51).
As to claim 36, Parker/Wehbe discloses the system of claim 35, wherein the comparator circuit is configured to: perform the third comparison of the first value with the second value (Parker s51; Wehbe, fig. 2 comparator 250).
As to claim 37, Parker/Wehbe discloses the system of claim 36, wherein the comparator circuit is configured to:
determine whether or not to allow access of the first ISR to a register (Parker, s47 or s48) based on whether or not the third comparison indicating that the first value matches the second value (col 4 lns 50-60. Note: It requires a register to store “second biometric sample” for comparison).
As to claim 38, Parker/Wehbe discloses the system of claim 37, wherein the microcontroller is configured to enable the access to the computer resource based on that the first ISR is allowed to access to the register (Parker, fig. 7 s48).
As to claim 40, Parker/Wehbe discloses the system of claim 31, further comprising: a microcontroller configured to service the second ISR to disable the access to the computer resource (Parker, s47).
Claims 22, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Parker in view of Wehbe and further in view of Zeh et al (US 20200065486, Zeh).
As to claim 22, Parker/Wehbe discloses the method of claim 21, but does not disclose the limitations in claim 22. In the same field of art (status updating), Zeh discloses a redundancy system which includes a first computational device and a second computational device (abstract). In one embodiment, Zeh further discloses the steps of implementing a delay lasting a random amount of time (par. 33 “random delay”) prior to performance of the comparison (par. 35). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Parker/Wehbe and Zeh by comprising: implementing a delay lasting a random amount of time prior to performance of the first comparison. The motivation is to improve the security of the system (par. 38).
As to claim 23, Parker/Wehbe discloses the method of claim 21, but does not disclose the limitations in claim 23. In the same field of art (status updating), Zeh discloses a redundancy system which includes a first computational device and a second computational device (abstract). In one embodiment, Zeh further discloses the steps of implementing a delay lasting a random amount of time (par. 33 “random delay”) prior to performance of the comparison (par. 35). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Parker/Wehbe and Zeh by comprising: implementing a delay lasting a random amount of time prior to performance of the second comparison. The motivation is to improve the security of the system (par. 38).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 41-42 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (US 20070198856, Lee).
As to claim 41, Lee discloses a system (fig. 3), comprising:
a microcontroller unit (CPU 104, controller 122) coupled to a bus (bus between ROM and SDRAM, bus 120);
a memory (ROM 106, SDRAM 102) coupled to the microcontroller unit via the bus (fig. 3);
a computer resource (fig. 8 secure card 350) coupled to the microcontroller unit via one or more connections (USB bus 128) that are separate from the bus; and
a hardware comparator circuit (par. 35, comparator 312) coupled to the memory via the bus (par. 11) and coupled to the computer resource via the one or more connections (fig. 3, 8).
As to claim 42, Lee discloses the system of claim 41, wherein the hardware comparator circuit is configured to perform a comparison of a first digital signature and a second digital signature, and selectively enable and disable access to the computer resource based on the comparison (par. 56).
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hiji (US 20020169900).
As to claim 43, Lee discloses the system of claim 41, but does not disclose the limitations in claim 43. In the same field of art (status updating), Hiji discloses an access controller capable of direct-memory-access-transferring data by using a ring buffer as an access object without increasing a circuit size or lowering a transfer capacity for direct memory access (par. 12). In one embodiment, Hiji further discloses a hardware comparator circuit (fig. 1) comprising: a set of registers having inputs coupled to the bus (registers 10-15); a digital comparator (comparator 22, 24) having a first input (from register 10), a second input (from register 15), and an output (to MCTL 21), the first input and the second input coupled to the set of registers (fig. 1); and circuitry (MCTL 21) having an input (from comp 22), a first output (to BUF 15), and a second output (to CCTR 18, 19), the input of the circuitry coupled to the output of the digital comparator (see fig. 1), the first output and the second output of the circuitry coupled to a microcontroller unit (selector 26).. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee and Hiji by comprising: a set of registers having inputs coupled to the bus; a digital comparator having a first input, a second input, and an output, the first input and the second input coupled to the set of registers; and circuitry having an input, a first output, and a second output, the input of the circuitry coupled to the output of the digital comparator, the first output and the second output of the circuitry coupled to the microcontroller unit. The motivation is to improve the efficiency of the system (par. 12).
Allowable Subject Matter
Claims 44-46 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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