DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 and 3-5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are:
The clock of the communication circuit. (According to ¶83 of the Applicant’s Specification in PG Pub US 2025/007170)
A processor or integrated circuit (such as the Wi-Fi IC as noted in ¶76-¶78 of PG Pub US 2025/0071709) that is capable of performing the generation of the interrupt signal (or data signal) as required by claims 3-4 and also capable of performing the execution of instructions to identify clock information of the communication circuit as required by claim 5.
The Examiner Notes:
The claims 1 and 3-5 are directed to a communication circuit while requiring the communication circuit to comprise “a first interface and a second interface”; wherein the processor of the electronic device is coupled to with the communication circuit via the first information or via the second interface. The claims additionally require the “sending, to the communication circuit via the first interface, a request for clock information of the communication circuit; receive, from the communication circuit via the first interface, the clock information of the communication circuit; receive, from the communication circuit via the second interface, an interrupt signal and first time information corresponding to the interrupt signal being generated;” The Examiner acknowledges that claim limitation directed to the processor being communicatively coupled with the communication circuit via the first information or via the second interface appears to be missing essential elements because the communication circuit is being described by the claims as both a destination element to which the processor is communicatively coupled while concurrently being described as the means (via the first interface) through when the processor will be communicatively coupled to itself (the communication circuit). Since the claimed invention is directed to requesting and/or receiving the clock information of the communication circuit, it appears that the clock of the communication circuit is the missing essential element. According to ¶83 of the Applicant’s Specification in PG Pub US 2025/0071709, “[0083]… the communication circuit 320 may identify the clock of the communication circuit 320 in response to receiving the clock information request from the processor 310.”
Secondly, absent the essential element of “a clock of the communication circuit”, the communication circuit has no way of being a medium through which the processor’s request may be delivered to a means (the clock of the communication circuit) for generating/reading clock information from said means (the clock of the communication circuit) and then sending the clock information to the processor for generation of clock information of the processor based on clock information of the communication circuit.
Therefore, the Examiner’s finds that the “the clock of the communication circuit” is an omitted essential limitation based on the rationale indicated above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 7, 8, 11, 12, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. US 2024/0172150 (hereinafter Zhang), in view of John et al. US 2021/0104211 (hereinafter John).
Regarding claim 1, Zhang teaches wherein an electronic device,
([Zhang, Fig. 1, Wireless device 110)
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comprising:
a communication circuit comprising a first interface and a second interface;
([Zhang, Fig. 2, ¶36 and ¶43-¶44] Wireless communication unit 116 ¶33 and bus system ¶43-¶44 which has connections to other parts of the wireless device 110 wherein the other connections are interpreted as at least two interfaces since there are multiple disclosed connections in the bus system and I/O ports including a Universal Serial Bus (USB).)
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a memory storing instructions; and
([Zhang, Fig. 2, Memory 208, ¶44,] Memory 208 stores instructions.)
a processor communicatively coupled with the communication circuit via the first interface or via the second interface, wherein the processor is configured to execute the instructions to:
[Zhang, Fig. 2, ¶36]
send, to the communication circuit via the first interface, a request for clock information of the communication circuit;
([Zhang, Fig. 4 and 7, ¶50 and ¶53-¶54] Method 400 is implemented by processor 114 of wireless device 110 which according to ¶54 of Zhang, sends a request for time information (interpreted as clock information) that is of bus system and wireless connection unit that is further connected to the source 130.)
receive, from the communication circuit via the first interface, the clock information of the communication circuit;
([Zhang, Fig. 7, Step 708, ¶82] Processor of wireless device 1110 receives the time information requested in Step 404 as indicated in the similarly corresponding request and reception of time information in steps 706-706. The Examiner points out that the processor sends this request 404/706 to the wireless connection unit 116/bus system for transport of the request and likewise in the reverse operation the processor receives the response of the requested time information via the wireless communication unit 706. Thus, the time information being carried via/from the wireless communication unit 116/bus system is able to be considered clock information of the communication circuitry.)
generate clock information of the processor based on the clock information of the communication circuit and the first time information.
([Zhang, ¶84] Correct its internal clock using the time information of the wireless communication unit 116/bus system (interpreted as the claimed clock information of communication circuit as discussed above) in step 708 of Zhang Fig. 7 and First clock time 702 of Fig. 7 (interpreted as the claimed first time information).)
Zhang teaches wherein the processor receives from the bus/interface with the source 120 [See Zhang, Figs 1-2 and 4, ¶50] but, Zhang does not teach the claim limitation of receive, from the communication circuit via the second interface, an interrupt signal and first time information corresponding to the interrupt signal being generated.
However, John teaches receive, from the communication circuit via the second interface, an interrupt signal and first time information corresponding to the interrupt signal being generated.
([John, Fig. 7, ¶117 and ¶155] The device HMD 112 receives from the wireless transceiver circuit (interpreted as the claimed communication circuit) via the GIPO interface, an interrupt signal 706 and first time information 710.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Zhang, indicating a device for synchronizing its processor based on the clock information of the communication circuit using a request and response exchange to obtain the clock information using a first interface, with the teachings of John, indicating that the a device may receive an interrupt and clock information from the communication circuit using a second interface. The resulting benefit would have been the ability to utilize a secondary path that will reduce the amount of time and overhead required to synchronize the clock of the device based on the device’s own communication circuit for more efficient and robust clock synchronization.
Regarding claim 2 and claim 12, Zhang, in view of John teaches the electronic device of claim 1 and method of claim 11 respectively, wherein the first interface comprises a universal serial bus (USB) interface [Zhang, ¶43-¶44], and wherein the second interface comprises a general purpose input output (GPIO) interface [John, ¶116].
Regarding claim 7 and claim 17, Zhang, in view of John teaches the electronic device of claim 1 and method of claim 11 respectively, wherein the processor is further configured to execute the instructions to:
transmit, to an external electronic device, a synchronization signal;
([Zhang, Fig. 7] transmit, to an external electronic device 730, a synchronization signal at step 706)
receive, from the external electronic device, an acknowledgement (ACK) signal based on the synchronization signal; and
([Zhang, Fig. 7] receive, from the external electronic device, an acknowledgement (ACK) signal, depicted as a response signal to the original transmission 706, based on the synchronization signal at step 708)
generate the clock information of the processor, based on transmission time information corresponding to the synchronization signal being transmitted and reception time information corresponding to the ACK signal being received [Zhang, ¶51].
Regarding claim 8 and claim 18, Zhang teaches the electronic device of claim 1 and the method of claim 11 respectively, wherein the processor is further configured to execute the instructions to:
receive, from an external electronic device, a synchronization signal comprising second time information corresponding to the synchronization signal being transmitted; and
([Zhang, Fig. 7], receive, from an external electronic device 730, a synchronization signal comprising second time information corresponding to the synchronization signal being transmitted at step 708.)
generate the clock information of the processor, based on the second time information and reception time information corresponding to the synchronization signal being received [Zhang, ¶51].
Claim(s) 3, 5, 6, 13, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of John as applied to claims 1 and 11 above, and further in view of Boone US 2017/0324888 (hereinafter Boone).
Regarding claim 3 and claim 13, Zhang, in view of John teaches the electronic device of claim 1 and the method of claim 11 respectively, wherein the communication circuit is configured to generate the interrupt signal [Zhang, Fig. 7, Step 702];
But it does not teach that the interruption is generated based on receiving a request.
However, Boone teaches wherein the communication circuit is configured to generate the interrupt signal based on receiving, from the processor, the request for the clock information of the communication circuit [Boone, Fig. 3, ¶11 and ¶20 (time query request and interrupt)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Zhang, in view of John, indicating a device and method for receiving an interrupt from a communication circuit, with the teachings of Boone, indicating that the interrupt may be generated by the communication circuit based on receiving, from the processor, the request for clock information (time query request) of the communication circuit. The resulting benefit of the combination would have been the ability to reduce the unexpected or untimely reception of interrupt by a processor unless authorized which also helps to reduce unwanted utilization or interface resources.
Regarding claim 5 and claim 15, the combination of Zhang, in view of John teaches the electronic device of claim 1 and the method of claim 11 respectively (see the rejection of claims 1 and 11 above),
But it does not teach wherein the communication circuit is further configured to execute the instructions to identify the clock information of the communication circuit based on a first synchronization signal received via the communication circuit.
However, Boone teaches wherein the communication circuit is further configured to execute the instructions to identify the clock information of the communication circuit based on a first synchronization signal received via the communication circuit. ([Boone, Fig. 3, Steps 302-304, ¶10] The station radio 112 is able to identify the time stamp (claimed clock information).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Zhang, in view of John, indicating a device is configured to identify clock information, with the teachings of Boone, indicating that the station radio is able to identify the time stamp (clock information). The resulting benefit of the combination would have been the ability to allow for the radio communication circuitry to maintain a local clock which may be synchronized to provide improved synchronization between the communication circuit and the network.
Regarding claim 6 and claim 16, the combination of Zhang, in view of John and Boone teaches the electronic device of claim 5 and the method of claim 15 respectively, wherein the first synchronization signal comprises information about a network to which the electronic device is coupled.
([Boone, Fig. 3, ¶10] Beason includes network (AP) timing information to which the station is coupled.)
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of John as applied to claims 1 and 11 above, and further in view of Bjorkengren US 2017/0094618 (hereinafter Bjrok).
Regarding claim 4 and claim 14, the combination of Zhang, in view of John teaches the electronic device of claim 1 and the method of claim 11 respectively, wherein the communication circuit is configured to generate the interrupt signal [John, Fig. 7, 702].
But it does not teach the interrupt signal comprising the first time information
However, Bjork teaches that the interrupt signal comprises the first time information [Bjork, ¶48].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Zhang, in view of John, indicating a device and method for receiving an interrupt from a communication circuit, with the teachings of Bjork, indicating that the interrupt signal comprises the first time information. The resulting benefit of the combination would have been the ability to reduce the total number of transmissions at the expense of a longer single transmission per interrupt resulting in less traffic being transmitted over the interface and less congestion.
Claim(s) 9, 10, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of John as applied to claims 1 and 11 above, and further in view of Bradley US 2019/0034985 (hereinafter Bradley).
Regarding claim 9 and claim 19, the combination of Zhang, in view of John teaches the electronic device of claim 1 and method of claim 11 respectively, wherein the processor performs clock corrections based on the differences between clock information [Zhang, ¶15, ¶51, ¶73 and ¶77-¶79] and wherein the plurality of offset values are identified based on a difference between the clock information of the communication circuit and the clock information of the processor [John, Figs. 5A and 7, 708-712 (offset is the computed difference between the internal clock of the HMD/processor 112 and the clock of the transceiver/communication circuit 142A) ¶42].
But it does not teach wherein the processor is further configured to execute the instructions to determine whether to correct the clock information of the processor based on a plurality of offset values identified for a predetermined time.
However, Bradley teaches wherein the processor is further configured to execute the instructions to determine whether to correct the clock information of the processor based on a plurality of offset values identified for a predetermined time, and wherein the plurality of offset values are identified.
([Bradley, ¶96 and also see ¶84-¶87] Bradley teaches instructions to determine whether to correct the clock information of the processor (further adjust the clock) based on a plurality of offset values (moving average of clock offsets) identified for a predetermined time (predicted clock offset), and wherein the plurality of offset values (clock offsets) are identified.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Zhang, in view of John, indicating a device is configured to identify clock information and update the current clock, with the teachings of Bradly, indicating that the determination to correct the clock information is based on a plurality of offset values identified for a predetermined time. The resulting benefit of the combination would have been the ability to enhance synchronization of the clock by allowing the clock to remain synchronized between update intervals [Bradley, ¶96].
Regarding claim 10 and claim 20, the combination of Zhang, in view of John teaches the electronic device of claim 9 and the method of claim 19 respectively, wherein the processor is further configured to execute the instructions to correct the clock information of the processor based on identifying that the plurality of offset values continuously increase for the predetermined time or identifying that the plurality of offset values continuously decrease for the predetermined time. ([Bradley, ¶96 and ¶85] The slope of the clock skew is used to correct the clock information, wherein the slope of the clock skew reflects offset values continuously increasing (positive slope, wherein a positive slope is a reflective of continuous increase) or decreasing (negative slope) for a predetermined time (the time axis direction of the slope, wherein a negative slope is a reflective of continuous decrease).)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONNIE V SWEET whose telephone number is (571)270-3622. The examiner can normally be reached Monday-Friday.
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/LONNIE V SWEET/Primary Examiner, Art Unit 2467
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