CTNF 18/882,227 CTNF 83072 Detailed Action The instant application having Application No. 18/882,227 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 9/11/24. Claims 1-20 are pending. NOTICE OF PRE-AIA OR AIA STATUS 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. INFORMATION CONCERNING DRAWINGS Drawings The applicant's drawings submitted 9/11/24 are acceptable for examination purposes. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tokutomi et al. (U.S. Patent Application Publication No. 2019/0087264), herein referred to as Tokutomi et al . Referring to claim 1, Tokutomi et al. disclose as claimed, a memory system comprising: a non-volatile memory that includes a plurality of memory cells each configured to store data according to a threshold voltage ( see fig. 1 and para. 70-73, where memory is stored using a threshold voltage ); and a memory controller configured to: set a first read voltage based on a first shift value; acquire hard bit data from the plurality of memory cells by a first read operation using the first read voltage ( see para. 94-99, where the memory controller reads out hard bit data based on a read voltage VCGR, or a default voltage and see para. 98, where those values may be shifted by Vth tracking to read voltages such as VA, VB, VC, etc. ); set a second read voltage based on a second shift value; acquire soft bit data from the plurality of memory cells by a second read operation using the second read voltage ( see para. 110, where soft bit voltages are read by using a read voltage based on a shift value ); execute first error correction on data read from the plurality of memory cells by using the hard bit data and the soft bit data ( see para. 86, where the ECC circuit uses both hard bit data and soft bit data ); in a case where the first error correction has failed, calculate a first log likelihood ratio (LLR) by using at least a result of the first error correction that has failed ( see para. 105 and fig. 26, showing where the fail signal and error corrected LLR values are sent to a decoding circuit and in a case the error correction fails, a new corrected LLR values are determined ); and correct at least one of the first shift value and the second shift value based on the first LLR ( see para. 117-120, where the shift values may be corrected based on a first LLR table. Also see fig. 11 ). Claim 16 recites similar limitations to claim 1 and would be rejected using the same rationale. As to claim 2, Tokutomi et al. also disclose the memory system according to claim 1, wherein the memory controller is further configured to: manage a plurality of sections each of which is obtained by dividing a range of the threshold voltage ( see fig. 3, showing a plurality of sections obtained by dividing a range of the threshold voltage ); in the case where the first error correction has failed, calculate the first LLR for each of the plurality of sections ( see fig. 6, showing an LLR table for the plurality of sections, and see fig. 10 and 11 and para. 105 and 117-119, where a new LLR table is calculated after error correction has failed ); and correct the first shift value such that the first read voltage is set between a first section and a second section ( see fig. 3, showing a read voltage VA-VG set between different sections ), the first section is one of the plurality of sections and the first LLR having a negative value was calculated for the first section, and the second section is another one of the plurality of sections adjacent to the first section and the first LLR having a positive value was calculated for the second section ( see fig. 6, showing a first section having a negative value -1, and a section adjacent section having a positive value +1 ). As to claim 3, Tokutomi et al. also disclose the memory system according to claim 2, wherein the memory controller is further configured to: determine a third read voltage for use in the second read operation, in response to the correction of the first shift value; and cause the non-volatile memory to execute a third read operation using the third read voltage ( see fig. 7, step S15, where a different shift value may be generated for each iteration of the flowchart of fig. 7, and would execute a third read operation using a third read voltage if the previous read operation failed. Also see para. 140, where an LLR table may be modified multiple times ). As to claim 4, Tokutomi et al. also disclose the memory system according to claim 3, wherein the memory controller is further configured to, in a case where the first read voltage based on the first shift value that is corrected is lower than the first read voltage based on the first shift value before the correction ( see fig. 10-11, where corrected shift values may be used so the read voltage may be higher or lower than the shift values before the correction ), set the third read voltage to be lower than the first read voltage based on the first shift value that is corrected ( see para. 107-110, where the soft bit voltages are based on the hard bit voltages that are corrected and would therefore be lower as well ). As to claim 5, Tokutomi et al. also disclose the memory system according to claim 2, wherein the memory controller is further configured to: replace the second read voltage for use in the second read operation with a third read voltage different from the second read voltage, in response to the correction of the first shift value; and cause the non-volatile memory to execute a third read operation using the third read voltage ( see fig. 10-11, and fig. 22, where an initial LLR table with first values may be replaced by a second with higher values or a third with lower values, and third read operations would take place using the third read voltages ). As to claim 6, Tokutomi et al. also disclose the memory system according to claim 5, wherein the memory controller is further configured to replace the second read voltage that is higher than the first read voltage, with the third read voltage that is lower than the first read voltage ( see fig. 10-11, and fig. 22, where an initial LLR table with first values may be replaced by a second with higher values or a third with lower values. As fig. 22, step 15 illustrates, different LLR tables may be utilized until decoding is successful ). As to claim 7, Tokutomi et al. also disclose the memory system according to claim 2, wherein the memory controller is further configured to: execute the second read operation using at least the second read voltage and a third read voltage different from the second read voltage ( see para. 107-110, where during a soft bit read, multiple voltages may be used to read the data ); replace the second read voltage with a fourth read voltage different from the second read voltage, in response to the correction of the first shift value; and cause the non-volatile memory to execute a fourth read operation using at least the third read voltage and the fourth read voltage ( see fig. 7, showing that soft bit reading may take place again in step S13 after changing the LLR table to use different voltages ). As to claim 8, Tokutomi et al. also disclose the memory system according to claim 7, wherein the memory controller is further configured to replace the second read voltage that is higher than the first read voltage, with the fourth read voltage that is lower than the first read voltage ( see fig. 10-11, and fig. 22, where an initial LLR table with first values may be replaced by a second with higher values or a third with lower values. As fig. 22, step 15 illustrates, different LLR tables may be utilized until decoding is successful ). As to claim 9, Tokutomi et al. also disclose the memory system according to claim 2, wherein the memory controller is further configured to: for each of the plurality of sections, count the number of memory cells whose threshold voltage belongs to the each of the plurality of sections, using a result of the first error correction; and calculate the first LLR based on a result of the counting ( see fig. 11, where each of an LLR value in 20 sections is shifted. Therefore, the number of sections is used in calculating a next LLR, as each of the 20 sections is shifted ). As to claim 10, Tokutomi et al. also disclose the memory system according to claim 1, wherein the second read voltage is obtained by adding the second shift value to the first read voltage ( see para. 107-110, where soft bit data may be read by the first read voltage shifted by a shift value ). Claim 18 recites similar limitations to claim 10 and would be rejected using the same rationale. As to claim 11, Tokutomi et al. also disclose the memory system according to claim 1, wherein the memory controller is further configured to: manage a plurality of sections each of which is obtained by dividing a range of the threshold voltage ( see fig. 3, showing a plurality of sections obtained by dividing a range of the threshold voltage ); in the case where the first error correction has failed, calculate the first LLR for each of the plurality of sections ( see fig. 6, showing an LLR table for the plurality of sections, and see fig. 10 and 11 and para. 105 and 117-119, where a new LLR table is calculated after error correction has failed ); search the plurality of sections for a first section and a second section that is adjacent to the first section, an absolute value of a difference between the first LLR in the first section and the first LLR in the second section being smaller than a first determination value ( see para. 150, where the differences between two adjacent sections is calculated. See, fig. 11, showing read voltages in section 18 and 19 with a difference in the absolute value of zero, which is smaller than a first determination value); and in a case where a smaller value of an absolute value of the first LLR in the first section and an absolute value of the first LLR in the second section is smaller than a second determination value ( see fig. 11, where a smaller value would be -9, which would be smaller than a second determination value ); correct the second shift value used to set the second read voltage corresponding to the first section, and correct a third shift value used to set a third read voltage corresponding to the second section ( see fig. 11, where when the table is shifted to the right, the values are corrected to -8 and -9 ), such that a range of the threshold voltage corresponding to the first section and a range of the threshold voltage corresponding to the second section are widened ( see fig. 11 for example, where the difference between 18 and 19 was 0 and then it becomes 1 when it is shifted to the right by 1 ). Claim 19 recites similar limitations to claim 11 and would be rejected using the same rationale. 12. As to claim 12, Tokutomi et al. also disclose the memory system according to claim 11, wherein the memory controller is further configured to, in a case where the smaller value of the absolute values of the first LLRs in the first and second sections is equal to or larger than the second determination value, correct the second shift value and the third shift value such that the range of the threshold voltage corresponding to each of the first and second sections is narrowed ( see fig. 11, showing section 0 and 1 for example, where the smaller value is -9, which could be larger than a second determination value. See where the LLR table shifts to the left by 1, and the range of the first and second sections is narrowed ). As to claim 13, Tokutomi et al. also disclose the memory system according to claim 1, wherein the memory controller is further configured to: in a case where the first error correction has succeeded ( see para. 103, where it is determined whether error correction has succeeded ), calculate a second LLR by using at least a result of the first error correction that has succeeded ( see para. 103-104, where if error correction passes, the controller receives back the set of LLR values that has been error corrected ); and correct at least one of the first shift value and the second shift value based on the second LLR ( see fig. 10, showing that the LLR values contain shift values, therefore the corrected or second LLR would have corrected shift values ). Claim 20 recites similar limitations to claim 13 and would be rejected using the same rationale. As to claim 14, Tokutomi et al. also disclose the memory system according to claim 1, wherein the memory controller is further configured to, in a case where second error correction different from the first error correction using the hard bit data has failed, execute the second read operation and execute the first error correction ( see fig. 7, steps S13-S15, where either or both of the first and second error correction can fail, therefore the second read operation and the first error correction would both be executed) . As to claim 15, Tokutomi et al. also disclose the memory system according to claim 1, wherein the memory controller is further configured to: execute the first error correction using the hard bit data, the soft bit data, and a preset third LLR; and update the third LLR based on the first LLR ( see para. 1899, where the LLR table may be selected from three or more preset LLR tables. The tables would then be updated or changed as needed based on shifting ). As to claim 17, Tokutomi et al. also disclose the method according to claim 16, further comprising: managing a plurality of sections each of which is obtained by dividing a range of the threshold voltage ( see fig. 3, showing a plurality of sections obtained by dividing a range of the threshold voltage ); in response to determining that the first error correction has failed, calculating the first LLR for each of the plurality of sections ( see fig. 6, showing an LLR table for the plurality of sections, and see fig. 10 and 11 and para. 105 and 117-119, where a new LLR table is calculated after error correction has failed ); determining a first section that is one of the plurality of sections and the first LLR having a negative value was calculated for the first section; determining a second section that is another one of the plurality of sections adjacent to the first section and the first LLR having a positive value was calculated for the second section ( see fig. 6, showing a first section having a negative value -1, and a section adjacent section having a positive value +1 ); and correcting the first shift value such that the first read voltage is set between the first section and the second section ( see fig. 3, showing a read voltage VA-VG set between different sections ). CLOSING COMMENTS Conclusion a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i) : a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a first action on the merits and are the subject of a first action non-final. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.O/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 18/882,227 Page 2 Art Unit: 2132 Application/Control Number: 18/882,227 Page 3 Art Unit: 2132
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