Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-5 is objected to because of the following informalities:
Regarding claim 1, “a first wire” and “a second wire” should be plural wires since they are connected to plural terminals.
Regarding claim 2, “the second extension portion is located at at a position” delete one at.
Regarding claim 5, “a plurlaity” should be “a plurality”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiraishi et al (PG Pub 2006/0113664 A1).
Regarding claim 1, Shiraishi teaches (figs. 5 and 6) a semiconductor device comprising: a package having a first side, a second side, a third side and a fourth side in a plan view; a plurality of terminals (GND or near 7a3, respectively on bottom and top of fig. 5) arranged along each of the first side and the second side of the package opposing to each other; a first island (7a2) having four sides in a plan view, one of the four sides of the first island opposing the first side of the package; a second island (7a3), separated from the first island, having four sides in a plan view, one of the four sides of the second island opposing the second side of the package; at least one first semiconductor chip (5b, paragraph [0100]) mounted on the first island; at least one second semiconductor chip (5c) mounted on the second island; an insulating element (6) provided on one or both of the first semiconductor chip and the second semiconductor chip; a first wire (W) electrically connecting the first semiconductor chip to the plurality of terminals arranged on the first side of the package; a second wire (W) electrically connecting the second semiconductor chip to the plurality of terminals arranged on the second side of the package; and a third wire (W) electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the first island has: a first extension portion (Lx on the left of fig. 5) extending to be exposed from one of the third side and the fourth side of the package; and a first terminal connector )Lx on the bottom of fig. 5) connected to a terminal, positioned farthest from the first extension portion, of the plurality of terminals arranged on the first side, the first island is supported (figs. 5 and 6) by the package through the first extension portion and the first terminal connector, the second island has: a second extension portion (on the right of fig. 5 near 7a3) extending to be exposed from the other of the third side and the fourth side; and a second terminal connector connected to a terminal (top of fig. 5, connected to 7a3), positioned farthest from the second extension portion, of the plurality of terminals arranged on the second side, and the second island is supported (figs. 5 and 6) by the package through the second extension portion and the second terminal connector.
Regarding claim 2, Shiraishi teaches (see fig. 5 attached) the semiconductor device according to claim 1, wherein the first extension portion is located at a position farther from the plurality of terminals arranged on the first side than a center position of the one of the third side and the fourth side is, and the second extension portion is located at a position farther from the plurality of terminals arranged on the second side than a center position of the other of the third side and the fourth side is. Note that the claims do not require that “a package” to be the entirety of the “semiconductor device” claimed in the preamble. Thus, the package’s side is only what’s indicated below in fig. 5.
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Regarding claim 3, Shiraishi teaches (see fig. 5 attached below) the semiconductor device according to claim 1, wherein the first extension portion is located at a position between the plurality of terminals arranged on the first side and a center position of the one of the third side and the fourth side, and the second extension portion is located at a position between the plurality of terminals arranged on the second side and a center position of the other of the third side and the fourth side.
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Regarding claim 4, Shiraishi teaches the semiconductor device according to claim 1, wherein a creepage distance between a first exposed portion exposed to outside of the package and electrically connected to the first island and a second exposed portion exposed to outside of the package and electrically connected to the second island is equal to or greater than a predetermined specified distance (the distance between lead near Lx on the left and the lead on the right and connected to 7a2) for insulation.
Regarding claim 5, Shiraishi teaches the semiconductor device according to claim 1, wherein the first extension portion is one of a plurality of first extension portions, and the second extension portion is one of a plurality of second extension portions (fig. 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
