Prosecution Insights
Last updated: August 17, 2026
Application No. 18/882,368

STORAGE SYSTEM

Non-Final OA §103§112
Filed
Sep 11, 2024
Priority
Dec 28, 2023 — JP 2023-222256
Examiner
HAILE, AWET A
Art Unit
Tech Center
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
548 granted / 690 resolved
+19.4% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
27 currently pending
Career history
714
Total Applications
across all art units

Statute-Specific Performance

§101
6.7%
-33.3% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 690 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Regarding claim 6, the limitation “wherein the network interface device is able to make an implementation function programmed” is indefinite. It is unclear what structural limitations or functional steps are required to satisfy the limitation “make an implementation function programmed”. A person having ordinary skill in the art would not understand whether this limitation requires the network interface device to possess specific hardware (such as a programmable logic circuit or FPGA), or if it merely recites a generic software execution capability. Regarding claim 9, the occurrence of “the total buffer capacity” in line 2 has no antecedent basis. Claim Rejections – 35 USC§ 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama et al(US 2009/0248830 A1) in view of Qiu et al(US 2018/0314450 A1). Regarding claims 1 and 7, Kodama ‘830 teaches, a storage system (Figs. 1-2) comprising: a controller ([0038], [0041], [0046] and Figs. 1-2, storage server 106 comprising server blade 108 and storage device 110. The storage device controller 132 interfaces between server 108 and storage device 110); a network interface device connected to the controller ([0046], [0047] and Fig. 2., ISCSI hardware solution (acting as the network device interface device) that is interconnected with the storage device controller via bus), wherein the network interface device receives an access request from a host([0041], [0075], [0084] and Figs. 1, 8, the iSCS hardware solution receiving storage network data( iSCSI command PDUs) from an initiator (application server/host) over the network), the network interface device converts the access request into an access request interpretable by the controller ([0041], [0044], [0069], iSNP and CPU that decode and decapsulate incoming iSCS instruction to resolve the SCSI commands), in processing in response to a data writing request from the host, the network interface device transmits a message for an instructing to start transmission of writing target data to the host ([0088]-[0089], [0098] and Fig. 8, when responding to a WRITE SCSI command , the target transmits a Ready to transfer (R2T) PDU to the initiator to indicate which blocks of data it is ready to receive), and then allocates a buffer that temporarily stores the writing target data ([0094], [0101]-[0105] and Figs. 8, 9B-9D, determines/allocates the buffer destination after R2T is received), stores the writing target data received from the host in the buffer ([0072], [0097], [0106] and Figs. 9A, 9D, receiving SCSI data-out PDUs from the initiator and temporarily assembling/placing this data into specific locations within the buffer memory using the pointers), and transfers the writing target data stored in the buffer to the controller([0072] and Fig. 6, the block-oriented storage I/O devices have direct access to retrieve the assembled data in the buffer memory through the storage controller interfaces). Kodama ‘830 does not explicitly teach, issues the access request to the controller. Qiu ‘450 teaches, issues the access request to the controller ([0160], [0161] and Fig. 3 step 208, the network adapted 401 modifies the received write command by changing the source address to the address of the allocated storage space within the network adapter memory and updating the data length, it then sends this modified write command to the controller of the destination hard disk). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Kodama ‘830, since such modification would enable resolve a prior-art problem that a data read/write command fails to be executed because a large amount of data needs to be transmitted according to the data read/write command and a storage space of a cache unit in a storage device is insufficient, as suggested by Qiu ‘450([0007]). Regarding claim 6, the combination of Kodama ‘830 and Qiu ‘450 teaches all of the claim limitations, Kodama ‘830 further teaches, wherein the network interface device is able to make an implementation function programmed ([0043], [0044], [0049] and Fig. 4the network interface device(e.g. the iSCSI hardware solution 120 or server blade 108) includes CPU 124 and dedicated processors (such as RISC processors) to process instructions). Claims 2-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kodama ‘830 and Qiu ‘450 as applied to claims above, and further in view of Santry et al(US 7152069 B1). Regarding claims 2 and 8, the combination of Kodama ‘830 and Qiu ‘450 teaches all of the claim limitations except, wherein the network interface device allocates the buffer that temporarily stores the writing target data, when the writing target data has been received from the host. Santry ‘069 teaches, wherein the network interface device allocates the buffer that temporarily stores the writing target data, when the writing target data has been received from the host (col 11 lines 40-61 and Figs. 6, 9, when data packets are receive, determines whether a new memory buffers (mbufs) must be additionally allocated. When a new mbuf is needed, the operating system allocates another mbuf at step 906 and keeps iteratively adding mbufs in accordance with a conventional memory allocation policy until either the received data is completely stored in chains of mbufs or the system runs out of available memory). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Kodama ‘830, since such modification would enable to minimize the amount of time and system resources needed to write large data files to one or more storage disks in a filer without affecting the resolution of other file access requests, such as file "READ" requests, as suggested by Santry ‘069(col 3 lines 1-23) . Regarding claims 3 and 8, the combination of Kodama ‘830 and Qiu ‘450 teaches all of the claim limitations, Kodama ‘830 further teaches, wherein the network interface device allocates the buffer that temporarily stores the writing target data ([0094], [0101]-[0105] and Figs. 8, 9B-9D, determines/allocates the buffer destination after R2T is received). The combination of Kodama ‘830 and Qiu ‘450 does not explicitly teach, when the writing target data has been received from the host. Santry ‘069 teaches, when a response to the message has been received from the host (col 11 lines 40-61 and Figs. 6, 9, when data packets are received, determines whether a new memory buffer (mbufs)must be additionally allocated. When a new mbuf is needed, the operating system allocates another mbuf at step 906 and keeps iteratively adding mbufs in accordance with a conventional memory allocation policy until either the received data is completely stored in chains of mbufs or the system runs out of available memory). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Kodama ‘830, since such modification would enable to minimize the amount of time and system resources needed to write large data files to one or more storage disks in a filer without affecting the resolution of other file access requests, such as file "READ" requests, as suggested by Santry ‘069(col 3 lines 1-23). Regarding claims 4 and 9, the combination of Kodama ‘830 and Qiu ‘450 teaches all of the claim limitations, Qiu ‘450 further teaches, wherein the network interface device includes a processor that converts the access request into the access request interpretable by the controller and issues the access request to the controller([0160], [0161] and Fig. 3 step 208, the network adapted 401 modifies the received write command by changing the source address to the address of the allocated storage space within the network adapter memory and updating the data length, it then sends this modified write command to the controller of the destination hard disk). The combination of Kodama ‘830 and Qiu ‘450 does not explicitly teach, a cache of the processor, and a total buffer capacity allocated for temporarily storing writing target data from the host is limited to be stored in the cache. Santry ‘069 teaches, a cache of the processor, and a total buffer capacity allocated for temporarily storing writing target data from the host is limited to be stored in the cache (col 11 lines 40-61, col 12 lines 1-54 and Figs. 6, 9, when a new mbuf is needed, the operating system allocates another mbuf at step 906 and keeps iteratively adding mbufs in accordance with a conventional memory allocation policy until either the received data is completely stored in chains of mbufs or the system runs out of available memory). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Kodama ‘830, since such modification would enable to minimize the amount of time and system resources needed to write large data files to one or more storage disks in a filer without affecting the resolution of other file access requests, such as file "READ" requests, as suggested by Santry ‘069(col 3 lines 1-23) . Regarding claims 5 and 10, the combination of Kodama ‘830 and Qiu ‘450 teaches all of the claim limitations except, wherein the network interface device allocates a reserve memory area allocated in advance in a case where a total buffer capacity allocated for temporarily storing writing target data from the host exceeds a maximum capacity set in advance. Santry ‘069 teaches, wherein the network interface device allocates a reserve memory area allocated in advance in a case where a total buffer capacity allocated for temporarily storing writing target data from the host exceeds a maximum capacity set in advance(col 11 lines 40-61, col 12 lines 1-54 and Figs. 6, 9, keeps iteratively adding mbufs in accordance with a conventional memory allocation policy until either the received data is completely stored in chains of mbufs or the system runs out of available memory). Internet Communications Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, which can be found: http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. The written authorization can be submitted via one of the following methods only: (1) Central Fax which can be found in the Conclusion section of this Office action; (2) regular postal mail; or (3) EFS WEB. Written authorization submitted via other methods, such as direct fax to the examiner or email, will not be accepted. See MPEP § 502.03. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AWET A HAILE whose telephone number is (571)270-3114. The examiner can normally be reached Monday through Friday 8:30 AM - 4:30 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Thier can be reached at (571)272-2832. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AWET HAILE/Primary Examiner, Art Unit 2474
Read full office action

Prosecution Timeline

Sep 11, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+25.5%)
3y 0m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 690 resolved cases by this examiner. Grant probability derived from career allowance rate.

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