CTNF 18/882,560 CTNF 83072 Detailed Action The instant application having Application No. 18/882,560 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 9/11/24. Claims 1-20 are pending. NOTICE OF PRE-AIA OR AIA STATUS 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. INFORMATION CONCERNING DRAWINGS Drawings The applicant's drawings submitted 9/11/24 are acceptable for examination purposes. 07-30-03-h AIA CLAIM INTERPRETATION 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-2, 8 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gatto et al. (U.S. Patent Application Publication No. 2024/0070024), herein referred to as Gatto et al . Referring to claim 1, Gatto et al. disclose as claimed, an apparatus, comprising: a central processing unit (CPU) coupled to a system-on-a-chip (SOC) interconnect ( see para. 26, where the host device may include a system on a chip with a CPU ); a plurality of logic structures coupled to a memory; and a safety mechanism coupled to and inline with the memory, the plurality of logic structures and the CPU via the SOC interconnect, the safety mechanism comprising a meta cache and configured to detect errors in one or more of the plurality of logic structures and the memory ( see para. 28, where the LRAID logic couples to the cache or processor or memory controller and uses metadata returned with data to detect errors. Also see para. 62 ). As to claim 2, Gatto et al. also disclose the apparatus of claim 1, in which the safety mechanism further comprises: a short code generator coupled to the meta cache; a cache lookup component coupled to the meta cache; and a check component coupled to the meta cache ( see para. 81, where the reliability check circuitry may additionally or alternatively include a CRC, which hashes the data and compares it to a checksum to determine a representation of the data received from memory. The checksum may be determined from metadata retrieved from memory alongside the data ). Referring to claim 8, Gatto et al. disclose as claimed, a method, comprising: receiving, from an upstream component, a data transaction ( see para. 71, where a processor may request data from a cache ); receiving a cache hit or a cache miss based on executing the data transaction at a meta cache; and transmitting data from the data transaction downstream based on receiving the cache miss ( see para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory ). Referring to claim 15, Gatto et al. disclose as claimed, an apparatus, comprising: means for receiving, from an upstream component, a data transaction ( means for receiving may be a processor, as discussed in applicant’s specification para. 37. See Gatto et al., para. 71, where a processor may request data from a cache ); means for receiving a cache hit or a cache miss based on executing the data transaction at a meta cache; and means for transmitting data from the data transaction downstream based on receiving the cache miss ( means for transmitting may be a memory, as discussed in applicant’s specification, para. 37. means for receiving a cache hit/miss is may be a cache or cache lookup as disclosed in para. 71. See Gatto et al., para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory ) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4-7, 9-12 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gatto et al. in view of Quach et al. (U.S. Patent Application No. 2017/0123897), herein referred to as Quach et al . As to claim 4, Gatto et al. disclose the claimed invention except for the apparatus of claim 2, in which the short code generator is configured to generate a meta code based on a data payload of a data transaction and an address of the data transaction. However, Quach et al. disclose the short code generator is configured to generate a meta code based on a data payload of a data transaction and an address of the data transaction ( see para. 5, where ECC bits, which would be a meta code, are generated for the compressed data line and would be based on the data payload and be based on the address as it would be necessary to retrieve the data to generate the code. Para. 7 also discloses that the ECC data is associated with an address for the data line ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise the short code generator is configured to generate a meta code based on a data payload of a data transaction and an address of the data transaction, as taught by Quach et al., in order to correct errors and have greater reliability. In addition, Gatto et al., para. 81 disclose a CRC hashing data and comparing it to a checksum which would be meta codes. As to claim 5, Gatto et al. disclose the claimed invention except for the apparatus of claim 1, in which the memory includes a meta region physically separated from a data region by a gap. However, Quach et al. disclose in which the memory includes a meta region physically separated from a data region by a gap ( see fig. 2a, where the ECC portion is separate from the data region. Also see para. 39, where the ECC portion may be located on a separate memory device than the data portion and would therefore be physically separate ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise in which the memory includes a meta region physically separated from a data region by a gap, as taught by Quach et al., in order to efficiently organize data for easier retrieval as well as performance improvements. It is well known in the art to have partitioned and separate metadata and data regions. As to claim 6, Gatto et al. disclose the claimed invention except for the apparatus of claim 1, in which the meta cache is configured to receive and transmit a data payload based on receiving a cache hit indication. However, Quach et al. disclose in which the meta cache is configured to receive and transmit a data payload based on receiving a cache hit indication ( see Gatto et al., para. 81, where a hash of the data is determined and transmitted to compare to a checksum ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise in which the meta cache is configured to receive and transmit a data payload based on receiving a cache hit indication, as taught by Quach et al., in order to efficiently organize data for easier retrieval as well as performance improvements. It is well known in the art to have partitioned and separate metadata and data regions. As to claim 7, Gatto et al. also disclose the apparatus of claim 1, in which the plurality of logic structures comprises a memory controller and an encryption engine ( see fig. 1 and 6, showing a memory controller as well as an ECC and CRC component ). However, Quach et al. disclose in which the plurality of logic structures comprises a compression engine and a last-level cache ( see Quach et al., fig. 1, showing a memory controller, a compression engine, ecc check/generation and a last level cache. Also see para. 39, explaining that the cache may be a last level cache ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise in which the plurality of logic structures comprises a compression engine and a last-level cache, as taught by Quach et al., in order to save space with compressing data. Compressing data to save space is well known in the art and would be obvious to include with Gatto et al. As to claim 9, Gatto et al. also disclose the method of claim 8, in which the data transaction is a write transaction including a first data payload ( see para. 58, where the memory access may be a read or write operation ) and the upstream component is a system-on-a-chip (SOC) interconnect ( see para. 26, where the host device may include a system on a chip ), and the method further comprises: receiving a write miss in response to the write transaction failing at the meta cache ( see para. 71 discloses where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory ); Gatto et al. disclose the claimed invention except for in response to the write miss: generating a first short code based on the first data payload; caching the first short code in the meta cache; and transmitting the first data payload to a memory. However, Quach et al. disclose in response to the write miss: generating a first short code based on the first data payload; caching the first short code in the meta cache; and transmitting the first data payload to a memory ( see para. 5 and 58, where ECC bits, which would be a meta code, are generated for the compressed data line and would be based on the data payload. See fig. 2a, where the meta ECC portion would store the ECC bits. The data payload would be stored in the data portion of memory 130 ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise in response to the write miss: generating a first short code based on the first data payload; caching the first short code in the meta cache; and transmitting the first data payload to a memory, as taught by Quach et al., in order to efficiently organize data for easier retrieval as well as performance improvements. It is well known in the art to have partitioned and separate metadata and data regions. As to claim 10, Gatto et al. and Quach et al. also disclose the method of claim 9, further comprising storing the first data payload at a data region that is physically separated from a meta region by a gap in the memory ( see Quach et al., fig. 2a, where the ECC portion is separate from the data region. Also see para. 39, where the ECC portion may be located on a separate memory device than the data portion and would therefore be physically separate ). As to claim 11, Gatto et al. and Quach et al. also disclose the method of claim 9, further comprising: receiving a read transaction for the first data payload, from the SOC interconnect ( see Gatto et al., para. 58-62, where a memory read is sent and received from the SOC interconnect ); receiving a read miss based on failing to retrieve the first data payload from the meta cache ( see Gatto et al., para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory. See Quach et al., para. 7, where there may be an ECC cache miss, which would be a read miss on a meta cache ); and in response to the read miss: retrieving a second data payload from the memory ( see Gatto et al., para. 71, where in the event of a cache miss, cache 112 may request the required data from lower-level memory ); generating a second short code based on the second data payload ( see Gatto et al., para. 81, where a checksum is determined from metadata retrieved from memory ); comparing the first short code to the second short code; and generating an error indication based on the first short code not matching the second short code ( see Gatto et al., para. 81, where a hash of the data may be compared to a checksum retrieved from memory to determine if they match, and an error is generated if they don’t match ). As to claim 12, Gatto et al. and Quach et al. also disclose the method of claim 11, in which comparing the first short code to the second short code comprises: generating a meta request for the first short code; receiving a meta request miss based on failing to retrieve the first short code from the meta cache; and retrieving the first short code from the memory ( see Gatto et al., para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory. See Quach et al., para. 7, where there may be an ECC cache miss, which would be a read miss on a meta cache ). As to claim 16, Gatto et al. also disclose the apparatus of claim 15, in which the data transaction is a write transaction including a first data payload ( see para. 58, where the memory access may be a read or write operation ) and the upstream component is a system-on-a-chip (SOC) interconnect ( see para. 26, where the host device may include a system on a chip with a CPU ), and the apparatus further comprises: means for receiving a write miss in response to the write transaction failing at the meta cache ( means for receiving a write miss may be a cache lookup component or cache, as disclosed in applicant’s specification para. 71. Gatto et al., para. 71 discloses where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory ); Gatto et al. disclose the claimed invention except for in response to the write miss: means for generating a first short code based on the first data payload ( means for generating a short code may be a safety mechanism as disclosed in applicant’s specification para. 31. See Gatto et al., para. 81, where the reliability check circuitry may additionally or alternatively include a CRC, which hashes the data and compares it to a checksum to determine a representation of the data received from memory. The checksum may be determined from metadata retrieved from memory alongside the data, which would happen on a write miss, as the data would need to be retrieved from memory ); means for caching the first short code in the meta cache ( means for caching may be a cache as taught by applicant’s specification, para. 38. See Gatto et al., para. 80-81, where redundant information is in the metadata as well as the checksum being determined from metadata ); and means for transmitting the first data payload to a memory ( means for transmitting may be any memory block, as disclosed in applicant’s specification, para. 37. See Gatto et al., para. 60, where a memory write may take place to a memory and the memory response may be returned ). However, Quach et al. disclose in response to the write miss: means for generating a first short code based on the first data payload ( means for generating a short code may be a safety mechanism as disclosed in applicant’s specification para. 31. See para. 5 and 58, where ECC bits, which would be a meta code, are generated for the compressed data line and would be based on the data payload. See fig. 2a, where the meta ECC portion would store the ECC bits. The data payload would be stored in the data portion of memory 130 ); means for caching the first short code in the meta cache ( means for caching may be a cache as taught by applicant’s specification, para. 38. See para. 5 and 58, where ECC bits, which would be a meta code, are generated for the compressed data line and would be based on the data payload. See fig. 2a, where the meta ECC portion would store the ECC bits. The data payload would be stored in the data portion of memory 130 ); and means for transmitting the first data payload to a memory ( means for transmitting may be any memory block, as disclosed in applicant’s specification, para. 37. See para. 5 and 58, where ECC bits, which would be a meta code, are generated for the compressed data line and would be based on the data payload. See fig. 2a, where the meta ECC portion would store the ECC bits. The data payload would be stored in the data portion of memory 130. ). Gatto et al. and Quach et al. are analogous art because they are from the same field of endeavor of data reliability ( see Gatto et al., abstract and Quach et al., abstract regarding data reliability ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise in response to the write miss: means for generating a first short code based on the first data payload; means for caching the first short code in the meta cache; and means for transmitting the first data payload to a memory, as taught by Quach et al., in order to efficiently organize data for easier retrieval as well as performance improvements. It is well known in the art to have partitioned and separate metadata and data regions. As to claim 17, Gatto et al. and Quach et al. also disclose the apparatus of claim 16, further comprising means for storing the first data payload at a data region that is physically separated from a meta region by a gap in the memory ( means for storing may be a memory block as disclosed in applicant’s specification, para. 38. S ee Quach et al., fig. 2a, where the ECC portion is separate from the data region. Also see para. 39, where the ECC portion may be located on a separate memory device than the data portion and would therefore be physically separate ). As to claim 18, Gatto et al. and Quach et al. also disclose the apparatus of claim 16, further comprising: means for receiving a read transaction for the first data payload, from the SOC interconnect ( means for receiving may be a CPU or cache as disclosed in applicant’s specification, para. 37. See Gatto et al., para. 58-62, where a memory read is sent and received from the SOC interconnect ); means for receiving a read miss based on failing to retrieve the first data payload from the meta cache ( means for receiving a read miss may be a cache or safety mechanism as disclosed in applicant’s specification, para. 69. See Gatto et al., para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory. See Quach et al., para. 7, where there may be an ECC cache miss, which would be a read miss on a meta cache ); and in response to the read miss: means for retrieving a second data payload from the memory ( means for retrieving a data payload may be a memory block, as disclosed in applicant’s specification, para. 38. See Gatto et al., para. 71, where in the event of a cache miss, cache 112 may request the required data from lower-level memory ); means for generating a second short code based on the second data payload ( means for generating a short code may be a safety mechanism as disclosed in applicant’s specification para. 31. See Gatto et al., para. 81, where a checksum is determined from metadata retrieved from memory ); means for comparing the first short code to the second short code; and means for generating an error indication based on the first short code not matching the second short code ( means for comparing may be a cache lookup component, as disclosed in applicant’s specification, para. 38. Means for generating an error may be a cache lookup or metadata generator, as disclosed in applicant’s specification para. 37. See Gatto et al., para. 81, where a hash of the data may be compared to a checksum retrieved from memory to determine if they match, and an error is generated if they don’t match ). As to claim 19, Gatto et al. and Quach et al. also disclose the apparatus of claim 18, in which comparing the first short code to the second short code comprises: means for generating a meta request for the first short code ( means for generating a meta request may be a cache lookup or safety mechanism as disclosed in applicant’s specification, para. 37. See Gatto et al., para. 71, where if the data is present within the cache memory, then there is a cache hit and it is returned to the processor, and where in the event of a cache miss, cache 112 may request the required data from lower-level memory ); means for receiving a meta request miss based on failing to retrieve the first short code from the meta cache; and means for retrieving the first short code from the memory ( means for receiving a meta request miss may be a memory block, as disclosed in applicant’s specification, para. 38. Means for retrieving may be a memory block, as disclosed in applicant’s specification, para. 38. See Quach et al., para. 7, where there may be an ECC cache miss, which would be a read miss on a meta cache ) . 07-21-aia AIA Claim s 3, 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gatto et al. in view of Clark et al. (U.S. Patent Application No. 2010/0268987), herein referred to as Clark et al . As to claim 3, Gatto et al. disclose the claimed invention except for the apparatus of claim 2, in which the cache lookup component is configured to: generate a first tag check result based on receiving a data transaction; generate a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; compare the first tag check result and the second tag check result; and generate an error indication based on the first tag check result not matching the second tag check result. However, Clark et al. disclose generate a first tag check result based on receiving a data transaction ( see para. 104-105, where a hit signal is provided to indicate the result of a cache lookup ); generate a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result ( see para. 104-105, where a hit signal is provided to indicate the result of a cache lookup, and may be a dual redundant cache lookup ); compare the first tag check result and the second tag check result ( see para. 104-105, where comparators are used to compare the tag array output ); and generate an error indication based on the first tag check result not matching the second tag check result ( see para. 67, where if a dual redundant mismatch occurs, the pipelines are flushed and invalidated and the instruction that requested the translation is restarted ). Gatto et al. and Clark et al. are analogous art because they are from the same field of endeavor of mitigating errors ( see Gatto et al., abstract and Clark et al., abstract, regarding error mitigation ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise generate a first tag check result based on receiving a data transaction; generate a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; compare the first tag check result and the second tag check result; and generate an error indication based on the first tag check result not matching the second tag check result. as taught by Clark et al., in order to provide greater reliability and redundancy. As to claim 8, Gatto et al. disclose the claimed invention except for the method of claim 8, further comprising: generating a first tag check result based on receiving the data transaction; generating a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; comparing the first tag check result and the second tag check result; and generating an error indication based on the first tag check result not matching the second tag check result. However, Clark et al. disclose generate a first tag check result based on receiving a data transaction ( see para. 104-105, where a hit signal is provided to indicate the result of a cache lookup ); generate a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result ( see para. 104-105, where a hit signal is provided to indicate the result of a cache lookup, and may be a dual redundant cache lookup ); compare the first tag check result and the second tag check result ( see para. 104-105, where comparators are used to compare the tag array output ); and generate an error indication based on the first tag check result not matching the second tag check result ( see para. 67, where if a dual redundant mismatch occurs, the pipelines are flushed and invalidated and the instruction that requested the translation is restarted ). Gatto et al. and Clark et al. are analogous art because they are from the same field of endeavor of mitigating errors ( see Gatto et al., abstract and Clark et al., abstract, regarding error mitigation ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise generate a first tag check result based on receiving a data transaction; generate a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; compare the first tag check result and the second tag check result; and generate an error indication based on the first tag check result not matching the second tag check result. as taught by Clark et al., in order to provide greater reliability and redundancy. As to claim 14, Gatto et al. and Clark et al. also disclose the method of claim 13, in which the error indication is an interrupt ( see Gatto et al., para. 22, where an error may be passed to an LRAID controller upon detecting an error ). As to claim 20, Gatto et al. disclose the claimed invention except for the apparatus of claim 15, further comprising: means for generating a first tag check result based on receiving the data transaction; means for generating a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; means for comparing the first tag check result and the second tag check result; and means for generating an error indication based on the first tag check result not matching the second tag check result. However, Clark et al. disclose means for generating a first tag check result based on receiving the data transaction; means for generating a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result ( means for generating a tag check result may be a cache lookup component, based on applicant’s specification, para. 73. See Clark et al., para. 104-105, where a hit signal is provided to indicate the result of a cache lookup, and may be a dual redundant cache lookup ); means for comparing the first tag check result and the second tag check result ( means for comparing may be a cache lookup component or safety mechanism as disclosed in applicant’s specification, para. 38. See Clark et al., para. 104-105, where comparators and a dual redundant cache lookup are used to compare the tag array output ); and means for generating an error indication based on the first tag check result not matching the second tag check result ( means for generating an error indication may be a cache lookup component, based on applicant’s specification, para. 73. See Clark et al., para. 67, where if a dual redundant mismatch occurs, the pipelines are flushed and invalidated and the instruction that requested the translation is restarted. This occurs due to a tag check result at the cache lookup, as indicated in para. 104-105 ). Gatto et al. and Clark et al. are analogous art because they are from the same field of endeavor of mitigating errors ( see Gatto et al., abstract and Clark et al., abstract, regarding error mitigation ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gatto et al. to comprise means for generating a first tag check result based on receiving the data transaction; means for generating a second tag check result based on receiving the data transaction, the second tag check result generated in parallel with the first tag check result; means for comparing the first tag check result and the second tag check result; and means for generating an error indication based on the first tag check result not matching the second tag check result, as taught by Clark et al., in order to provide greater reliability and redundancy. CLOSING COMMENTS Conclusion a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i) : a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a first action on the merits and are the subject of a first action non-final. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.O/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 18/882,560 Page 2 Art Unit: 2132
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