DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Device with Laminated Structure and Capacitors.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-11, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al (US 2023/0180456).
Regarding Claim 1, Jeong et al discloses a semiconductor memory device (semiconductor memory device [0010] Fig 2 and Fig 4), comprising: a laminated structure (shown in annotated Fig 4) with a plurality of first layers (shown in annotated Fig 4) and a plurality of second layers (shown in annotated Fig 4) alternately stacked in a first direction (vertical z direction Fig 4);
a first bit line (150 (left) [0037] Fig 4) that extends in the first direction (vertical z direction Fig 4) through the laminated structure (shown in annotated Fig 4); and
a second bit line (150 (right) [0037] Fig 4) that extends in the first direction through the laminated structure (shown in annotated Fig 4), the second bit line (150 (right) Fig 4) being spaced from the first bit line (150 (left) Fig 4) in a second direction (horizontal x direction Fig 4) crossing the first direction (vertical z direction Fig 4),
wherein each first layer (shown in annotated Fig 4) includes:
a word line (word line 130 [0049] Fig 4) that extends in the second direction (horizontal x direction Fig 4),
a first semiconductor layer (transistor body 120 (left) which is a semiconductor material [0040] Fig 4) that extends in the second direction (horizontal x direction Fig 4) alongside word line (130 Fig 4) and is connected to the first bit line (150 (left) Fig 4),
a second semiconductor layer (transistor body 120 (right) which is a semiconductor material [0040] Fig 4) that extends in the second direction (horizontal x direction Fig 4) alongside the word line (130 Fig 4), the second semiconductor layer (120 (right) Fig 4) being spaced from the first semiconductor layer (120 (left) Fig 4) in the second direction (horizontal x direction Fig 4) and connected to the second bit line (150 (right) Fig 4),
a first gate insulating layer (gate insulating layer 140 (left) [0051] Fig 4) between the word line (130 Fig 4) and the first semiconductor layer (120 (left) Fig 4),
a second gate insulating layer (gate insulating layer 140 (right) [0051] Fig 4) between the word line (130 Fig 3) and the second semiconductor layer (120 (right) Fig 4),
a first part (first electrode EL1 (left) [0056] Fig 4) of a first capacitor (cell capacitor CAP (left) [0056] Fig 4) connected to the first semiconductor layer (120 (left) Fig 4), and
a first part (first electrode EL1 (right) [0056] Fig 4) of a second capacitor (cell capacitor CAP (right) [0056] Fig 4) connected to the second semiconductor layer (120 (right) Fig 4).
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Regarding Claim 2, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein the word lines (130 Fig 4) in each first layer (shown above in annotated Fig 4) overlap when viewed from the first direction (vertical z direction Fig 4).
Regarding Claim 3, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein the first semiconductor layers (120 (left) Fig 4) overlap with each other when viewed from the first direction (vertical z direction Fig 4), and the second semiconductor layers (120 (right) Fig 4) overlap with each other when viewed from the first direction (vertical z direction Fig 4).
Regarding Claim 4, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein, when viewed from the first direction (vertical z direction Fig 4), the first semiconductor layers (120 (left) Fig 4) are aligned with the second semiconductor layers (120 (right) Fig 4) on a straight line that extends in the second direction (horizontal x direction Fig 4).
Regarding Claim 7, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein each second layer (shown above in annotated Fig 4) includes: an insulating layer (separation insulating layer 166 [0052] Fig 4) which has a part between word lines (130 Fig 4) adjacent to each other in the first direction (vertical z direction Fig 4), a part between first semiconductor layers (120 (left) Fig 4) adjacent to each other in the first direction (vertical z direction Fig 4), and a part between second semiconductor layers (120 (right) Fig 4) adjacent to each other in the first direction (vertical z direction Fig 4).
Regarding Claim 8, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein each first capacitor (cell capacitor CAP (left) [0056] Fig 4) further includes a second part (upper part shown in Fig 4) in an adjacent second layer, and each second capacitor (cell capacitor CAP (right) [0056] Fig 4) further includes a second part (upper part shown in Fig 4), provided in the adjacent second layer.
Regarding Claim 9, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
wherein each first capacitor (cell capacitor CAP (left) [0056] Fig 4) and each second capacitor (cell capacitor CAP (right) [0056] Fig 4) includes a first electrode (first electrode EL1 [0056] Fig 4), a second electrode (second electrode EL2 [0056] Fig 4), and a dielectric layer (capacitor dielectric layer DL [0056] Fig 4) provided between the first electrode (EL1 Fig 4) and the second electrode (EL2 Fig 4).
Regarding Claim 10, Jeong et al discloses the limitations of claim 9 as explained above. Jeong et al further discloses
wherein the first electrode (EL1 Fig 4) of each first capacitor (CAP (left) Fig 4) is connected to a corresponding first semiconductor layer (120 (left) Fig 4), and the first electrode (EL1 Fig 4) of each second capacitor (CAP (right) Fig 4) is connected to a corresponding second semiconductor layer (120 (right) Fig 4).
Regarding Claim 11, Jeong et al discloses the limitations of claim 9 as explained above. Jeong et al further discloses
further comprising: a common electrode (central portion of second electrode EL2 [0037] Fig 4) that extends in the first direction (vertical z direction Fig 4) through the laminated structure (shown above in annotated Fig 4), the common electrode (central portion of EL2 Fig 4) being connected to each second electrode (EL2 Fig 4) of the first (CAP (left) Fig 4) and second capacitors (CAP (right) Fig 4).
Regarding Claim 12, Jeong et al discloses the limitations of claim 1 as explained above. Jeong et al further discloses
further comprising: a first insulating part that extends in the first direction (vertical z direction Fig 4) through the laminated structure (shown above in annotated Fig 4), the first insulating part being between the first semiconductor layers (120 (left) Fig 4) and the second semiconductor layers (120 (right) Fig 4) in the second direction (horizontal x direction Fig 4).
Regarding Claim 17, Jeong et al discloses a semiconductor memory device (semiconductor memory device [0010] Fig 2 and Fig 4), comprising:
a laminated structure (shown in annotated Fig 4) with a plurality of first layers (shown in annotated Fig 4) and a plurality of second layers (shown in annotated Fig 4) alternately stacked in a first direction (vertical z direction Fig 4);
a common electrode (portion of second electrode EL2 [0037] shown in annotated Fig 3) that extends through the laminated structure (shown in annotated Fig 4) in the first direction (vertical z direction Fig 4) and extends a second direction (into the page y direction Fig 4) crossing the first direction (vertical z direction Fig 4) to divide the laminated structure (shown in annotated Fig 4) into a first side (left side) and second side (right side),
the common electrode (portion of EL2 shown in annotated Fig 3) being between the first side (left side) and the second side (right side) in a third direction (x direction Fig 3 and Fig 4) crossing the first (vertical z direction Fig 3 and Fig 4) and second directions (vertical y direction Fig 3 and into the page y direction Fig 4);
a first bit line (150 (left) [0037] Fig 3 and Fig 4) in a first section (bottom section shown in annotated Fig 3) on the first side (left side Fig 4) of the laminated structure (shown in annotated Fig 4), the first bit line (150 (left) Fig 4, 150 (bottom left) Fig 3) extending in the first direction (vertical z direction Fig 3 and Fig 4) through the laminated structure (shown in annotated Fig 4); and
a second bit line (150 (left) [0037] Fig 4) in a second section (top section shown in annotated Fig 3) on the first side (left side Fig 4) of the laminated structure (shown in annotated Fig 4), the second bit line (150 (left) Fig 4, 150 (top left) Fig 3) extending in the first direction (vertical z direction Fig 3 and Fig 4) through the laminated structure (shown in annotated Fig 4), the second bit line (150 (left) Fig 4, 150 (top left) Fig 3) being spaced from the first bit line (150 (left) Fig 4, 150 (bottom left) Fig 3) in the second direction (vertical y direction Fig 3 and into the page y direction Fig 4),
wherein each first layer (shown in annotated Fig 4) includes:
a word line (word line 130 [0049] Fig 4) that extends in the second direction (vertical y direction Fig 3 and into the page y direction Fig 4),
a first semiconductor layer (transistor body 120 (left) which is a semiconductor material [0040] Fig 4) that extends in the second direction (vertical y direction Fig 3 and into the page y direction Fig 4) alongside word line (130 Fig 4) and is connected to the first bit line (150 (left) Fig 4, 150 (bottom left) Fig 3),
a second semiconductor layer (transistor body 120 (left) which is a semiconductor material [0040] Fig 4) that extends in the second direction (vertical y direction Fig 3 and into the page y direction Fig 4) alongside the word line (130 Fig 4), the second semiconductor layer (120 (left) Fig 4, 120 (top left) Fig 3) being spaced from the first semiconductor layer (120 (left) Fig 3, 120 (bottom left) Fig 3) in the second direction (vertical y direction Fig 3 and into the page y direction Fig 4) and connected to the second bit line (150 (left) Fig 4, 150 (top left) Fig 3),
a first gate insulating layer (gate insulating layer 140 (left) [0051] Fig 4, 140 (bottom left) Fig 3) between the word line (130 Fig 4) and the first semiconductor layer (120 (left) Fig 4, 120 (bottom left) Fig 3),
a second gate insulating layer (gate insulating layer 140 (left) [0051] Fig 4, 140 (top left) Fig 3) between the word line (130 Fig 4) and the second semiconductor layer (120 (left) Fig 4, 120 (top left) Fig 3),
a first part (first electrode EL1 (left) [0056] Fig 4) of a first capacitor (cell capacitor CAP (left) [0056] Fig 4) connected to the first semiconductor layer (120 (left) Fig 4, 120 (bottom left) Fig 3); and
each second layer (shown in annotated Fig 4) includes:
an insulating layer (spacer buried layer 162 and separation insulating layer 166 [0052] Fig 4) which has a part (shown in Fig 3 and Fig 4) between word lines (130 Fig 4) adjacent to each other in the first direction (vertical z direction Fig 4), a part (shown in Fig 4) between first semiconductor layers (120 (left) Fig 3, 120 (bottom left) Fig 3) adjacent to each other in the first direction (vertical z direction Fig 4), and a second part (shown in Fig 4) of the first capacitor (CAP (left) Fig 4) that is in an adjacent first layer (shown in annotated Fig 4).
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Regarding Claim 19, Jeong et al discloses the limitations of claim 17 as explained above. Jeong et al further discloses
wherein the first bit line (150 (left) Fig 4, 150 (bottom left) Fig 3) is a columnar structure (shown in Fig 4).
Allowable Subject Matter
Claims 5-6, 12-16, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5:
Regarding Claim 5, Jeong et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 5 is the inclusion of
further comprising: a first body contact that extends in the first direction through the laminated structure, the first body contact being connected to the first semiconductor layers; and
a second body contact that extends in the first direction through the laminated structure, the second body contact being connected to the second semiconductor layers.
Specifically, Jeong et al does not disclose a first body contact or a second body contact extending through the laminated structure as 41 or 42 as shown in Fig 1 of the instant application. Further, should a secondary reference be found that discloses a first body contact or a second body contact, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Jeong et al to include these features.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 6 would be allowable based on its dependency on Claim 5.
Claim 12:
Regarding Claim 12, Jeong et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 12 is the inclusion of
further comprising: a first insulating part that extends in the first direction through the laminated structure, the first insulating part being between the first semiconductor layers and the second semiconductor layers in the second direction.
Specifically, Jeong et al does not disclose a first insulating part extending through the laminated structure as 51b as shown in Fig 1 of the instant application. Further, should a secondary reference be found that discloses a first insulating part, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Jeong et al to include this feature in this precise location.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 13-16 would be allowable based on their dependency on Claim 12.
Claim 18:
Regarding Claim 18, Jeong et al discloses the limitations of claim 17 as explained above.
The reason for the indication of allowability of Claim 18 is the inclusion of
further comprising: a body contact in the first section and extending in the first direction through the laminated structure, the body contact being connected to the first semiconductor layers.
Specifically, Jeong et al does not disclose a body contact extending through the laminated structure as 41 or 42 as shown in Fig 1 of the instant application. Further, should a secondary reference be found that discloses a body contact, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Jeong et al to include these features.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 20:
Regarding Claim 20, Jeong et al discloses the limitations of claim 17 as explained above.
The reason for the indication of allowability of Claim 18 is the inclusion of
further comprising: a first insulating part that extends in the first direction through the laminated structure, the first insulating part being between the first semiconductor layers and the second semiconductor layers in the second direction, and
a second insulating part that extends in the first direction through the laminated structure, the second insulating part being adjacent to the first semiconductor layers in the third direction.
Specifically, Jeong et al does not disclose a first insulating part and a second insulating part extending through the laminated structure as 51b and 52b as shown in Fig 1 of the instant application. Further, should a secondary reference be found that discloses a first insulating part and a second insulating part, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Jeong et al to include these feature in these precise locations.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 2022/0199621) which discloses a semiconductor memory device [0018]-[0019], and Yim et al (US 2023/0301063) which discloses a semiconductor device with first pillar insulation patterns [0005].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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