Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
The application claims priority to Korean Patent Application No. 10-2024-0055302, filed on April 25, 2024, in the Korean Intellectual Property Office.
The application includes a timely claim for foreign priority as indicated in the Application Data Sheet (ADS). The Filing Receipt also lists the foreign priority information in the “Foreign Applications” section, confirming that the priority claim was properly submitted.
However, the certified copy of the foreign priority document has not been retrieved through the Priority Document Exchange (PDX) system. The PDX retrieval attempt on 09/25/2025 was unsuccessful. In addition, Applicant has not filed a certified copy of the foreign priority document in the present application.
Applicant is required to submit a certified copy of the foreign priority document in accordance with 37 CFR 1.55 in order to perfect the foreign priority claim.
Failure to timely provide the certified copy may result in loss of the foreign priority benefit.
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 09/12/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIN et al. (US Pub. 2020/0242068).
Regarding independent claim 1, LIN discloses a memory system (Fig.1 and [0028]: a smart interface circuit 100 that connects a host device 14 and a storage device 14, constituting a memory system) comprising:
at least one memory device (Fig.1: storage device 14); and
a controller (Fig.1: the smart interface circuit 100) comprising
at least one mailbox (Fig.1: instruction register 120 and data buffer 130) configured to receive a doorbell signal to output an interrupt signal (Fig.1 & Fig.2 and [0029]-[0034]: The instruction register 120 and data buffer 130 function as a mailbox storing received protocol commands and their associated doorbell signals),
a processor (Fig.1: first protocol processing circuit 110) configured to process a mailbox command based on the interrupt signal (Fig.1 & Fig.2 and [0029]-[0034]: The first protocol processing circuit 110 receives interrupts and processes corresponding commands), and
at least one logic (Fig.1: The second protocol processing circuit 140) configured to perform a preset operation (Fig.1 & Fig.2 and [0029]-[0034]: The second protocol processing circuit 140 executes NVMe protocol commands, functioning as logic performing preset operations),
wherein the at least one mailbox (Fig.1: instruction register 120 and data buffer 130) is configured to:
transfer, to the processor (Fig.1: first protocol processing circuit 110), the interrupt signal based on a first doorbell signal corresponding to a first command when receiving the first command input from a host (Fig.1: Host 12) (Fig.1 & Fig.2 and [0029]-[0034]: The instruction register 120 and data buffer 130 transfer first command related interrupts, associated with a first protocol command CMD IU_1 and its read completion, to the first protocol processing circuit 110); and
transfer, to the at least one logic (Fig.1: The second protocol processing circuit 140), a second doorbell signal corresponding to a second command when receiving the second command input from the host (Fig.1: Host 12) (Fig.1 & Fig.2 and [0029]-[0034]: the second protocol processing circuit 140 receives second protocol commands CMD IU_2 or X/Y commands that are associated with doorbell signals).
Regarding independent claim 15, LIN discloses a controller (Fig.1: the smart interface circuit 100) comprising:
at least one processor (Fig.1: first protocol processing circuit 110) configured to execute a first command input from an external device (Fig.1 & Fig.2 and [0029]-[0034]: The first protocol processing circuit 110 executes first protocol commands CMD IU_1);
at least one logic (Fig.1: The second protocol processing circuit 140) configured to perform a preset operation (Fig.1 & Fig.2 and [0029]-[0034]: The second protocol processing circuit 140 performs the logic operations of retrieving and executing NVMe commands from storage device 14); and
a mailbox (Fig.1: instruction register 120 and data buffer 130) configured to transfer a doorbell signal (i.e, doorbell signals associated with second protocol commands ([0032]-[0034]) to the at least one logic (Fig.1: The second protocol processing circuit 140) (Fig.1 & Fig.2 and [0029]-[0034]: The second protocol processing circuit receives these doorbell triggered commands for execution. Instruction register 120 and buffer 130 serve as mailbox storing these signals) after transferring an interrupt signal corresponding to the first command to the at least one processor (Fig.1: first protocol processing circuit 110) (Fig.1 & Fig.2 and [0029]-[0034]: first command completion generates “Read completion -> Interrupt” sent to the first protocol processing circuit 110. Afterwards the second protocol processing circuit 140 processes doorbell associated second commands).
Regarding claim 13, LIN teaches wherein the controller is configured to perform data input/output operations to the at least one memory device, regardless of the first command input to the at least one mailbox (Fig.1 and [0033]: For a better understanding, in the following description the first interface 102 is a USB (Universal Serial Bus) interface 102, the second interface 104 is a PCIe (Peripheral Component; Interconnect Express) interface 104, the first device 12 is a host 12 (e.g., a personal computer), the second device 14 is a storage device 14 (e.g., a solid-state driver (SSD)), the first data and second data are the first stored data and second stored data stored in the storage device 14 respectively, the first protocol processing circuit 110 is a UAS (USB Attached SCSI (Small Computer System Interface)) protocol processing circuit 110, the second protocol processing circuit 140 is an NVMe (Non-Volatile Memory Express) protocol processing circuit 140, the first protocol command is a UAS command, and each second protocol command(s) is an NVMe command).
Regarding claim 14, The memory system according to claim 1, wherein the at least one logic is configured to perform detailed operations associated with data input/output operations within the controller, or perform a background operation for the data input/output operations (Fig.1 and [0033]: For a better understanding, in the following description the first interface 102 is a USB (Universal Serial Bus) interface 102, the second interface 104 is a PCIe (Peripheral Component; Interconnect Express) interface 104, the first device 12 is a host 12 (e.g., a personal computer), the second device 14 is a storage device 14 (e.g., a solid-state driver (SSD)), the first data and second data are the first stored data and second stored data stored in the storage device 14 respectively, the first protocol processing circuit 110 is a UAS (USB Attached SCSI (Small Computer System Interface)) protocol processing circuit 110, the second protocol processing circuit 140 is an NVMe (Non-Volatile Memory Express) protocol processing circuit 140, the first protocol command is a UAS command, and each second protocol command(s) is an NVMe command).
Allowable Subject Matter
Claims 2-12, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 identifies the distinct features “wherein an operation code corresponding to the first command is input to a command register, and wherein an identifier used to specify a first logic among the at least one logic, and an operation code corresponding to a logic command to be performed by the first logic, which are accompanied by the first command, are input to a payload register", which are not taught or suggested by the prior art of records.
Claims 3-12, which respectively depend on objected-to claim 2, are allowable for at least the same reasons as claim 2.
Claim 16 identifies the distinct features “wherein the first command comprises an identifier used to specify a first logic among the at least one logic and an operation code corresponding to a logic command to be performed by the first logic", which are not taught or suggested by the prior art of records.
Claims 17 and 18, which respectively depend on objected-to claim 16, are allowable for at least the same reasons as claim 16.
Claim 19 identifies the distinct features “wherein the mailbox comprises: plural registers comprising a doorbell register, a command register, a return code register, and a payload register; and parsing circuitry configured to parse a second command and a third command input through the command register from the external device and determine whether to transfer the doorbell signal input through the doorbell register to the at least one logic", which are not taught or suggested by the prior art of records.
Claim 20, which respectively depends on objected-to claim 19, are allowable for at least the same reasons as claim 19.
Claims 2-12, 16-20 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Related Prior Art but Not Cited
PTO-892 contains the complete list of all references reviewed during the search. A few representative related prior art references that were reviewed but not cited are briefly noted here for the applicant’s convenience.
Slaight et al. (Pub. No.: US 2014/0189212) “Presentation of direct accessed storage under a logical drive model”
Considered for teachings related to the field of computing, and more particularly to the presentation of direct accessed storage under a logical drive model, including methods, systems, and apparatuses for implementing presentation of direct accessed storage under a logical drive model and other complementary solutions related to Direct memory access (DMA) based storage technologies, such as improved Redundant Array of Independent Disks (RAID) support, distributed RAID support, local block mirroring for improving device latency consistency, improved door bell schemes for coalescence and arbitration, as such improvements relate to DMA based storage technologies.
Does not disclose or suggest wherein the at least one mailbox is configured to: transfer, to the processor, the interrupt signal based on a first doorbell signal corresponding to a first command when receiving the first command input from a host; and transfer, to the at least one logic, a second doorbell signal corresponding to a second command when receiving the second command input from the host.
HORWICH (Pub. No.: US 2025/0315377) “Method for creating multi-namespace and method for accessing data therein”
Considered for teachings related to the host-side signaling that can issue or assert the doorbell, an interrupt, a mailbox, or a coherency mechanism (e.g., such as monitor/mwake, etc.).
Does not disclose or suggest wherein the at least one mailbox is configured to: transfer, to the processor, the interrupt signal based on a first doorbell signal corresponding to a first command when receiving the first command input from a host; and transfer, to the at least one logic, a second doorbell signal corresponding to a second command when receiving the second command input from the host.
Conclusion
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135