DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 14-15, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “high-speed” in claims 2-4, 14-15, and 21 is a relative term which renders the claim indefinite. The term “high-speed” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, each of these claims uses or depends on language stating “high-speed interconnect ASIC”. It is unclear what exactly constitutes a “high-speed” interconnect ASIC in comparison to an interconnect ASIC that is not “high-speed”. The specification and claims do not provide any specific definition of the term “high-speed”. Thus it is unclear what specific speed or speeds equate to the claimed “high-speed” interconnect ASIC. For purposes of examination in view of the prior art, it will be assumed that any interconnect ASIC capable of performing the claimed functions is equivalent to the claimed “high-speed interconnect ASIC”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-17, 19, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Quartiroli et al. (U.S. Publication US 2024/0048144 A1).
With respect to claim 1, Quartiroli et al. discloses a syntonization system, comprising: a device (See the abstract, paragraph 19, and Figure 1 of Quartiroli et al. for reference to an electronic system including a device, i.e. sensor 10.1, wherein the system performs synchronization of a local oscillator to a bus clock CKB that is a master clock). Quartiroli et al. also discloses a dedicated clock signal input interface to be connected by a clock connection to a remote device and to receive a remote clock signal from the remote device, the remote device being external to the device (See paragraph 19, paragraph 25, paragraph 27, and Figures 1 and 2 of Quartiroli et al. for reference to the device including an interface to receive the bus clock CKB, which is a remote clock signal generated by a processing unit 2 external from the sensor 10.1). Quartiroli et al. further disclose clock circuitry to generate a local clock signal (See paragraph 22 and Figure 2 of Quartiroli et al. for reference to an oscillator 14 producing a local clock signal CKJ). Quartiroli et al. also discloses a digital clock controller to: generate digital control signals to control the clock circuitry to syntonize the local clock signal according to the remote clock signal based on a difference between frequencies of the remote clock signal and the local clock signal (See paragraph 29, paragraphs 34-35, and Figures 2 and 3 of Quartiroli et al. for reference to an all-digital phased locked loop 25, which is a digital clock controller, that generates a signal CKRS, which is a control signal used to syntonize the local clock CKJ to the bus clock CKB based on a frequency ratio between the clocks CKJ and CKB, wherein the ratio is a difference between the frequencies of the clocks). Quartiroli et al. further discloses providing the digital control signals to the clock circuitry, wherein the clock circuitry is to adjust the frequency of the local clock signal based on the digital control signals (See paragraphs 34-38 and Figures 2 and 3 of Quartiroli et al. for reference to using the signal CKRS to obtain synchronization of the local clock CKJ with the external bus clock CKB, such that the local clock CKJ is adjusted based on the signal CKRS).
With respect to claim 2, Quartiroli et al. discloses wherein the device includes a high-speed interconnect ASIC, which includes the dedicated clock signal input interface (See paragraph 64 of Quartiroli et al. for reference to functionality of the device being provided at least partially in one or more ASIC, such that the interface receiving the bus clock CKB may be included on an ASIC).
With respect to claim 3, Quartiroli et al. discloses wherein the digital clock controller is disposed on the high-speed interconnect ASIC See paragraph 64 of Quartiroli et al. for reference to functionality of the device being provided at least partially in one or more ASIC, such that the all-digital phased locked loop 25 may be included on the ASIC).
With respect to claim 4, Quartiroli et al. discloses wherein the digital clock controller is to execute firmware to: generate the digital control signals to control the clock circuitry; and provide the digital control signals to the clock circuitry (See paragraphs 34-38, paragraph 64, and Figures 2 and 3 of Quartiroli et al. for reference to the functionality of the device being provided at least partially in firmware, such that the all-digital phased locked loop 25 generating and providing the signal CKRS to control the local clock CKJ may be implemented by executing firmware).
With respect to claim 5, Quartiroli et al. discloses wherein the digital clock controller is disposed in a host device which executes software to generate the digital control signals to control the clock circuitry; and provide the digital control signals to the clock circuitry (See paragraph 19, paragraphs 34-38, paragraph 63, and Figures 1-3 of Quartiroli et al. for reference to an embodiment wherein the functionality may take the form of a computer program product comprising an executed computer program stored on a computer readable medium, such that the all-digital phased locked loop 25 of the sensor 10.1, which is a host device, generating and providing the signal CKRS to control the local clock CKJ may be implemented by executing a computer program, i.e. software).
With respect to claim 6, Quartiroli et al. discloses wherein: the device includes at least one counter to count clock signal pulses of the remote clock signal and the local clock signal; and the digital clock controller is to generate the digital control signals based on at least one value of the at least one counter (See paragraph 29-37 and Figure 3 of Quartiroli et al. for reference to using counters to count pulses of the bus clock CKB and the local clock CKJ that are used to generate the signal CKRS by the all-digital phase locked loop 25).
With respect to claim 8, Quartiroli et al. discloses wherein: the device includes a counter to count a difference between clock signal pulses of the remote clock signal and clock signal pulses of the local clock signal; and the digital clock controller is to generate the digital control signals based on at least one value of the counter (See paragraph 29-37 and Figure 3 of Quartiroli et al. for reference to using counters to count pulses of the bus clock CKB and the local clock CKJ that are used to determine the frequency ratio, i.e. difference, between the clocks CKB and CKJ and used to generate the signal CKRS by the all-digital phase locked loop 25).
With respect to claim 9, Quartiroli et al. discloses wherein the digital clock controller is to generate the digital control signals in order to maintain the counter at a given value, which represents the local clock signal and the remote clock signal having a same frequency (See paragraph 29-37 and Figure 3 of Quartiroli et al. for reference to using counters to count pulses of the bus clock CKB and the local clock CKJ that are used to determine the frequency ratio, i.e. difference, between the clocks CKB and CKJ and used to generate the signal CKRS by the all-digital phase locked loop 25, such that the local clock CKJ is maintained in synchronization with the bus clock CKB).
With respect to claim 10, Quartiroli et al. discloses wherein: the device includes a first counter to count clock signal pulses of the remote clock signal; the device includes a second counter to count clock signal pulses of the local clock signal; and the digital clock controller is to generate the digital control signals based on at least one value of the first counter and at least one value of the second counter (See paragraph 29-37 and Figure 3 of Quartiroli et al. for reference to using counters to count pulses of the bus clock CKB and the local clock CKJ that are used to generate the signal CKRS by the all-digital phase locked loop 25).
With respect to claim 11, Quartiroli et al. discloses wherein the digital clock controller is to generate the digital control signals in order to maintain the first counter and the second counter at respective values that represent syntonization of the local clock signal and the remote clock signal (See paragraph 29-37 and Figure 3 of Quartiroli et al. for reference to using counters to count pulses of the bus clock CKB and the local clock CKJ that are used to determine the frequency ratio, i.e. difference, between the clocks CKB and CKJ and used to generate the signal CKRS by the all-digital phase locked loop 25, such that the local clock CKJ is maintained in synchronization with the bus clock CKB).
With respect to claim 12, Quartiroli et al. discloses wherein: the clock circuitry includes signal generation circuitry to generate a reference clock signal; and the clock circuitry also includes frequency manipulation circuitry to generate the local clock signal from the reference clock signal, the local clock signal and the reference clock signal having different frequencies (See paragraph 22 of Quartiroli et al. for reference to embodiments wherein each component of the device producing the local clock may be timed with a respective clock, i.e. a reference clock, obtained from the local clock, but not necessarily equal, i.e. having different frequencies, wherein the clock signal of each component may be obtained from the local clock signal CKJ by frequency division according to an integer number).
With respect to claim 13, Quartiroli et al. discloses wherein: the device includes ports (See paragraph 19, paragraph 22, and Figures 1 and 2 of Quartiroli et al. for reference to the device 10.1 including ports to receive input signals, as illustrated in the figures). Quartiroli et al. also discloses the frequency manipulation circuitry is to generate a network clock signal to drive the ports from the reference clock signal or from the local clock signal, the network clock signal and the local clock signal having different frequencies (See paragraph 22 of Quartiroli et al. for reference to embodiments wherein each component of the device producing the local clock may be timed with a respective clock, i.e. a reference clock, obtained from the local clock, but not necessarily equal, i.e. having different frequencies, wherein the clock signal of each component may be obtained from the local clock signal CKJ by frequency division according to an integer number).
With respect to claim 14, Quartiroli et al. discloses wherein: the device includes a circuit board including a high-speed interconnect ASIC; and the signal generation circuitry is disposed on the circuit board externally to the high-speed interconnect ASIC (See paragraph 64 of Quartiroli et al. for reference to functionality of the device being provided at least partially in one or more ASIC, such that the sensor 10.1 may include an ASIC partially implementing the functions of the sensor 10.1, but other functions, such as the functions of the all-digital phased locked loop 25 may be external to the ASIC).
With respect to claim 15, Quartiroli et al. discloses wherein the frequency manipulation circuitry is disposed on the high-speed interconnect ASIC (See paragraph 22 and paragraph 64 of Quartiroli et al. for reference to functionality of the device being provided at least partially in one or more ASIC, such that the function of obtaining the clock signal of each component from the local clock signal CKJ by frequency division may be provided by the ASIC).
With respect to claim 16, Quartiroli et al. discloses wherein the frequency manipulation circuitry includes at least one phase locked loop (PLL) circuit (See paragraph 22, paragraph 29, and Figures 2 and 3 of Quartiroli et al. for reference to the device comprising an all-digital phased locked loop 25 used to control the local clock, which is then used to generate the clock signal of each component).
With respect to claim 17, Quartiroli et al. discloses wherein the signal generation circuitry includes any one or more of the following: a digitally controlled oscillator; a network synchronizer; or a digital phase locked loop (DPLL) circuit (See paragraph 20-38 and Figures 2 and 3 of Quartiroli et al. for reference to the circuitry of the device used to generate to control signals for the local clock CKJ including an oscillator 14 and an all-digital phase locked loop 25).
With respect to claim 19, Quartiroli et al. discloses wherein the remote device is a non-network device and includes a clock output port (See paragraph 19 and Figure 1 of Quartiroli et al. for reference to the remote device being processing unit 2 including an output port to provide the bus clock CKB).
With respect to claim 21, Quartiroli et al. discloses further comprising a circuit board, wherein: the device is disposed on the circuit board and includes a high-speed interconnect ASIC; and the remote device is disposed on the circuit board externally to the high-speed interconnect ASIC (See paragraph 64 of Quartiroli et al. for reference to functionality of the device being provided at least partially in one or more circuits including an ASIC, such that components of the sensor 10.1 may implemented via the ASIC and the external processing unit 2 may be external to the ASIC of the sensor 10.1).
With respect to claim 22, Quartiroli et al. discloses a syntonization method (See the abstract, paragraph 19, and Figure 1 of Quartiroli et al. for reference to an electronic system including a device, i.e. sensor 10.1, wherein the system performs a method synchronization of a local oscillator to a bus clock CKB that is a master clock). Quartiroli et al. also discloses receiving a remote clock signal from a remote device via a clock connection using a dedicated clock input interface (See paragraph 19, paragraph 25, paragraph 27, and Figures 1 and 2 of Quartiroli et al. for reference to the device including an interface receiving the bus clock CKB, which is a remote clock signal generated by a processing unit 2 external from the sensor 10.1). Quartiroli et al. further discloses generating a local clock signal (See paragraph 22 and Figure 2 of Quartiroli et al. for reference to an oscillator 14 producing a local clock signal CKJ). Quartiroli et al. also discloses generating digital control signals to control clock circuitry to syntonize the local clock signal according to the remote clock signal based on a difference between frequencies of the remote clock signal and the local clock signal (See paragraph 29, paragraphs 34-35, and Figures 2 and 3 of Quartiroli et al. for reference to an all-digital phased locked loop 25, which is a digital clock controller, that generates a signal CKRS, which is a control signal used to syntonize the local clock CKJ to the bus clock CKB based on a frequency ratio between the clocks CKJ and CKB, wherein the ratio is a difference between the frequencies of the clocks). Quartiroli et al. further discloses providing the digital control signals to the clock circuitry; and adjusting the frequency of the local clock signal based on the digital control signals (See paragraphs 34-38 and Figures 2 and 3 of Quartiroli et al. for reference to using the signal CKRS to obtain synchronization of the local clock CKJ with the external bus clock CKB, such that the local clock CKJ is adjusted based on the signal CKRS).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Quartiroli et al. in view of Sinclair et al. (U.S. Publication US 2018/0294946 A1).
With respect to claim 7, Quartiroli et al. does not specifically disclose : the remote clock signal is received by the dedicated clock signal input interface from the remote device as an analog signal; and the dedicated clock signal input interface includes an analog to digital converter to convert the remote clock signal from an analog signal to a digital signal. However, the receipt of an analog clock signal and use of an analog to digital converter to convert the analog clock signal to a digital signal is old and well known in the art of communications. For example, Sinclair et al., in the field of communications, discloses performing time synchronization between clocks of a remote and master wherein an analog clock signal is received from the master and is converted into a digital signal by an analog to digital converter (See paragraph 16, paragraphs 152-153, and Figure 12 of Sinclair et al.). Using an analog to digital convert to convert a received analog clock signal to a digital signal has the advantage of allowing the analog clock signal of a master device to be used to control clock adjustment by digital circuitry of another device. Thus, it would have been obvious for one of ordinary skill in the art at the time of effective filing, when presented with the work of Sinclair et al., to combine using an analog to digital convert to convert a received analog clock signal to a digital signal, as suggested by Sinclair et al., within the system and method of Quartiroli et al., with the motivation being to allow the analog clock signal of a master device to be used to control clock adjustment by digital circuitry of another device.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Quartiroli et al. in view of Pind et al. (U.S. Publication US 2026/0058747 A1).
With respect to claim 18, Quartiroli et al. does not specifically disclose wherein the device is a syntonization leader device.
With respect to claim 20, Quartiroli et al. does not specifically disclose wherein the remote device includes any one or more of the following: a Global Navigation Satellite Systems (GNSS) receiver; an atomic clock; or a Precision Time Protocol (PTP) grand master.
With further respect to claims 18 and 20, Pind et al., in the field of communications, discloses the use of a clock-leader unit, i.e. a syntonization leader device, for orchestrating a resynchronization process among a plurality of devices, wherein the clock-leader unit receives a clock signal provided from an external signal source such as a PTP master (See paragraphs 13-16 of Pind et al.). Synchronizing multiple devices via a clock-leader unit based on an external signal from a PTP master has the advantage of allowing multiple different devices of a network to obtain synchronization to the PTP master. Thus, it would have been obvious for one of ordinary skill in the art at the time of effective filing, when presented with the work of Pind et al., to combine synchronizing multiple devices via a clock-leader unit based on an external signal from a PTP master, as suggested by Pind et al., within the system and method of Quartiroli et al., with the motivation being to allow multiple different devices of a network to obtain synchronization to the PTP master.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason E Mattis whose telephone number is (571)272-3154. The examiner can normally be reached M-F 7:00am-4:30pm.
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/JASON E MATTIS/Primary Examiner, Art Unit 2461
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