DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim(s) 1-20 do not use “means for” (or “step for”) language, or generic placeholders for "means” coupled with functional language without recitation of sufficient structure for carrying out the claimed functions and therefore do not invoke 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim et al. (US 2022/0337777 A1).
[Claim 11]
Regarding claim 11, Shim teaches an image sensor device (Figure 1, 100) comprising:
a row driver (Figure 1, 120) configured to output a reset signal (Figure 1, RS), a transmission signal (Figure 2, TS), a selection signal (a selection signal SEL), and
a filler signal (Figure 2, LRS); and
a pixel array (Figure 1, 110) including a first pixel (Figure 2, pixel PX) connected to a first column line (Figure 1, CL), wherein the first pixel includes a reset transistor (Figure 2, RG) connected between a power supply voltage (Figure 2, VPIX) and a floating diffusion node (Figure 2, FD1) of the first pixel (Figure 2, pixel PX), the reset transistor (Figure 2, RG) configured to operate in response to the reset signal (RS),
a transmission gate transistor (Figure 2, TG) connected between the floating diffusion node (FD1) and a zeroth node of the first pixel (Figure 2, PD), the transmission gate transistor (Figure 2, TG) configured to operate in response to the transmission signal (Figure 2, TS),
a photodiode (Figure 2, PD) connected between the zeroth node and a ground voltage, the photodiode configured to sense light to accumulate charges,
a filler transistor (Figure 2, LRG) connected between a filler voltage (Figure 2, BST) and the floating diffusion node (FD1), the filler transistor (Figure 2, LRG) configured to operate in response to the filler signal (Figure 2, LRS) to connect the floating diffusion node (FD1) to the filler voltage (BST), and the filler voltage (BST) being lower than the power supply voltage (Figure 2, VPIX),
a source follower transistor(Figure 2, DX) connected between the power supply voltage(VPIX) and a first node (Figure 2, common node , DX and SX), the source follower transistor(DX) configured to operate in response to a voltage of the floating diffusion node(FD1), and a selection transistor(Figure 2, SX) connected between the first node and the first column line (Figure 1, CL), the selection transistor (SX) configured to operate in response to the selection signal (Figure 2, SEL).
[Claim 17]
Regarding claim 17,
Shim teaches a method of operating an image sensor device (Shim, Figure 1, 100) using
a sensor controller (Figure 1, 150), the image sensor device (Figure 1, 100) including a pixel (PX) that outputs a pixel signal (pixel signal received through each of the plurality of the column lines CL, paragraph 0039), the pixel including
a reset transistor (Figure 2, RG) connected between a power supply voltage and a floating diffusion node (Figure 2, FD1) of the pixel,
a transmission gate transistor (Shim, Figure 2, TG) connected between the floating diffusion node (FD1) and a zeroth node (Shim, Figure 2, PD) of the pixel PX, and
a filler transistor (Shim, Figure 2, LRG) connected between a filler voltage (Figure 2, BST) and the floating diffusing node (FD1),
the method comprising:
turning on the filler transistor (by turning on the LCG transistor LRG in response to a LCG control signal LRS) during a time period between T7 and T10 (Figure 4) to reduce a voltage (Shim, LCG transistor may connect the first diffusion node FD1 to a third diffusion node FD3, paragraphs 0048- 0049)
of the floating diffusion node from a first voltage to a second voltage lower than the first voltage (as the floating diffusion node FD1 is connected to third diffusion node FD3, and a CAP, capacitance may increase, paragraph 0049). The floating diffusion node is at steady state prior to this period and having additional capacitor CAP and floating diffusion node FD2 is connected during this period.
Therefore, increasing the capacitance of the floating diffusion node FD1, by adding a CAP and floating diffusion node FD2 and FD3, reduces the voltage of the diffusion node FD1 lower than the first voltage. This is because of the relationship between charge Q, voltage V and capacitance C, where V = Q/C. Since the charge remains same, increasing capacitance C would reduce the voltage.
turning on the reset transistor (RG) during a time period between T0 and T1 (Shim, Figure 4) to reset the floating diffusion node; and
comparing a voltage of the pixel signal (pixel signal received through each of the plurality of the column line CL, paragraph 0039) with a voltage of a ramp signal ADC circuit 131 (Figure 1) comparing pixel signal received from column line CL with the ramp signal (Shim, paragraph 0039).
[Claim 18]
Regarding claim 18, Shim’s disclosure further addresses the requirements set forth in claim 17 by teaching the inclusion of a filler transistor (LRG) that is connected between the floating diffusion node (FD1) and a bias voltage, which is referred to as BST and illustrated in Figure 2. Shim specifies that the BST voltage can be set to a ground voltage, as described in paragraph 0109.
[Claim 20]
Regarding claim 20, Shim teaches an image device (Figure 1, 100) wherein the pixel PX further comprises:
a photodiode (Figure 2, PD) connected between the zeroth node (corresponding cathode node of the photodiode PD) and a ground node; the photodiode (PD) configured to sense light to accumulate charges. Shim further teaches that the photodiode PD generate photo-charges that vary according to the intensity of the light (Shim, paragraph 0046).
Shim also discloses that the voltage at the zeroth node, corresponding to the cathode of the photodiode (PD), reaches its maximum value during conditions of lowest illumination, and, photodiode is at the highest voltage directly after reset and prior to receiving light since receiving light generates charge which would reduce the photodiode voltage (Shim, paragraph 0046).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 6-9, 12-14, 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2022/0337777 A1) in view of Voss et al. (US 2003/0147640 A1).
[Claim 1]
Regarding claim 1, Shim teaches an image sensor device (Shim, Figure 1, 100) comprising:
a pixel (Figure 2, PX),
a column line (Shim, Figure 1, CL), a sensor controller (Shim, Figure 1, 150) connected to the pixel, wherein the pixel includes
a reset transistor (Shim, Figure 2, RG) connected between a power supply voltage (VPIX) and a floating diffusion node (Shim, Figure 2, FD1) of the pixel,
a transmission gate transistor (Figure 2, TG) connected between the floating diffusion node (FD1) and a zeroth node (Figure 2, cathode of the photodiode PD) of the pixel (PX),
a photodiode (Figure 2, PD) connected between the zeroth node (common node between the cathode of the photodiode and the transmission transistor (Shim, Figure 2, TG) and a ground voltage,
a filler transistor (Shim, Figure 2, LRG) connected between a filler voltage (Shim, Figure 2, BST) and the floating diffusion node (FD1),
a source follower transistor (Shim, Figure 2, DX) connected between the power supply voltage
and a first node (Shim, Figure 2, a common node between drive transistor DX and a selection
transistor SX), and
a selection transistor (Shim, Figure 2, SX) connected between the first node and the column line (Shim, Figure 1, CL), and wherein the sensor controller (Shim, Figure 1, 150) is configured to turn on the filler transistor (Shim, Figure 2, LRG).
Shim further teaches during a first time period (Figure 4, first time period is between T7 and
before T10), and
turn on the reset transistor (Figure2, RG) during a second time period (Figure 4, between T0 and T1).
However, Shim does not teach the second time period to occur after the first time period.
Voss, teaches a system for capturing and embedding high resolution still images in a burst
mode. During burst mode, high resolution still images are captured sequentially and the single frame is repeated multiple as shown in (Voss, Figure 3A) where still image data frames, represented using reference numeral 314 (Voss, Figure 3A, paragraph 0049). Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Shim with the teaching of Voss to operate high resolution burst mode image capturing with the same camera.
In a burst mode, a first period T7 to T10 in N-1 frame would be followed by second period T0 to T1, in an N frame (Shim, Figure 4, repeated as taught by Voss).
[Claim 2]
Regarding claim 2, Shim in view of Voss, teach all the limitations outlined in claim 1 of the image sensor device. In particular, Shim describes a sequence during the first period, specifically between time periods T7 and T10, where the floating diffusion node (Shim, Figure 2, FD1) is electrically connected to a capacitor (Shim, Figure 2, CAP). This connection results in an increase in the total capacitance associated with the floating diffusion node. During the first time period (Shim, time period between T7 and T10), diffusion node FD2 is connected to floating diffusion node FD1, in addition to diffusion node FD2 and CAP. In the first time period, the reset transistor RG is turned off and the reset to VPIX is not occurring until the second time period between time T0 and T1, as outlined in (Shim, Figure 4). The floating diffusion node is at steady state prior to this period and having additional capacitor CAP and floating diffusion node FD2 is connected during this period.
Due to the increased capacitance (combined capacitance of FD2, FD3 and CAP), the voltage of the floating node FD1 is reduced. This reduction occurs because the charge is distributed across a larger capacitance, as governed by the equation V = Q/C, where V represents voltage, Q is charge, and C is capacitance. The relationship indicates that with a higher capacitance, the voltage for a given charge decrease.
Therefore, Shim’s teachings include a first time period in which the filler transistor is arranged to lower the voltage of the diffusion node from an initial value to a subsequent, reduced value. This aspect directly addresses the requirements of claim 2.
[Claim 3]
With respect to claim 3, Shim in view of Voss, provides additional teachings that are relevant to the claimed limitations. Specifically, Shim describes a first time period, defined as the interval between time T7 and T10, during which the floating diffusion node FD1 is electrically connected to both the second floating diffusion node FD2 and the third diffusion node FD3, which is coupled with the capacitor (CAP). This connection results in increase in overall capacitance associated with the floating diffusion node during this period.
As a consequence of the increased capacitance, the combined voltage of the first diffusion node FD1 becomes lower than the maximum voltage observed at the photodiode. This relationship is illustrated in Shim, Figure 5D, which represents the first time period, showing the voltage at the floating diffusion node is reduced below the maximum voltage at the zeroth node, corresponding to the cathode node of the photodiode.
[Claim 4]
Regarding claim 4, Shim in view of Voss, further details relevant to claim 4 of the image sensor device. In particular, Shim teaches that the sensor controller (Shim, Figure 1, 150) is configured to maintain the transmission gate transistor (Shim, Figure 2, TG) in a turn-off state during the first time period, which is defined as the interval between time T7 and T10, as depicted in Figure 4. Additionally, during second time period, which occurs between T0 and T1 and is also shown in Figure 4, the transmission gate transistor (TG) is maintained in the turn-off state for at least a portion of the interval. While the transmission gate transistor (TG) is not kept in the turn-off state throughout the entire duration of both the first and second time periods, it remains off for the entirety of the first time period and part of the second time period. Claim 4 does not require having the transmission gate to be low during the entirety of the first and the second time period.
Shim also discloses that the voltage at the zeroth node, corresponding to the cathode of the photodiode (PD), reaches its maximum value during conditions of lowest illumination, and, photodiode is at the highest voltage directly after reset and prior to receiving light since receiving light generates charge which would reduce the photodiode voltage (Shim, paragraph 0046).
[Claim 6]
Regarding claim 6, Shim in view of Voss, elaborates that the filler voltage (Shim, Figure 2, BST) is lower than the power supply voltage. Specifically, Shim states that, in one embodiment, the boosting signal BST may be a ground voltage (Shim, paragraph 0109). Since the ground voltage is lower than the power supply voltage (VPIX), this teaching fulfills the requirement that the filler voltage is less than the power supply voltage.
[Claim 7]
Regarding claim 7, Shim in view of Voss, teaches that the image sensor of claim 6, wherein the filler voltage is the ground voltage. Shim described that in an embodiment, the boosting signal BST is a ground voltage, (Shim, paragraph 0109).
[Claim 8]
Regarding claim 8, Shim in view of Voss, describes a sensor controller (Shim, Figure 1, 150) that is configured to operate the pixel in a low conversion gain mode and a high conversion gain mode. The high conversion gain mode is used during a low illumination environment (Shim, paragraph 0032).
Shim teaches a sensor configured to operate a pixel to capture an image of an object based on the intensity of light (Shim, paragraphs 0003, 0046). However, Shim does not teach taking image in a low illumination environment in a first period. Specification teaches a low illumination environment as an environment with illuminance lower than a reference illuminance (Specification, paragraph 0080). However, reference illuminance may be arbitrarily set higher than the environment of Shim. Therefore, the environment of Shim can be considered as a low illumination environment at least in the case where the reference illuminance is set higher than the environment of Shim.
Also see MPEP 2114(II): “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co.v.Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
[Claim 9]
Regarding claim 9, Shim in view of Voss, describes the operation of a sensor controller in a timing diagram (Shim, Figure 4), identifies the timing controller (Shim, Figure 2, 150), that manages the activation of various transistors during distinct time periods. According to Shim, the sensor controller (Shim, Figure 2, 150) is configured to turn on the selection transistor (Shim, Figure 4, SX) by a selection control signal SEL (Figure 4) during a third time period, which occurs between T1 and T3 as shown in Figure 4, following the conclusion of the second time period (between T0 and T1). Subsequently, the transmission gate transistor (Shim, Figure 4, TG) is activated by control signal TS (Figure 4) during a fourth time period, which spans from T3 to T6, immediately after the third time period. Finally, the sensor controller turns on the selection transistor (SX) control signal (SEL)
during a fifth time period, defined as the interval between T6 and T7, which follows the fourth time period. The sequence of operations, detailed in Shim’s disclosure (Figure 4, paragraphs 0065-0072), satisfies the requirements set forth in claim 9.
[Claim 12]
Regarding claim 12, Shim addresses the limitations outlined in claim 11 of the image sensor device and provide specific details relevant to claim 12. During the first time period, defined as the intervals between T7 and T10 in Figure 4, Shim teaches that the filler transistor is activated by the LRG control signal (LRS). When the LRG transistor is turned on, the floating diffusion node FD1 becomes connected to both a second diffusion node (FD2) and a third diffusion node (FD3+CAP). This configuration results in an increase in the overall capacitance of the floating diffusion node FD1.
As the capacitance associated with FD1 rises, the voltage at the floating diffusion node deceases. This relationship follows the equation V = Q/C, where V represents the voltage, Q is the charge and C is the capacitance. Therefore, the increase in capacitance directly leads to a reduction in voltage. Shim’s teachings demonstrates that when the filler transistor (LRG) is activated by the timing controller, the voltage of the floating diffusion node is effectively reduced.
In addition, Shim discloses that during a second time period defined in Figure 4 as the interval between T0 and T1, the reset transistor (RG) is configured to generate a reset voltage (VPIX) at the diffusion node FD1. This action is carried out in response to the reset signal (RS), ensuring the floating diffusion node FD1 receives the appropriate reset voltage during this period of operation.
Shim further teaches during a first time period (Figure 4, first time period is between T7
and before T10), and turn on the reset transistor (Figure2, RG) during a second time period (Figure 4, between T0 and T1), however, Shim does not teach the second time period to occur after the first time period.
Voss, teaches a system for capturing and embedding high resolution still images in a burst
mode. During burst mode, high resolution still images are captured sequentially and the single frame is repeated multiple as shown in (Voss, Figure 3A) where still image data frames, represented using reference numeral 314 (Voss, Figure 3A, paragraph 0049). Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Shim with the teaching of Voss to operate high resolution burst mode image capturing with the same camera.
In a burst mode, a first period T7 to T10 in N-1 frame would be followed by second period T0 to T1, in an N frame (Shim, Figure 4, repeated as taught by Voss).
[Claim 13]
With respect to claim 13, Shim in view of Voss, provides additional teachings that are relevant to the claimed limitations. Specifically, Shim describes a first time period, defined as the interval between time T7 and T10, during which the floating diffusion node FD1 is electrically connected to both the second diffusion node FD2 and the third diffusion node FD3, which is coupled with the capacitor (CAP). This connection results in increase in overall capacitance associated with the floating diffusion node during this period.
As a consequence of the increased capacitance, the combined voltage of the first diffusion node FD1 becomes lower than the maximum voltage observed at the photodiode. This relationship is illustrated in Figure 5D, which represents the first time period, showing the voltage at the floating diffusion node is reduced below the maximum voltage at the zeroth node, corresponding to the cathode node of the photodiode.
[Claim 14]
Regarding claim 14, Shim in view of Voss, further details a method of operating an image sensor device. In particular, Shim teaches that the sensor controller (Shim, Figure 1, 150) is configured the transmission gate transistor (Shim, Figure 2, TG) in a turn-off state during the first time period, which is defined as the interval between time T7 and T10, as depicted in Figure 4. Additionally, during second time period, which occurs between T0 and T1 and is also shown in Figure 4, the transmission gate transistor (TG) is maintained in the turn-off state for at least a portion of the interval. While the transmission gate transistor (TG) is not kept in the turn-off state throughout the entire duration of both the first and second time periods, it remains off for the entirety of the first time period and part of the second time period. Claim 14 does not require having the transmission gate to be low during the entirety of the first and the second time period.
Shim also discloses that the voltage at the zeroth node, corresponding to the cathode of the photodiode (PD), reaches its maximum value during conditions of lowest illumination, and, photodiode is at the highest voltage directly after reset and prior to receiving light since receiving light generates charge which would reduce the photodiode voltage (Shim, paragraph 0046).
[Claim 19]
Regarding claim 19, Shim in view of Voss, describes a sensor controller (Shim, 150) that is configured to operate the pixel in a low conversion gain mode and a high conversion gain mode. The high conversion gain mode is used during a low illumination environment (Shim, paragraph 0032).
Shim teaches a sensor configured to operate a pixel to capture an image of an object based on the intensity of light (Shim, paragraphs 0003, 0046). However, Shim does not teach taking image in a low illumination environment in a first period. Specification teaches a low illumination environment as an environment with illuminance lower than a reference illuminance (Specification, paragraph 0080). However, reference illuminance may be arbitrarily set higher than the environment of Shim. Therefore, the environment of Shim can be considered as a low illumination environment at least in the case where the reference illuminance is set higher than the environment of Shim.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2022/0337777 A1), in view of Ebihara US 2009/0303362 A1)
[Claim 16]
Regarding claim 16, Shim describes in paragraph 0101 and Figure 7A, a transmission gate transistor that is configured to be turned on in response to a transmission signal TS (Shim, Figure 4) having a logic high level. Additionally, Shim explains that the filler transistor (Shim, Figure 2, LRG) is operated by the LCG control signal LRS (Shim, Figure 2). Specifically, the LRS signal may transition from a first level (for example, a logic low level) to a second level (for example, a logic high level), thereby causing the filler transistor LRG (Shim, Figure 2, LRG) to turn on, as indicated in paragraph 0108. This means that the filler transistor is configured to be activated when the filler signal (Shim, Figure 4, LRS) as at a logic high level, and the voltage level of this logic high filler signal is at a certain level.
Shim further teaches the use of a row driver (Shim, Figure 1, 120), which generates control signals for managing the pixel array (Shim, Figure 1, 110). These control signals include transmission control signal TS, the reset control signal RS, and the low conversion gain (LCG) signal LRG, which is responsible for controlling the filler transistor as detailed in paragraph 0036.
However, Shim does not explicitly disclose that the voltage level of the transmission signal TS and the voltage level of the filler signal LRS, when both are a logic high level, are same.
Ebihara discloses a CMOS sensor 10 that includes a pixel array section 11 (Ebihara, Figure 1) and a pixel driver circuit (Ebihara, Figure 1, specifically, a row selection circuit referred as Vdec) and described as unit 12 in Figure 1. Ebihara further illustrates, in paragraph 0007, that the image sensor operates with a single power supply. As a result, it can be inferred that the row driver circuit 12 (Ebihara, Figure 1) generates control signals that share the same voltage level when at a logic high level.
Therefore, it would been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the timing sensor controller taught by Shim with the teaching of Ebihara. Specifically, by operating the image sensor with a single supply source, it is possible to maintain the same voltage level for both transmission and filler signals when at a logic high level. This enables the CMOS sensor, including both analog and logic circuit, to be fabricated using a CMOS manufacturing process and disposed on the same chip.
Allowable Subject Matter
Claim 5, 10, 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
[Claim 5, and 15]
Regarding claim 5 and 15, While Shim teaches a boost voltage which may be a ground voltage (Shim, paragraph 0109), the additional presence of capacitor (Shim, Figure 2, CAP) would prevent the second voltage from being decreased to the ground voltage when the filler transistor is turned on. Therefore, prior art does not teach or reasonably suggest that an image sensor where first voltage is decreased to a second voltage, that is at a ground voltage.
[Claim 10]
Shim does not teach a fourth time period where a trap site between the transmission gate transistor and the floating diffusion is fully filled with charges.
However, Hasegawa in (US 20120320245 A1) discloses a solid-state imaging device where trapped charges, specifically holes trapped near an interface under the transfer transistor are reduced.
With this configuration, the potential of the transfer signal is changed from the second potential (V2) to the third potential (V3), so that the holes trapped by traps near an interface under the gate of the transfer transistors are emitted. In the transfer operation, loss of the signal charges due to recoupling of the holes and the signal charges due to recoupling of the holes and the signal charges are reduced as described in (Hasegawa, paragraph 0008-0009).
Hasegawa implements a filler voltage similar to a bias voltage but that is applied at the gate of the transmission gate transistor. In the present application, the filler voltage is applied at floating diffusion node to control the electrons in the trap site. Also, the process of emitting holes cannot be related to a fourth time period as presented by the application.
Regarding claim 10, prior art does not teach or reasonably suggest that an image sensor according to claim 9, further comprising:
wherein, during the fourth time period, a trap site between the transmission gate transistor and the floating diffusion node is fully filled with charges.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following show additional prior art systems/methods for image sensors:
Ayers et al. US 2013/0020466 A1
Kato et al. US 2025/0344000 A1
Geurts et al. US 2019/0075259 A1
Prentice US 2012/0257071 A1
Choi US 11,736,833 B1
Yonggu et al. US 2025/0203246 A1
Johansson US 2025/0203245 A1
Hsieh et al. US 9,774,801 B2
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHEDI HASSAN whose telephone number is (571)272-7173. The examiner can normally be reached 8am-5pm.
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/MEHEDI HASSAN/Examiner, Art Unit 2637
/SINH TRAN/Supervisory Patent Examiner, Art Unit 2637