DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yeom US 20210351953 and in view of Kessner US 20160353204.
Regarding claim 1, Yeom teaches a bi-directional communication-based control apparatus (see figure 1) comprising:
a processor (battery management system BMS 1) that controls a target element according to a control signal applied to a communication bus (see para 0028, a modulating pulse signal (MPS) is transmitted to the BMS 1 from the ECU 2 through the single line 3, and the BMS 1 may control the relay according to the modulating pulse signal (MPS)) and causes state information of the target element according to a result of the control to be formed on the communication bus (see para 0028, the BMS 1 may apply a first voltage level to the single line 3 as feedback by a period that corresponds to feedback information), the control signal being input and a state signal for forming the state information being formed being output through two input/output pins provided in the processor (pins P1 and P4 of the BMS 1).
But Yeom fails to teach the control signal being input and a state signal for forming the state information being formed being output through a single bi-directional port provided in the processor; and an arbitrator that arbitrates first direction transmission of the control signal from the communication bus to the bi-directional port and second direction transmission of the state signal from the bi-directional port to the communication bus.
However, Kessner teaches a single bi-directional port and an arbitrator that arbitrates first direction transmission from the communication bus to the bi-directional port and second direction transmission from the bi-directional port to the communication bus (see figure 2, port 108 and switch 112, see para 0021, where the switch 112 is controlled by the CPU 102 to be in an open state. This configures the bi-directional port to behave as an input port, also see para 0022, when the switch 112 is closed and the bi-directional port is configured as an output port).
Therefore, it would have been obvious to modify the processor of Yeom and incorporate the arbitrator and the single bi-directional port for both input and output.
The motivation for doing so is to simplify the design of the communication system by reducing the number of ports as taught by Kessner (see para 0013).
Regarding claim 2, Yeom further teaches the processor receives the control signal, which is applied to the communication bus and has passed through the arbitrator during a first time period, through the bi-directional port and outputs the state signal to the arbitrator during a second time period following the first time period to form the state information on the communication bus (see figure 3, MPS signaling period PT1 and BMS response period PT3).
Regarding claim 3, Yeom further teaches as a predefined protocol is applied to the control signal and the state information, the control signal is formed as a pulse width modulation (PWM) signal during the first time period (see para 0045, the modulating pulse signal (MPS) with the frequency of F1 [Hz] and D1[%] is applied to the single line 3 in a MPS section PT1), and the state information is defined by a length of the second time period in which a signal level of the communication bus is maintained at a low level (see para 0047, For a BMS response period PT3, the DIO module 110 turns on the switch 5 for T1 [s] to pull down the voltage at the single line 3 to the ground (GND)).
Regarding claim 11, Yeom further teaches the processor is implemented as a battery management system (BMS) or as a controller included in the BMS (see figure 1, BMS 1),
the communication bus is connected to a vehicle controller that functions as a high-level controller of the processor (bus 3 connected to ECU 2), and
the control signal is applied from the vehicle controller to the communication bus, and the state information formed on the communication bus is transmitted to the vehicle controller (see para 0028, A modulating pulse signal (MPS) is transmitted to the BMS 1 from the ECU 2, also see para 0041, transmit a control result to the ECU 2 as a feedback).
Regarding claim 12, Yeom further teaches the bi-directional port functions as a timer input module (TIM) during a first time period in which the control signal is input (see figure 3, time period PT1) and functions as a data input/output (DIO) during a second time period in which the state signal is output (see figure 3, BMS response period PT3).
Regarding claim 13, Yeom further teaches the first time period is preset in the processor according to a predefined protocol, and the processor operates the bi-directional port as the TIM during the first time period (see para 0045, the modulating pulse signal (MPS) with the frequency of F1 [Hz] and D1[%] is applied to the single line 3 in a MPS section PT1), and operates the bi-directional port as the DIO during the second time period from a time point at which the first time period has elapsed (see figure 3, BMS response period PT3 after PT1 has elapsed).
Regarding claim 14, Yeom teaches a bi-directional communication interface (see figure 1) comprising:
a processor (battery management system BMS 1) that controls a target element according to a control signal applied to a communication bus (see para 0028, a modulating pulse signal (MPS) is transmitted to the BMS 1 from the ECU 2 through the single line 3, and the BMS 1 may control the relay according to the modulating pulse signal (MPS)) and causes state information of the target element according to a result of the control to be formed on the communication bus (see para 0028, the BMS 1 may apply a first voltage level to the single line 3 as feedback by a period that corresponds to feedback information), the control signal being input and a state signal being output through two input/output pins provided in the processor (pins P1 and P4 of the BMS 1).
But Yeom fails to teach the control signal being input and a state signal being output through a single bi-directional port; and an arbitrator that arbitrates first direction transmission of the control signal from the communication bus to the bi-directional port and second direction transmission of the state information from the bi-directional port to the communication bus.
However, Kessner teaches a single bi-directional port and an arbitrator that arbitrates first direction transmission from the communication bus to the bi-directional port and second direction transmission from the bi-directional port to the communication bus (see figure 2, port 108 and switch 112, see para 0021, where the switch 112 is controlled by the CPU 102 to be in an open state. This configures the bi-directional port to behave as an input port, also see para 0022, when the switch 112 is closed and the bi-directional port is configured as an output port).
Therefore, it would have been obvious to modify the processor of Yeom and incorporate the arbitrator and the single bi-directional port for both input and output.
The motivation for doing so is to simplify the design of the communication system by reducing the number of ports as taught by Kessner (see para 0013).
Regarding claim 15, Yeom teaches a bi-directional communication-based control system (see figure 1) comprising:
a first processor (ECU 2) configured to apply to a communication bus a control signal for controlling a target element (see para 0028, a modulating pulse signal (MPS) is transmitted to the BMS 1 from the ECU 2 through the single line 3) and receives state information of the target element formed on the communication bus (see para 0041, transmit a control result to the ECU 2 as a feedback);
a second processor (battery management system BMS 1) configured to control the target element according to the control signal applied to the communication bus (see para 0028, a modulating pulse signal (MPS) is transmitted to the BMS 1 from the ECU 2 through the single line 3, and the BMS 1 may control the relay according to the modulating pulse signal (MPS)) and cause state information of the target element according to a result of the control to be formed on the communication bus (see para 0028, the BMS 1 may apply a first voltage level to the single line 3 as feedback by a period that corresponds to feedback information); and inputting the control signal and outputting a state signal for forming the state information is performed through two input/output pins provided in the processor (pins P1 and P4 of the BMS 1).
But Yeom fails to teach inputting the control signal and outputting a state signal for forming the state information is performed through a single bi-directional port provided in the processor and an arbitrator configured to arbitrate first direction transmission of the control signal from the communication bus to the bi-directional port and second direction transmission of the state signal from the bi-directional port to the communication bus,
However, Kessner teaches a single bi-directional port and an arbitrator that arbitrates first direction transmission from the communication bus to the bi-directional port and second direction transmission from the bi-directional port to the communication bus (see figure 2, port 108 and switch 112, see para 0021, where the switch 112 is controlled by the CPU 102 to be in an open state. This configures the bi-directional port to behave as an input port, also see para 0022, when the switch 112 is closed and the bi-directional port is configured as an output port).
Therefore, it would have been obvious to modify the processor of Yeom and incorporate the arbitrator and the single bi-directional port for both input and output.
The motivation for doing so is to simplify the design of the communication system by reducing the number of ports as taught by Kessner (see para 0013).
Regarding claims 16-17, please refer to the rejection of claims 2-3 since the claimed subject matter is substantially similar.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yeom and Kessner as applied to claims above, and further in view of Puente et al US 20210135326.
Regarding claim 4, the combination of Yeom and Kessner teaches all the features with respect to claim 3 as outlined above.
Yeom further teaches using transistor switch as the arbitrator (see para 0016, other types of switches such as solid-state relays or transistor switches could also be used).
But the combination of Yeom and Kessner fails to teach the arbitrator includes a first transistor that arbitrates the first direction transmission of the control signal, and a second transistor that arbitrates the second direction transmission of the state signal.
However, Puente teaches an input/output arbitrator includes a first transistor switch that arbitrates the first direction transmission, and a second transistor switch that arbitrates the second direction transmission (see figures 4A and 4B, switch 312 for input direction and switch 314 for output direction).
Therefore, it would have been obvious to modify the transistor switch of Kessner and further incorporate two transistors controlling both transmission direction.
The motivation for doing so is to provide better signal isolation between the input/output circuitry as taught by Puente (see the abstract and para 0002).
Allowable Subject Matter
Claims 5-10 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shin et al US 20210276532 discloses power relay assembly and control method of the power relay assembly
Park et al US 20060197505 discloses measuring voltage of a switching section of a battery pack and control the switching section depending of the measured voltage
Liron US 20020138684 discloses a routing switch with variable input/output architecture
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/PHONG H DANG/Primary Examiner, Art Unit 2184