Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,125,121. Although the claims at issue are not identical, they are not patentably distinct from each other because all the instant claim limitations are essentially covered by the U.S. Patent.
Instant application 18/883,068
1-20
U.S. Patent No. 12,125,121
1-20
Instant application 18/883,068
U.S. Patent No. 12,125,121
1. An apparatus comprising: a processor comprising tessellation circuitry to:
redistribute, using redistribution circuitry communicably coupled to geometry fixed-function units comprising front ends and back ends, patches among the back ends using a redistribution bus coupling the front ends and the back ends, wherein the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation;
receive, by the redistribution circuitry from the front ends in parallel, patch transmissions marked for distribution and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the redistribution circuitry, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
1. An apparatus comprising: a processor to: provide parallel interconnected geometry fixed-function units with separate front ends and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus provided between the front ends and the back ends; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution central engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
2. The apparatus of claim 1, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
2. The apparatus of claim 1, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
3. The apparatus of claim 2, wherein the synchronization barrier packet comprises an identifier (ID) of the geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
3. The apparatus of claim 2, wherein the synchronization barrier packet comprises an identifier (ID) of the parallel interconnected geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
4. The apparatus of claim 2, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to tessellation work stored in the entry being associated with the synchronization barrier packet.
4. The apparatus of claim 2, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to the tessellation work stored in the entry being associated with the synchronization barrier packet.
5. The apparatus of claim 2, wherein the front ends to push the tessellation work marked for local processing to the intermediate storage.
5. The apparatus of claim 2, wherein the front ends to push the tessellation work marked for local processing to the intermediate storage.
6. The apparatus of claim 1, wherein each of the geometry fixed-function units comprises a corresponding intermediate storage.
6. The apparatus of claim 1, wherein each of the parallel interconnected geometry fixed-function units comprises a corresponding intermediate storage.
7. The apparatus of claim 6, wherein each of the geometry fixed-function units comprises selection circuitry to switch a control signal that indicates to each of the corresponding back ends to process tessellation work from either the intermediate storage or the redistribution bus.
7. The apparatus of claim 6, wherein each of the parallel interconnected geometry fixed-function units comprises selection circuitry to switch a control signal that indicates to each of corresponding ones of the back ends to process the tessellation work from either the intermediate storage or the redistribution bus.
8. The apparatus of claim 1, wherein the redistribution circuitry to queue the patch transmissions marked for distribution that are received from the front ends and to process in a sequential order the patch transmissions that are queued, the sequential order defined by a determined sequence of the geometry fixed-function units.
8. The apparatus of claim 1, wherein the tessellation redistribution central engine to queue the patch transmissions marked for distribution that are received from the front ends and to process in a sequential order the patch transmissions that are queued, the sequential order defined by a determined sequence of the parallel interconnected geometry fixed-function units.
9. The apparatus of claim 1, wherein the processor comprises a graphics processing unit (GPU).
9. The apparatus of claim 1, wherein the processor comprises a graphics processing unit (GPU).
10. The apparatus of claim 1, wherein the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.
10. The apparatus of claim 1, wherein the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.
11. A method comprising:
redistribute, using redistribution circuitry communicably coupled to geometry fixed-function units comprising front ends and back ends, patches among the back ends using a redistribution bus coupling the front ends and the back ends, wherein the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation;
receive, by the redistribution circuitry from the front ends in parallel, patch transmissions marked for distribution and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the redistribution circuitry, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
11. A method comprising: providing, by a processor, parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation; providing a tessellation redistribution central engine to redistribute patches among the back ends of the parallel interconnected geometry fixed-function units using a redistribution bus provided between the front ends and the back ends; receiving, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution central engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcasting, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
12. The method of claim 11, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
12. The method of claim 11, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
13. The method of claim 12, wherein the synchronization barrier packet comprises an identifier (ID) of the geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
13. The method of claim 12, wherein the synchronization barrier packet comprises an identifier (ID) of the parallel interconnected geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
14. The method of claim 12, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to tessellation work stored in the entry being associated with the synchronization barrier packet.
14. The method of claim 12, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to the tessellation work stored in the entry being associated with the synchronization barrier packet.
15. The method of claim 11, wherein each of the parallel interconnected geometry fixed-function units comprises a corresponding intermediate storage, and wherein each of the geometry fixed-function units comprises selection circuitry to switch a control signal that indicates to each of the corresponding back ends to process tessellation work from either the intermediate storage or the redistribution bus.
15. The method of claim 11, wherein each of the parallel interconnected geometry fixed-function units comprises a corresponding intermediate storage, and wherein each of the parallel interconnected geometry fixed-function units comprises selection circuitry to switch a control signal that indicates to each of corresponding ones of the back ends to process tessellation work from either the intermediate storage or the redistribution bus.
16. The method of claim 11, further comprising: queuing, by the redistribution circuitry, the patch transmissions marked for distribution that are received from the front ends; and processing, by the redistribution circuitry in a sequential order, the patch transmissions that are queued, the sequential order defined by a determined sequence of the geometry fixed-function units.
16. The method of claim 11, further comprising: queuing, by the tessellation redistribution central engine, the patch transmissions marked for distribution that are received from the front ends; and processing, by the tessellation redistribution central engine in a sequential order, the patch transmissions that are queued, the sequential order defined by a determined sequence of the parallel interconnected geometry fixed-function units.
17. A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to:
redistribute, using redistribution circuitry communicably coupled to geometry fixed-function units comprising front ends and back ends, patches among the back ends using a redistribution bus coupling the front ends and the back ends, wherein the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation;
receive, by the redistribution circuitry from the front ends in parallel, patch transmissions marked for distribution and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the redistribution circuitry, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
17. A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to: provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front ends and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends of the parallel interconnected geometry fixed-function units using a redistribution bus provided between the front ends and the back ends; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution central engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
18. The non-transitory computer-readable medium of claim 17, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
18. The non-transitory computer-readable medium of claim 17, wherein the synchronization barrier packet to cause the one of the back ends corresponding to the synchronization barrier packet to read out the tessellation work from intermediate storage corresponding to the one of the back ends, and wherein the one of the back ends to perform the patch tessellation on the tessellation work read out from the intermediate storage.
19. The non-transitory computer-readable medium of claim 18, wherein the synchronization barrier packet comprises an identifier (ID) of the geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
19. The non-transitory computer-readable medium of claim 18, wherein the synchronization barrier packet comprises an identifier (ID) of the parallel interconnected geometry fixed-function unit originating the synchronization barrier packet, and wherein the back ends utilize the ID to determine whether to process the synchronization barrier packet or to drop the synchronization barrier packet.
20. The non-transitory computer-readable medium of claim 18, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to tessellation work stored in the entry being associated with the synchronization barrier packet.
20. The non-transitory computer-readable medium of claim 18, wherein the intermediate storage is a first in first out (FIFO) queue, and wherein each entry of the FIFO queue comprising a synchronization barrier bit that is set responsive to the tessellation work stored in the entry being associated with the synchronization barrier packet.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11 and 17 recite “using redistribution circuitry communicably coupled to geometry fixed-function units comprising front ends and back ends, patches among the back ends using a redistribution bus coupling the front ends and the back ends”. It is unclear how the patches are related to the geometry fixed-function units and the redistribution bus. In addition, it is unclear what operation is being performed with respect to the patches, whether the redistribution circuitry performs the recited function.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ZHAI whose telephone number is (571)270-3740. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571) 272 - 7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE ZHAI/ Primary Examiner, Art Unit 2611
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