DETAILED ACTION
Applicant’s amendment, filed 07/13/2026 for application 18/883,132, has been received
and entered into record. Claim 17 has been cancelled. Claims 1, 2, 7, 15, 16, 18, 19, and 20
have been amended. Therefore, Claims 1-16 and 18-20 are presented for examination. The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 7, 8, 11, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 2022/0197541 A1) in view of CHAIKEN et al. (US 2020/0159302 A1), KIM et al. (US 2017/0104406 A1), and LI et al. (CN 114840456 A), US 2023/0393959 A1 being interpreted as a translation of CN 114840456 A.
Regarding Claim 1, OH discloses a method of operating a storage device (storage device 200, FIG. 1, [0002]) which communicates with a host device (storage device 200 communicates with host 100, FIG. 1, [0041]), the method comprising:
receiving a first power supply voltage and a second power supply voltage from the host device (storage device 200 receives various voltages 3.5V, 5V and 12V from host device 100, FIG. 4, [0069]);
executing, by a micro controller unit (MCU) of the storage device, a first power-on sequence for sequentially generating a plurality of internal voltages of the storage device (storage controller includes a pin manager circuit [0008]; pin manager 360 contains turn-on voltage generator 380 that provides a plurality of turn-on voltages TON1, TON2, …, to sequentially turn on selection transistors 531-53q, which are internal to storage device 200 (Fig. 13A, [0123]) based on the second power supply voltage (storage controller 300 powered by voltage V0P2, FIG. 1, [0046]).
OH does not disclose detecting, by the MCU, a first power failure corresponding to the first power-on sequence; and performing, by the MCU, a second power-on sequence for sequentially generating the plurality of internal voltages in response to detecting the first power failure, wherein the second power-on sequence is different from the first power-on sequence, wherein the storage device includes: a storage controller configured to perform in-band communication with a processor of the host device, wherein the MCU is separate from the storage controller.
However, in the analogous art of power error detection during start-up, CHAIKEN teaches detecting, by the MCU (embedded controller EC 150, FIG. 1), a first power failure corresponding to the first power-on sequence (EC 150 detects power failure during IHS boot process, [0058]);
and performing, by the MCU, a power-on sequence for sequentially generating the plurality of internal voltages in response to detecting the first power failure (embedded controller EC 150 power cycles the system to restart the reboot after detecting power failure during IHS boot process (FIG. 3 Steps 220-250, [0052]), the boot process consisting of a power sequence for sequentially enabling internal IHS components with an operating voltage, [0051]).
It would have been obvious to one of ordinary skill, having the teachings of OH and CHAIKEN before him before the effective filing date of the claimed invention, to incorporate the method of detecting a power failure and performing a second power-on sequence as taught by CHAIKEN into the method of operating a storage device which communicates with a host device as taught by OH in order to incorporate a method of detecting and recovering from a power failure without suffering information loss (CHAIKEN, [0007]).
OH in view of CHAIKEN does not explicitly teach wherein the second power-on sequence is different from the first power-on sequence, wherein the storage device includes: a storage controller configured to perform in-band communication with a processor of the host device, wherein the MCU is separate from the storage controller.
However, in the analogous art of power up circuits, KIM teaches wherein a second power-on sequence is different from the first power-on sequence [a power-up sequence of first to third internal source voltages PWR1 to PWR3 may be generated in a different sequence each time a power-up operation is performed, par. 72].
It would have been obvious to one of ordinary skill in the art, having the teachings of OH, CHAIKEN, and KIM before him before the effective filling date of the claimed invention, to incorporate a second power-on sequence different from a first power-on sequence as taught by KIM into the method as taught by OH in view of CHAIKEN in order to incorporate generating internal source voltages in order for a peak current of a power-up current to be equally distributed [KIM par. 5].
OH in view of CHAIKEN and KIM do not explicitly teach wherein the storage device includes: a storage controller configured to perform in-band communication with a processor of the host device, wherein the MCU is separate from the storage controller.
However, in the analogous art of power management, LI teaches wherein the storage device includes: a storage controller [storage apparatus 420 contains main controller 423 (i.e. storage controller), FIG. 4] configured to perform in-band communication with a processor of the host device [main controller 423 carries out in-band communication with CPU 412 inside host 410 (i.e. host device), FIG. 4, par. 89].
wherein an MCU is separate from the storage controller [MCU 421 (i.e. an MCU) and main controller 423 (i.e. storage controller) are separate components in storage apparatus 420, FIG. 4].
It would have been obvious to one of ordinary skill, having the teachings of OH, CHAIKEN, KIM, and LI before him before the effective filing date of the claimed invention, to incorporate the storage controller separate from the MCU and carrying out a method of out-of-band communication between a host and storage device taught by LI into the method as taught by OH in view of CHAIKEN and KIM in order to offer an alternate communication option between a host and storage device in case of an abnormality in the storage device (US 2023/0393959 A1 [0012]).
Regarding Claim 2, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
LI further teaches wherein the MCU is configured to perform out-of-band communication with a baseboard management controller (BMC) of the host device. (baseboard management controller BMC 411 in host 410 communicates with micro control unit 411 of storage apparatus 420 via an out-of-band function, FIG. 4, US 2023/0393959 A1 [0079]).
Regarding Claim 6, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
CHAIKEN further teaches wherein the MCU is configured to detect the first power failure, based on failing in the execution of the first power-on sequence or based on detecting an abnormal power-off event through a monitoring operation of the plurality of internal voltages generated by the first power-on sequence (embedded controller EC 150 detects failure of power-on sequence consisting of Information Handling System (IHS) 100 components powering on, FIG. 1, FIG. 3 Step 230, [0051-0052]).
Regarding Claim 7, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
CHAIKEN further teaches determining, by the MCU, whether a second power failure of at least one or more of the plurality of internal voltages generated by the second power-on sequence occurs (embedded controller EC 150 detects operating voltage sufficiency (failure) through detecting failure of IHS 100 components powering on in a power-on sequence; subsequent power sequencing procedures following a reset similarly checks for no-power boot situations, FIG. 1, FIG. 3, Steps 220-230, [0051-0052]).
Regarding Claim 8, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 7 as applied above.
OH further teaches wherein the storage device includes: a plurality of power blocks configured to generate the plurality of internal voltages (selection transistors 531-53q coupled with pins on nonvolatile memory devices 400a-400k which sequentially generate merged signal current RnBx, FIG. 14A, [0140, 0146]);
and a recovery block configured to replace a failed power block among the plurality of power blocks (if one of the pins REP or REBP is unusable in the current mode, then the mode is changed and the remaining pin is used in the new mode; pin REP configured to replace pin REBP using a CMOS mode, FIG. 18, [0174, 0175, 0180]),
and the method further comprises: determining, by the MCU, whether the recovery block configured to replace the failed power block causing the second power failure from among the plurality of power blocks exists, in response to determining that the second power failure occurs (storage controller 300 determines whether the operation mode of a leakage pin (defective, failed power block) is replaceable in response to detecting a pin leakage, FIG. 16 Steps S110-S130, [0173-0175]);
replacing, by the MCU, the failed power block with the recovery block in response to determining that the recovery block exists ((if one of the pins REP or REBP is unusable in the current mode, then the mode is changed and the remaining pin is used in the new mode; pin REP configured to replace pin REBP using a CMOS mode, FIG. 18, [174, 175]), changes initial mode of REP pin to replace REPB using a CMOS mode, FIG. 16, [0048, 0180]);
and performing, by the MCU, a third power-on sequence (storage controller 300 performs a power-on sequence after changing the initial mode for the pin that replaces the defective pin, Step 160, [0176]) for sequentially generating the plurality of internal voltages by using the replaced recovery block (power-up S160 consists of sequentially turning on transistors ([0123]), selection transistors sequentially generate merged signal current RnBx, FIG. 14A, [0146]).
Regarding Claim 11, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 7 as applied above.
OH further teaches wherein the storage device includes: a plurality of power blocks configured to generate the plurality of internal voltages (selection transistors 531-53q coupled with pins on nonvolatile memory devices 400a-400k sequentially generate merged signal current RnBx, FIG. 14A) [0140, 0146]);
and a recovery block configured to replace a failed power block among the plurality of power blocks (if one of the pins REP or REBP is unusable in the current mode, then the mode is changed and the remaining pin is used in the new mode; pin REP configured to replace pin REBP using a CMOS mode, FIG. 18, [0174, 0175, 0180]),
and the method further comprises: determining, by the MCU (storage controller 300, FIG. 4), whether the recovery block configured to replace the failed power block causing the second power failure from among the plurality of power blocks exists, in response to determining that the second power failure occurs (storage controller 300 determines whether the operation mode of a leakage pin (defective, failed power block) is replaceable in response to detecting a pin leakage, FIG. 16 Steps S110-S130, [0173-0175]);
determining that the recovery block does not exist, storing the information in the MCU (storage controller 300 determines if there are available affordable pins to replace defective pins [0048], information about defective pins (leakage pins) stored in register 370 [0165]; register 370 is contained in pin manager 360 which is stored in storage controller 300 (FIG. 3), storage controller processor is configured to perform operations performed by the pin manager, [0055])
LI further teaches providing, by the MCU, an error message to the host device, error message containing error information stored in the MCU (storage apparatus 420 provides information surrounding an error (before and after an error) to the baseboard management controller 411 of host device 410 in an out-of-band management mode [US 2023/0393959 A1 0089]; out-of-band management carried out between micro control unit 421 of storage apparatus 420 and baseboard management controller 411 of host device 410, US 2023/0393959 A1 [0079]; MCU 421 stores information surrounding an error in persistent memory 422 of MCU).
Regarding Claim 12, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 11 as applied above.
LI further teaches wherein the MCU is configured to: operate based on the second power supply voltage while providing the error message to the host device (micro control unit 421 operating using power supplied by second power supply unit (PSU2) 442 [US 2023/0393959 A1 0081], storage apparatus 420 provides information surrounding an error (before and after an error) to the baseboard management controller 411 of host device 410 in an out-of-band management mode (US 2023/0393959 A1 [0089]); out-of-band management carried out between micro control unit 421 of storage apparatus 420 and baseboard management controller 411 of host device 410, US 2023/0393959 A1 [0079]).
and provide the error message of a BMC of the host device by using out-of-band communication (storage apparatus 420 provides information surrounding an error (before and after an error) to the baseboard management controller 411 of host device 410 in an out-of-band management mode [US 2023/0393959 A1 0089]; out-of-band management carried out between micro control unit 421 of storage apparatus 420 and baseboard management controller 411 of host device 410, US 2023/0393959 A1 [0079]).
Regarding Claim 13, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
OH further discloses wherein the first power supply voltage is higher than the second power supply voltage (voltage 12V supplied to the storage device 200 is higher than voltage 3.3V supplied to the storage device 200, FIG. 4, [0069]).
Claims 3, 4, 5, 9, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of CHAIKEN, KIM, and LI as applied to Claims 1 and 8 above, and further in view of BISBEE (US 7,694,163 B1).
Regarding Claim 3, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
CHAIKEN further teaches wherein the executing of the first power-on sequence for sequentially generating the plurality of internal voltages of the storage device based on the second power supply voltage by the MCU of the storage device includes: activating the MCU (embedded controller EC 150, FIG. 1) based on the second power supply voltage (operating voltage supplied by the power management and logic circuitry 155 through one of the power rails, FIG. 1, [0039-0040]);
determining, by the activated MCU, whether the first power supply voltage is provided to a power supply circuit of the storage device (embedded controller EC 150 determines whether platform controller hub PCH 120 is supplied with power from standby power by continuing the power-on sequence only after the PCH is turned on and begins to supply sleep state exit signals to EC 150, FIG. 1, [0040]).
OH in view of CHAIKEN, KIM, and LI does not teach loading, by the activated MCU, a sequence instruction defining an enablement order of a plurality of power blocks of the power supply circuit in response to determining that the first power supply voltage is provided to the power supply circuit; executing, by the activated MCU, the first power-on sequence for sequentially generating the plurality of internal voltages depending on the enablement order, based on the loaded sequence instruction; and updating, by the activated MCU, sequence history information based on executing the first power-on sequence.
However, in the analogous art of power management, BISBEE teaches loading, by the activated MCU (programmable control and monitoring chip CMD 44, FIG. 3), a sequence instruction defining an enablement order of a plurality of power blocks of the power supply circuit in response to determining that the first power supply voltage is provided to the power supply circuit (CMD 44 is programmable, program to sequentially turn on point-of-load (POL) convertors 46 1-46 n stored in CMD memory (Column 4 Lines 18-27), CMD generates enable signal EN as part of the power-on sequence (Column 5 Lines 35-42), power-on sequence starts in response to deriving power from input voltage supply, Column 5 Lines 59-66);
executing, by the activated MCU, the first power-on sequence for sequentially generating the plurality of internal voltages depending on the enablement order, based on the loaded sequence instruction (CMD 44 performs the power-up sequencing function program (sequence function program stored in CMD memory, Column 4 Lines 18-27), sequentially enables POL convertors 46 1-46 n that produce internal voltages via enable line EN, Column 5 Lines 35-42).
It would have been obvious to one of ordinary skill, having the teachings of OH, CHAIKEN, KIM, LI, and BISBEE before him before the effective filing date of the claimed invention, to incorporate the method of loading and executing a power-up sequence instruction as taught by BISBEE into the method of operating a storage device as taught by OH in view of CHAIKEN, KIM, and LI in order to ensure proper supply voltage is applied (BISBEE, Column 1 Lines 34-40).
Regarding Claim 4, OH in view of CHAIKEN, KIM, LI, and BISBEE teaches the method of Claim 3 as applied above.
CHAIKEN further teaches wherein the performing of the second power-on sequence for sequentially generating the plurality of internal voltages in response to detecting the first power failure by the MCU includes: loading, by the activated MCU, the sequence instruction in response to detecting the first power failure (embedded controller EC 150 power cycles the system after resetting the real-time clock RTC 160 in response to detecting a no-power failure (FIG. 3 Steps 220-250, [0052]), a boot process consisting of embedded controller EC 150 executing program instructions to initiate boot process of Information Handling System IHS 100, [0038]);
and executing, by the activated MCU, the second power-on sequence (embedded controller EC 150 power cycles the system to restart the reboot after detecting power failure during IHS boot process (FIG. 3 Steps 220-250, [0052]), the boot process consisting of a power sequence for sequentially enabling internal IHS components with an operating voltage, [0051]).
BISBEE further teaches executing, by the activated MCU, power-on sequence for sequentially generating the plurality of internal voltages based on the loaded sequence instruction (programmable control and monitoring chip CMD 44 performs the power-up sequencing function program (sequence function program stored in CMD, Column 4 Lines 18-27) for sequentially enabling convertors 46 1-46 n that produce internal voltages via enable line EN, Column 5 Lines 35-42);
and further updating, by the activated MCU, the sequence history information based on executing the second power-on sequence (programmable control and monitoring chip CMD 44 logs power down conditions (Column 7 Lines 18-21), a power down is a power-off after the failure of a power-on sequence, Column 4 Lines 28-44).
Regarding Claim 5, OH in view of CHAIKEN, KIM, LI, and BISBEE teaches the method of Claim 3 as applied above.
BISBEE further teaches wherein the MCU includes: a power sequence manager configured to execute the first power-on sequence (program stored in programmable and monitoring Chip CMD 44 performs the method of executing power-on sequence, FIG. 3, Column 4 Lines 18-27);
a power sequence memory configured to store the sequence instruction (CMD 44 contains memory 48 storing sequencing function performed by CMD, FIG. 3, Column 4 Lines 18-27);
and a log register configured to store the sequence history information (CMD 44 contains non-volatile flash memory for data logging, Column 4 Lines 52-54).
Regarding Claim 9, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 8 as applied above.
OH further teaches, further comprising: updating, by the MCU, a sequence instruction corresponding to the second power-on sequence based on executing the third power-on sequence (processor 310 of storage controller 300 changes initial mode of a nonvolatile memory device before executing a power-up sequence (FIG. 16 Step S160), processor functions (inclusive of the power-up sequence) configured to be executable software (instructions), FIG. 3, [0055]).
BISBEE further teaches and updating, by the MCU (programmable control and monitoring chip CMD 44, FIG. 3), sequence history information based on executing the third second power-on sequence (CMD 44 logs power down conditions (Column 7 Lines 18-21), a power down is a power-off after the failure of a power-on sequence, Column 4 Lines 28-44).
Regarding Claim 10, OH in view of CHAIKEN, KIM, LI, and BISBEE teaches the method of Claim 9 as applied above.
OH further teaches wherein the updated sequence instruction indicates the recovery block instead of the failed power block (power-up sequence occurs after changing the initial mode of the replaced pin (FIG. 16 Step S160, [0176]), processor functions (inclusive of the power-up sequence) configured to be executable software (instructions) FIG. 3, [0055]).
Regarding Claim 15, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
BISBEE further teaches wherein the MCU (programmable control and monitoring chip CMD 44, FIG. 3) is configured to perform a power-off sequence for deactivating the plurality of internal voltages generated by the first power-on sequence or the second power-on sequence (CMD 44 executes power-off sequence to deactivate previously sequentially powered POL convertors 46 1-46 n generating internal voltages in a first power-up sequence, FIG. 3, Column 4 Lines 37-44).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of CHAIKEN, KIM, and LI as applied to Claim 1 above, and further in view of CHANG (US 2020/0192418 A1).
Regarding Claim 14, OH in view of CHAIKEN, KIM, and LI teaches the method of Claim 1 as applied above.
OH in view of CHAIKEN, KIM, and LI does not explicitly teach wherein the MCU is configured to: receive an internal voltage dedicated for the MCU from among the plurality of internal voltages generated by the first power-on sequence or the second power-on sequence; and operate based on both the second power supply voltage and the internal voltage dedicated for the MCU.
However, in the analogous art of power supply means and management, CHANG teaches wherein the MCU (functional unit 151, FIG. 1) is configured to: receive an internal voltage dedicated for the MCU from among the plurality of internal voltages generated by the first power-on sequence or the second power-on sequence (functional unit 151 is supplied with internal voltage VDDI (FIG. 1, [0031]); VDDI is generated by power-on after receiving power-on signal SPO, [0027]);
and operate based on both the second power supply voltage and the internal voltage dedicated for the MCU (functional unit 151 is enabled and is supplied with both internal supply voltage VDDI and supply voltage VDD. Functional unit 151 then starts a corresponding operation, FIG. 1 [0031]).
It would have been obvious to one of ordinary skill, having the teachings of OH, CHAIKEN, KIM , LI, and CHANG before him before the effective filing date of the claimed invention, to incorporate the method of a unit using an internal and an external power supply as taught by CHANG into the method of operating a storage device as taught by OH in view of CHAIKEN, KIM, and LI in order to enable a dependent unit without causing a power surge on the main power supply (CHANG, [0004, 0038]).
Claims 16, 18, and 19 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of LI, BISBEE, CHAIKEN, and KIM.
Regarding Claim 16, OH discloses a storage device comprising: a non-volatile memory device (storage device 200 comprises non-volatile memory devices NVM1-NVMk, FIG. 4, [0039]);
and a micro controller (storage controller 300, FIG. 4) configured to receive a second power supply voltage lower than the first power supply voltage from the host device and to execute a first power-on sequence based on the second power supply voltage (storage controller 300 configured to receive voltage 3.3V lower than voltage 12V from host device ([0069]) and executes a power-on sequence of sequentially turning on selection transistors 531-53q [0123] based on power received from host device 100, [0069]).
OH does not explicitly disclose a storage device comprising a storage controller; a power supply circuit including a plurality of power blocks configured to generate a plurality of internal voltages to be provided to the storage controller and the non-volatile memory device based on a first power supply voltage received from a host device; wherein the micro controller is separate from the storage controller, wherein the power supply circuit is configured to sequentially activate the plurality of power blocks depending on an enablement order defined in the first power-on sequence under control of the micro controller, wherein the micro controller is configured to: detect a first power failure, based on failing in the execution of the first power-on sequence or based on detecting an abnormal power-off event in the plurality of internal voltages generated by the plurality of power blocks activated by the first power-on sequence; and execute a second power-on sequence defining the enablement order in response to detecting the first power failure, wherein the second power-on sequence is different from the first power-on sequence.
However, in the analogous art of power management, LI teaches a storage device comprising a storage controller [main controller 423, FIG. 4]
wherein a micro controller is separate from the storage controller [MCU 421 (i.e. a micro controller) and main controller 423 (i.e. storage controller) are separate components in storage apparatus 420, FIG. 4].
It would have been obvious to one of ordinary skill, having the teachings of OH and LI before him before the effective filing date of the claimed invention, to incorporate a micro controller separate from a storage controller as taught by LI into the method as disclosed by OH in order to offer an alternate communication option between a host and storage device in case of an abnormality in the storage device (US 2023/0393959 A1 [0012, 0089]).
OH in view of LI does not explicitly teach a power supply circuit including a plurality of power blocks configured to generate a plurality of internal voltages to be provided to the storage controller and the non-volatile memory device based on a first power supply voltage received from a host device; wherein the power supply circuit is configured to sequentially activate the plurality of power blocks depending on an enablement order defined in the first power-on sequence under control of the micro controller, wherein the micro controller is configured to: detect a first power failure, based on failing in the execution of the first power-on sequence or based on detecting an abnormal power-off event in the plurality of internal voltages generated by the plurality of power blocks activated by the first power-on sequence; and execute a second power-on sequence defining the enablement order in response to detecting the first power failure, wherein the second power-on sequence is different from the first power-on sequence.
However, in the analogous art of power management, BISBEE teaches a power supply circuit (programmable control and monitoring chip CMD 44, FIG. 3) including a plurality of power blocks configured to generate a plurality of internal voltages to be provided to the storage controller and the non-volatile memory device based on a first power supply voltage received from a host device (CMD 44 includes point-of-load (POL) convertors 46 1-46 n that are configured to produce voltages for devices 42 1-42 n (Column 4 Lines 15-22) based on an input voltage supply Vin (Column 5 Lines 61-62);
wherein the power supply circuit is configured to sequentially activate the plurality of power blocks depending on an enablement order defined in the first power-on sequence under control of the micro controller (CMD 44 performs the power-up sequencing function program (sequence function program stored in CMD, Column 4 Lines 18-27), sequentially enables convertors 46 1-46 n that produce internal voltages via enable line EN, Column 5 Lines 35-42).
It would have been obvious to one of ordinary skill, having the teachings of OH, LI, and BISBEE before him before the effective filing date of the claimed invention, to incorporate a power supply circuit containing power blocks that generate internal voltages as part of a power-of sequence as taught by BISBEE into the storage system as taught by OH in view of LI in order to incorporate a circuit capable of generating multiple voltages for a variety of components in a system (BISBEE, Column 1 Line 64 through Column 2 Line 5).
OH in view of LI and BISBEE does not explicitly teach wherein the micro controller is configured to: detect a first power failure, based on failing in the execution of the first power-on sequence or based on detecting an abnormal power-off event in the plurality of internal voltages generated by the plurality of power blocks activated by the first power-on sequence; and execute a second power-on sequence defining the enablement order in response to detecting the first power failure, wherein the second power-on sequence is different from the first power-on sequence.
However, in the analogous art of power error detection during start-up, CHAIKEN teaches wherein the micro controller is configured to: detect a first power failure, based on failing in the execution of the first power-on sequence or based on detecting an abnormal power-off event in the plurality of internal voltages generated by the plurality of power blocks activated by the first power-on sequence [embedded controller EC 150 detects power failure during IHS boot process, par. 58];
and execute a second power-on sequence defining the enablement order in response to detecting the first power failure (embedded controller EC 150 power cycles the system to restart the reboot after detecting power failure during IHS boot process (FIG. 3 Steps 220-250, [0052]), the boot process consisting of a power sequence for sequentially enabling internal IHS components with an operating voltage, [0051]).
It would have been obvious to one of ordinary skill, having the teachings of OH, LI, BISBEE and CHAIKEN before him before the effective filing date of the claimed invention, to incorporate the method of detecting a power failure and performing a second power-on sequence as taught by CHAIKEN into the method of operating a storage device which communicates with a host device as taught by OH in view of LI and BISBEE order to incorporate detecting and recovering from a power failure without suffering information loss (CHAIKEN, [0007]).
OH in view of LI, BISBEE, and CHAIKEN does not explicitly teach wherein the second power-on sequence is different from the first power-on sequence.
However, in the analogous art of power up circuits, KIM teaches wherein a second power-on sequence is different from the first power-on sequence [a power-up sequence of first to third internal source voltages PWR1 to PWR3 may be generated in a different sequence each time a power-up operation is performed, par. 72].
It would have been obvious to one of ordinary skill in the art, having the teachings of OH, LI, BISBEE, CHAIKEN, and KIM before him before the effective filling date of the claimed invention, to incorporate a second power-on sequence different from a first power-on sequence as taught by KIM into the storage system as taught by OH in view of LI, BISBEE, and CHAIKEN in order to incorporate generating internal source voltages in order for a peak current of a power-up current to be equally distributed [KIM par. 5].
Regarding Claim 18, OH in view of LI, BISBEE, CHAIKEN, and KIM teaches the device of Claim 16 as applied above. The remainder of claim 18 recites limitations similar to those of claim 8, and is rejected accordingly.
Regarding Claim 19, OH in view of LI, BISBEE, CHAIKEN, and KIM teaches the device of Claim 16 as applied above. The remainder of claim 18 recites limitations similar to those of claim 11, and is rejected accordingly.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over LI in view of CHAIKEN, KIM, and BISBEE
Regarding Claim 20, LI discloses an electronic device (storage system 400, FIG. 4) comprising: a host device configured to generate a main voltage and an auxiliary voltage (host device 410 of storage system 400 receives external voltage from power supply 430 ([0103]) and supplies two voltages through first power supply unit 441 and second power supply unit 442, FIG. 4, [0100];
and a storage device (storage device 420 part of storage system 400, FIG. 4) including:
a storage controller, a power supply circuit configured to receive the main voltage, and a micro controller configured to receive the auxiliary voltage (main controller 423 (i.e. storage controller and power supply circuit) and micro control unit 421 of storage device 420 receive power from first power supply unit 441 and second power supply unit 442 respectively, FIG. 4, [0100]).
wherein the micro controller is separate from the storage controller [MCU 421 (i.e. micro controller) and main controller 423 (i.e. storage controller and power supply circuit) are separate components in storage apparatus 420, FIG. 4].
LI does not explicitly disclose wherein the micro controller is further configured to: execute a first power-on sequence based on the auxiliary voltage; detect a power failure corresponding to the power-on sequence; and perform a second power-on sequence in response to detecting the power failure, wherein the second power-on sequence is different from the first power-on sequence and wherein the storage device is configured to sequentially activate a plurality of power blocks of the power supply circuit depending on an enablement order defined in the first power-on sequence.
However, in the analogous art of power management, CHAIKEN teaches wherein the micro controller (embedded controller EC 150) is further configured to: execute a first power-on sequence based on the auxiliary voltage (EC 150 executes a power-on sequence after being powered on by one of multiple operating voltages supplied to various IHS 100 components, FIG. 1, [0039-0040]);
detect a power failure corresponding to the power-on sequence (EC 150 detects a no power failure while executing the power-on sequence, FIG. 3, Step 220, [0051-0052]);
and perform the power-on sequence in response to detecting the power failure (in response to the no power failure, EC 150 resets Real-Time Clock RTC 160 and power cycles the system to restart the boot (power-on) sequence, FIG. 3, Steps 220-250, [0052]).
It would have been obvious to one of ordinary skill, having the teachings of LI and CHAIKEN before him before the effective filing date of the claimed invention, to incorporate a controller configured to execute power on, detect a power failure, and reboot after power failure as taught by CHAIKEN into the device as disclosed by LI in order to enable a controller with the capability to resolve power failures (CHAIKEN, [0004]).
LI in view of CHAIKEN does not explicitly teach wherein the second power-on sequence is different from the first power-on sequence and wherein the storage device is configured to sequentially active a plurality of power blocks of the power supply circuit depending on an enablement order defined in the first power-on sequence.
However, in the analogous art of power up circuits, KIM teaches wherein a second power-on sequence is different from the first power-on sequence [a power-up sequence of first to third internal source voltages PWR1 to PWR3 may be generated in a different sequence each time a power-up operation is performed, par. 72],
It would have been obvious to one of ordinary skill in the art, having the teachings of LI, CHAIKEN, and KIM before him before the effective filling date of the claimed invention, to incorporate a second power-on sequence different from a first power-on sequence as taught by KIM into the method as taught by LI in view of CHAIKEN in order to incorporate generating internal source voltages in order for a peak current of a power-up current to be equally distributed [KIM par. 5].
LI in view of CHAIKEN and KIM does not explicitly teach wherein the storage device is configured to sequentially active a plurality of power blocks of the power supply circuit depending on an enablement order defined in the first power-on sequence.
However, in the analogous art of power management, BISBEE teaches the storage device is configured to sequentially active a plurality of power blocks of the power supply circuit depending on an enablement order defined in the power-on sequence (programmable control and monitoring chip CMD 44 is programmed to sequentially activate voltage-generating POL convertors 46 1-46 n dependent on an enable signal EN, FIG. 3, Column 5 Lines 35-42).
It would have been obvious to one of ordinary skill, having the teachings of LI, CHAIKEN, KIM, and BISBEE before him before the effective filing date of the claimed invention, to incorporate a controller configured to sequentially power on power blocks dependent on an enablement order as taught by BISBEE into the device as taught by LI in view of CHAIKEN and KIM in order to enable the power supply circuit to sequentially generate different voltages by using power blocks (BISBEE, Column 1 Lines 56-60).
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSUE L RODRIGUEZ whose telephone number is (571)272-8927. The examiner can normally be reached Monday-Friday 9am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.L.R./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
Prosecution Insights