Detailed Action
The instant application having Application No. 18/883,151 has a total of 18 claims pending in the application; there are 3 independent claims and 15 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 3/17/26. Claims 1-6, 8-15 and 17-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (U.S. Patent Application Publication No. 2018/0329651 herein referred to as Chang et al. in view of Patsilaras et al. (U.S. Patent Application Publication No. 2015/0293847), herein referred to as Patsilaras et al.
Referring to claim 1, Chang et al. disclose as claimed, an electronic device comprising: a memory; and a processor connected to the memory and configured to execute at least one instruction (see para. 44-51, where an NVDIMM, containing both volatile and non-volatile memory, is coupled to a host processor and receives commands), wherein the processor executes the at least one instruction to transmit indicator information to the memory, wherein the indicator information identifies one or more memory areas (see para. 98, giving an example of a PWRITE command which includes a memory address, write group ID and a persist flag. The persist flag is used to set the valid and dirty bits), among a plurality of memory areas included in the memory, where useless data is stored (see para. 75, explaining that an invalid state indicates that the value can be ignored. Also see para. 72, where when data is not marked as persistent, there is not writeback of the data in response to a PWRITE or FLUSH command), each of the plurality of memory areas comprises a first bit, a second bit, and a third bit. The first bit is a valid bit, and the valid bit indicates if the memory area is valid and the second bit is a dirty bit, and the dirty bit indicates if data stored in the memory area has been modified (see page 6, Table 1 and Table 2, as well as para. 75 explaining the valid and dirty bits. See para. 75, where a third bit may be the persist bit); and the memory skips a writeback for the one or more memory areas, in response to the indicator information (see para. 70 and para. 93, where when the state of the cache line is invalid or not persistent, the memory skips a writeback. Also see table 1 and table 2 on page 6).
Chang et al. disclose the claimed invention except for where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data
However, Patsilaras et al. disclose where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data (see para. 4, where a no-writeback bit in a cache line is set to indicate that a cache line is not to be written back to a memory upon eviction of a cache line. See para. 26, where this data is ephemeral data that has seen its last use and can be replace, and would therefore be useless data)
Chang et al. and Patsilaras et al. are analogous art because they are from the same field of endeavor of cache memory (see Chang et al., abstract, and Patsilaras et al., abstract, regarding cache memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang et al. to comprise where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data, as taught by Patsilaras et al., in order to save power and memory bandwidth (see Patsilaras et al., para. 2 and 26, where not writing back ephemeral or useless data may save power and memory bandwidth).
As to claim 2, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 1, wherein each of the plurality of memory areas comprises a valid bit and a dirty bit, wherein the valid bit indicates if the memory area is valid, and the dirty bit indicates if data stored in the memory area has been modified (see Chang et al., page 6, Table 1 and Table 2, as well as para. 75 explaining the valid and dirty bits).
As to claim 3, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 2, wherein the indicator information is used to set the valid bit, included in at least one of the memory areas, to logic low to indicate that the at least one memory area is invalid (see Chang et al., para. 74-75 and Table 2, showing that logic low signifies invalid data. See para. 98, where the persist flag may also be set low which may be used to set valid and dirty bits).
As to claim 4, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 2, wherein the indicator information is used to set the dirty bit, included in at least one of the memory areas, to logic low to indicate that the data stored in the at least one memory area is not modified (see Chang et al., para. 77, giving an example of an eviction which changes the dirty bit to logic low to signify that the memory area is not modified).
As to claim 5, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 4, wherein the memory is configured to: receive a request that requires the writeback for the at least one memory area from the processor; and skip the writeback that was requested and clear the at least one memory area, when the dirty bit is logic low (see Chang et al., para. 70-72, where in response to a flush or writeback, the writeback is skipped if the dirty bit is low. See page 6, Table 1, showing an Evict command).
As to claim 6, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 5, wherein the useless data is modified or unmodified data (see Chang et al., page 6, Table 2 and para. 75, showing that invalid data has a dirty bit value of X, which means the value may be ignored and could be either modified or unmodified).
As to claim 13, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 1, further comprising: a useless data detector configured to determine whether an access to the memory is associated with the useless data, by comparing a register associated with the useless data and an address of the access to the memory (see Chang et al., para. 48, where the metadata cache is implemented using SRAM, which uses flip-flops or registers to store data. See para. 67-75, where the different states of each entry are used to determine if the data is invalid or useless and whether a writeback is necessary).
As to claim 14, Chang et al. and Patsilaras et al. also disclose the electronic device of claim 1, wherein the useless data is data based on a dynamic allocation of the one or more memory areas after being released (see Chang et al., para. 67, where flushing is redundant and not necessary after cache eviction or releasing memory. Also see para. 70, where after releasing memory or cache eviction, there is no need to write invalid or useless data).
Referring to claim 15, Chang et al. disclose as claimed, a method of operating an electronic device, the method comprising: checking whether data stored in one or more memory areas, among a plurality of memory areas included in a memory, is useless data (see para. 75, explaining that an invalid state indicates that the value can be ignored. Also see para. 72, where when data is not marked as persistent, there is not writeback of the data in response to a PWRITE or FLUSH command. Therefore data stored in memory areas is checked to make sure it is valid or invalid); and transmitting indication information associated with the one or more memory areas to the memory, based on the checking of the useless data (), wherein the indicator information is used to skip a writeback for the one or more memory areas (see para. 70 and para. 93, where when the state of the cache line is invalid or not persistent, the memory skips a writeback. Also see table 1 and table 2 on page 6); each of the plurality of memory areas comprises a first bit, a second bit, and a third bit. The first bit is a valid bit, and the valid bit indicates if the memory area is valid and the second bit is a dirty bit, and the dirty bit indicates if data stored in the memory area has been modified (see page 6, Table 1 and Table 2, as well as para. 75 explaining the valid and dirty bits. See para. 75, where a third bit may be the persist bit);
Chang et al. disclose the claimed invention except for where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data
However, Patsilaras et al. disclose where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data (see para. 4, where a no-writeback bit in a cache line is set to indicate that a cache line is not to be written back to a memory upon eviction of a cache line. See para. 26, where this data is ephemeral data that has seen its last use and can be replace, and would therefore be useless data)
Chang et al. and Patsilaras et al. are analogous art because they are from the same field of endeavor of cache memory (see Chang et al., abstract, and Patsilaras et al., abstract, regarding cache memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang et al. to comprise where the third bit is a useless bit, and the useless bit indicates if the data stored in the memory is the useless data, as taught by Patsilaras et al., in order to save power and memory bandwidth (see Patsilaras et al., para. 2 and 26, where not writing back ephemeral or useless data may save power and memory bandwidth).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Normoyle et al. (U.S. Patent No. 6,477,622), herein referred to as Normoyle et al.
Referring to claim 20, Chang et al. disclose as claimed, an electronic device comprising: a first memory; a processor connected to the first volatile memory and configured to execute at least one instruction (see para. 44-51, where an NVDIMM, containing both a volatile and non-volatile memory is coupled to a host processor and receives commands); and a second memory (see para. 67, where a volatile or first memory may flush a cache line to non-volatile memory, or second memory), wherein the processor executes the at least one instruction to transmit indicator information to the memory, wherein the indicator information identifies one or more memory areas (see para. 98, giving an example of a PWRITE command which includes a memory address, write group ID and a persist flag. The persist flag is used to set the valid and dirty bits), among a plurality of memory areas included in the first memory, where useless data is stored (see para. 75, explaining that an invalid state indicates that the value can be ignored. Also see para. 72, where when data is not marked as persistent, there is not writeback of the data in response to a PWRITE or FLUSH command), and the first volatile memory skips a writeback to the second memory from the one or more memory areas, in response to the indication information (see para. 70 and para. 93, where when the state of the cache line is invalid or not persistent, the memory skips a writeback. Also see table 1 and table 2 on page 6).
Chang et al. disclose the claimed invention except for where the second memory is a volatile memory.
However, Normoyle et al. disclose where the second memory is a volatile memory. (see col. 3, lines 22-42, where the main memory is a volatile memory such as a DRAM and the main cache may preferably be an SRAM).
Chang et al. and Normoyle et al. are analogous art because they are from the same field of endeavor of cache memory (see Chang et al., abstract, and Normoyle et al., abstract, regarding cache memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang et al. to comprise where the second memory is a volatile memory., as taught by Normoyle et al., in order to allow for faster access and greater endurance. The benefits of volatile memory vs non-volatile memory (flash) are well known in the art and would be an obvious implementation to add them to Chang et al.
Claims 8-12 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Patsilaras et al. and in view of Hoogerbrugge (U.S. Patent Application Publication No. 20090150619), herein referred to as Hoogerbrugge.
As to claim 8, Chang et al. and Patsilaras et al. disclose the claimed invention except for the electronic device of claim 7, wherein the indicator information is used to set the useless bit, included in at least one of the memory areas, to logic high to indicate that the data stored in the at least one memory area is the useless data.
However, Hoogerbrugge discloses wherein the indicator information is used to set the useless bit, included in at least one of the memory areas, to logic high to indicate that the data stored in the at least one memory area is the useless data (see para. 24-27, where an invalid bit being set, or “set to high” means that the data is invalid).
Chang et al. and Hoogerbrugge are analogous art because they are from the same field of endeavor of cache memory (see Chang et al., abstract, and Hoogerbrugge, abstract, regarding cache memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang et al. to comprise wherein the indicator information is used to set the useless bit, included in at least one of the memory areas, to logic high to indicate that the data stored in the at least one memory area is the useless data, as taught by Hoogerbrugge, in order to maintain cache coherency for multiple memories and caches (see Hoogerbrugge, para. 6). In addition, it would be obvious to utilize a logic high instead of a logic zero to indicate invalidity or useless data, as that is simply another method to accomplish the same result that one of ordinary skill in the art would know to utilize.
As to claim 9, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the electronic device of claim 8, wherein the memory is configured to: receive a request that requires the writeback for the at least one memory area from the processor; and skip the writeback that was requested and clear the at least one memory area, when the useless bit is logic high (see Chang et al., para. 70-71, where an eviction would normally require a flush, except where the data is invalid, in which case the writeback is skipped, and the slate is clean. Also see para. 77, where after data is evicted, the state is transitioned to clean. See Hoogerbrugge, para. 24-28, which teaches that invalidity can be shown with a logic high).
As to claim 10, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the electronic device of claim 8, wherein the processor executes the at least one instruction to set the useless bit to logic low to indicate that the data stored in each of the plurality of memory areas is not the useless data, when the useless bit is set to logic high and a write access to the at least one memory area is being performed (see Chang et al., para. 98, giving an example of a PWRITE command in a persist state which sets the valid and dirty states to valid and dirty. See Hoogerbrugge, para. 24-28, which teaches that invalidity can be shown with a logic high).
As to claim 11, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the electronic device of claim 8, wherein the processor executes the at least one instruction to determine whether the read access requires eviction or flushing, when the useless bit is set to logic high and a read access to the at least one memory area is being performed (see Hoogerbrugge, para. 23-27, where in a read operation, it is determined whether the data is invalid, and if so, processors that hold the data in a modified state must send the modified data back to the local memory, which would be a flush or eviction. When combined with Chang et al., which teaches in para. 69-70 and 77, where it is determined if an eviction is performed as opposed to a flush command, this would allow determining after a read whether an eviction or flush is necessary).
As to claim 12, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the electronic device of claim 11, wherein the processor executes the at least one instruction to set the valid bit to logic low to indicate that the at least one memory area is invalid, in response to the read access that requires the eviction or the flushing and the dirty bit is set to logic high (see Chang et al., para. 77, where during an eviction, the metadata may indicate a dirty bit and an invalid bit before later being changed to a clean state).
As to claim 17, Chang et al. and Patsilaras et al. disclose the claimed invention except for the method of claim 16, wherein the indicator information is used to set the useless bit, included in at least one of the memory area, to logic high to indicate that the data stored in the at least one memory area is the useless data.
However, Hoogerbrugge discloses wherein the indicator information is used to set the useless bit, included in at least one of the memory areas, to logic high to indicate that the data stored in the at least one memory area is the useless data (see para. 24-27, where an invalid bit being set, or “set to high” means that the data is invalid).
Chang et al. and Hoogerbrugge are analogous art because they are from the same field of endeavor of cache memory (see Chang et al., abstract, and Hoogerbrugge, abstract, regarding cache memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang et al. to comprise wherein the indicator information is used to set the useless bit, included in at least one of the memory areas, to logic high to indicate that the data stored in the at least one memory area is the useless data, as taught by Hoogerbrugge, in order to maintain cache coherency for multiple memories and caches (see Hoogerbrugge, para. 6). In addition, it would be obvious to utilize a logic high instead of a logic zero to indicate invalidity or useless data, as that is simply another method to accomplish the same result that one of ordinary skill in the art would know to utilize.
As to claim 18, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the method of claim 17, further comprising: determining whether the useless data is logic high; determining whether an access to the at least one memory area is a write access, when the useless data is logic high (see Chang et al., para. 98, giving an example of a write access, and see para. 70-75, showing where the useless data may be invalid and showing different responses depending on the status); and determining whether a write access requires eviction or flushing, when the access is the write access (see Chang et al., para. 69-70 and 77, where it is determined if an eviction is performed as opposed to a flush command. See para. 67, where an eviction may be necessary when the cache is full).
As to claim 19, Chang et al., Patsilaras et al. and Hoogerbrugge also disclose the method of claim 18, further comprising: determining whether the dirty bit is set to logic high to indicate that the data stored in the at least one memory area has been modified (see Chang et al., para. 70-75, where a dirty bit being high indicates that the data is dirty and therefore has been modified), in response to a read access that requires the eviction or the flushing; and setting the valid bit to logic low to indicate that the at least one memory area is invalid, when the dirty bit is set to logic high (see Chang et al. para. 77, where after data is evicted, the values of the metadata may be changed from invalid and dirty to valid and clean. Therefore, prior to the clean state, the metadata would show that the memory area is invalid and dirty).
Response to Arguments
Applicant’s arguments, filed 3/17/26, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Patsilaras et al. and Normoyle et al.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-6, 8-15 and 17-20 stand rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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